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SN74HC573N PDF
SN74HC573N PDF
SCLS147E DECEMBER 1982 REVISED SEPTEMBER 2003
D
D
D
D
19
18
17
16
15
14
13
12
10
11
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
3D
4D
5D
6D
7D
OE
VCC
1Q
20
2D
1D
SN54HC573A . . . FK PACKAGE
(TOP VIEW)
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
2Q
3Q
4Q
5Q
6Q
8D
GND
LE
8Q
7Q
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
Typical tpd = 21 ns
6-mA Output Drive at 5 V
Low Input Current of 1 A Max
Bus-Structured Pinout
description/ordering information
These octal transparent D-type latches feature 3-state outputs designed specifically for driving highly capacitive
or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
While the latch-enable (LE) input is high, the Q outputs respond to the data (D) inputs. When LE is low, the
outputs are latched to retain the data that was set up.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
ORDERING INFORMATION
PDIP N
SN74HC573AN
Tube of 40
SN74HC573ADW
Reel of 2500
SN74HC573ADWR
Reel of 2000
SN74HC573ADBR
Reel of 2000
SN74HC573APWR
Reel of 250
SN74HC573APWT
CDIP J
Tube of 25
SNJ54HC573AJ
SNJ54HC573AJ
CFP W
Tube of 150
SNJ54HC573AW
SNJ54HC573AW
LCCC FK
Tube of 55
SNJ54HC573AFK
SSOP DB
TSSOP PW
55C
55
C to 125
125C
C
TOP-SIDE
MARKING
Tube of 25
SOIC DW
40C to 85C
ORDERABLE
PART NUMBER
PACKAGE
TA
SN74HC573AN
HC573A
HC573A
HC573A
SNJ54HC573AFK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
LE
OUTPUT
Q
Q0
1
11
C1
1D
19
1Q
1D
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA
Package thermal impedance, JA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
SCLS147E DECEMBER 1982 REVISED SEPTEMBER 2003
Supply voltage
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
VCC = 2 V
VIL
VI
VO
tt
MIN
NOM
MAX
Input voltage
MAX
3.15
3.15
4.2
4.2
VCC = 6 V
UNIT
V
0.5
0.5
1.35
1.35
1.8
1.8
VCC
VCC
VCC = 2 V
VCC = 4.5 V
NOM
1.5
Output voltage
MIN
1.5
VCC = 4.5 V
VCC = 6 V
SN74HC573A
VCC
VCC
1000
1000
500
500
400
400
V
V
V
ns
TA
Operating free-air temperature
55
125
40
85
C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
VOH
VOL
TEST CONDITIONS
VI = VCC or 0,
MIN
MAX
SN74HC573A
MIN
MAX
UNIT
1.9
1.998
1.9
1.9
IOH = 20 A
4.4
4.499
4.4
4.4
6V
5.9
5.999
5.9
5.9
IOH = 6 mA
IOH = 7.8 mA
4.5 V
3.98
4.3
3.7
3.84
6V
5.48
5.8
5.2
5.34
2V
0.002
0.1
0.1
0.1
IOL = 20 A
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
6V
0.15
0.26
0.4
0.33
6V
0.1
100
1000
1000
nA
6V
0.01
0.5
10
160
80
10
10
10
pF
IOL = 6 mA
IOL = 7.8 mA
ICC
Ci
SN54HC573A
2V
VI = VIH or VIL
VI = VCC or 0
VO = VCC or 0
TA = 25C
MIN
TYP
MAX
4.5 V
VI = VIH or VIL
II
IOZ
VCC
IO = 0
6V
2 V to 6 V
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
tw
tsu
th
TA = 25C
MIN
MAX
SN54HC573A
MIN
MAX
SN74HC573A
MIN
2V
80
120
100
4.5 V
16
24
20
6V
14
20
17
2V
50
75
63
4.5 V
10
15
13
6V
13
11
2V
20
24
24
4.5 V
6V
MAX
UNIT
ns
ns
ns
FROM
(INPUT)
ten
tdis
tt
OE
OE
SN54HC573A
SN74HC573A
VCC
2V
77
175
265
220
4.5 V
26
35
53
44
6V
23
30
45
38
2V
87
175
265
220
4.5 V
27
35
53
44
6V
23
30
45
38
2V
68
150
225
190
4.5 V
24
30
45
38
6V
21
26
38
32
2V
47
150
225
190
4.5 V
23
30
45
38
6V
21
26
38
32
2V
28
60
90
75
4.5 V
12
18
15
6V
10
15
13
tpd
LE
TA = 25C
MIN
TYP
MAX
TO
(OUTPUT)
Any Q
Any Q
Any Q
Any Q
MIN
MAX
MIN
MAX
UNIT
ns
ns
ns
ns
SCLS147E DECEMBER 1982 REVISED SEPTEMBER 2003
SN54HC573A
SN74HC573A
TO
(OUTPUT)
VCC
2V
95
200
300
250
4.5 V
33
40
60
50
6V
21
34
51
43
2V
103
225
335
285
4.5 V
33
45
67
57
6V
29
38
57
48
tpd
LE
ten
TA = 25C
TYP
MAX
FROM
(INPUT)
Any Q
OE
Any Q
tt
Any Q
MIN
MIN
MAX
MIN
MAX
2V
85
200
300
250
4.5 V
29
40
60
50
6V
26
34
51
43
2V
60
210
315
265
4.5 V
17
42
63
53
6V
14
36
53
45
UNIT
ns
ns
ns
TEST CONDITIONS
No load
TYP
50
UNIT
pF
Test
Point
From Output
Under Test
ten
RL
tPZH
RL
CL
50 pF
or
150 pF
1 k
tPZL
tdis
S2
tPLZ
1 k
50 pF
50 pF
or
150 pF
tpd or tt
LOAD CIRCUIT
50%
Closed
Closed
Open
Open
Closed
Closed
Open
Open
Open
50%
0V
50%
tsu
0V
tw
Data
50%
Input 10%
VCC
Low-Level
Pulse
50%
50%
50%
0V
tPLH
50%
10%
tPHL
90%
90%
tr
tPHL
90%
tf
50%
10%
Output
Control
(Low-Level
Enabling)
50%
10% V
OL
tf
tPZL
Output
Waveform 1
(See Note B)
VOH
tPZH
VOH
tPLH
50%
10%
90%
90%
VCC
50%
10% 0 V
tf
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VCC
50%
th
tr
0V
VOLTAGE WAVEFORMS
PULSE DURATIONS
Out-ofPhase
Output
Open
VCC
Reference
Input
VCC
High-Level
Pulse
In-Phase
Output
S2
tPHZ
CL
(see Note A)
Input
S1
90%
VOL
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
VCC
50%
Output
Waveform 2
(See Note B)
50%
0V
tPLZ
VCC
50%
10%
VCC
VOL
tPHZ
50%
90%
VOH
0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
MCFP006B JANUARY 1995 REVISED JULY 2003
W (R-GDFP-F20)
0.300 (7,62)
0.245 (6,22)
0.045 (1,14)
0.026 (0,66)
0.009 (0,23)
0.004 (0,10)
0.100 (2,54)
0.045 (1,14)
0.320 (8,13) MAX
1
0.022 (0,56)
0.015 (0,38)
20
0.050 (1,27)
0.540 (13,72)
MAX
10
11
0.370 (9,40)
0.250 (6,35)
0.370 (9,40)
0.250 (6,35)
4040180-4 /D 07/03
NOTES: A.
B.
C.
D.
E.
MECHANICAL DATA
MLCC006B OCTOBER 1996
FK (S-CQCC-N**)
28 TERMINAL SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
22
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
52
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
25
26
27
28
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.
MECHANICAL
MPDI002C JANUARY 1995 REVISED DECEMBER 20002
N (R-PDIP-T**)
16 PINS SHOWN
PINS **
14
16
18
20
A MAX
0.775
(19,69)
0.775
(19,69)
0.920
(23,37)
1.060
(26,92)
A MIN
0.745
(18,92)
0.745
(18,92)
0.850
(21,59)
0.940
(23,88)
MS-100
VARIATION
AA
BB
AC
DIM
A
16
0.260 (6,60)
0.240 (6,10)
AD
8
0.070 (1,78)
0.045 (1,14)
0.045 (1,14)
0.030 (0,76)
0.325 (8,26)
0.300 (7,62)
0.015 (0,38)
Gauge Plane
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.010 (0,25) M
D
4040049/E 12/2002
MECHANICAL DATA
MSOI003E JANUARY 1995 REVISED SEPTEMBER 2001
DW (R-PDSO-G**)
16 PINS SHOWN
0.020 (0,51)
0.014 (0,35)
9
0.050 (1,27)
16
0.010 (0,25)
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
0.299 (7,59)
0.291 (7,39)
Gage Plane
0.010 (0,25)
1
0 8
0.050 (1,27)
0.016 (0,40)
Seating Plane
0.104 (2,65) MAX
0.012 (0,30)
0.004 (0,10)
PINS **
0.004 (0,10)
16
18
20
24
28
A MAX
0.410
(10,41)
0.462
(11,73)
0.510
(12,95)
0.610
(15,49)
0.710
(18,03)
A MIN
0.400
(10,16)
0.453
(11,51)
0.500
(12,70)
0.600
(15,24)
0.700
(17,78)
DIM
4040000/E 08/01
NOTES: A.
B.
C.
D.
MECHANICAL DATA
MSSO002E JANUARY 1995 REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
08
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
MECHANICAL DATA
MTSS001C JANUARY 1995 REVISED FEBRUARY 1999
PW (R-PDSO-G**)
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
7
0 8
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
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