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Hosono Science2
Hosono Science2
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Transparent conductive oxides such as
indium-tin oxide (ITO) and ZnO have found
applications as electrical interconnections and
as window electrodes in flat panel displays and
solar cells. The discovery of a p-type transparent oxide semiconductor (TOS), CuAlO2 (4),
and the development of key device components
fabricated from TOSs, such as pn-junction
rectifiers (5, 6) and ultraviolet light emitting
diodes (7), have led to the emergence of TOSs
as viable materials for further development of
transparent electronics.
However, the TFETs fabricated to date
using conventional TOSs such as SnO2 and
ZnO (8, 9) exhibit poor performance. For
instance, their on-to-off current ratios and
field-effect mobilities are on the order of 103
and as low as 10 cm2 V1 s1, respectively,
and the device exhibits normally-on characteristics. Although a polycrystalline ZnO
TFET has previously been found to have
normally-off characteristics with an on-tooff current ratio of 107, its field-effect mobility is only 3 cm2 V1 s1. Grain-boundary
potential barriers are thought to limit the
performance (10). The large off-current and
the normally-on characteristics may originate
from the fact that these conventional TOSs
contain many carriers in the as-prepared state
(as the result of a somewhat large nonstoichiometry in the chemical composition),
making it difficult to control the carrier density down to less than 1017 cm3 without
counterdoping of acceptors. Hence, it is imperative to choose a material that can control
the carrier concentration down to the intrinsic
level and to develop a method to grow a
high-quality single-crystalline thin film.
We report the fabrication and performance of TFETs that use a single-crystalline
film of a TOS, InGaO3(ZnO)5, for the active
channel layer. This material has advantages
over conventional TOSs, including easy
growth of a high-quality single-crystalline
film and good controllability of carrier concentration. The use of a gate insulator with a
high dielectric constant (high-k dielectric),
amorphous HfO2, was found to improve the
FET performance.
The structure of InGaO3(ZnO)5 is characterized by its layered superlattice structure
(Fig. 1A)in which InO2 layers and
GaO(ZnO)5 blocks are alternately stacked
along the 0001 axis (11, 12)and is
thought to be the origin of its superior
electronic properties. The layers are similar
to those of ITO and Ga-doped ZnO, in
1
Hosono Transparent ElectroActive Materials, Exploratory Research for Advanced Technology (ERATO),
Japan Science and Technology ( JST ), 3-2-1 Sakado,
Takatsu, Kawasaki 213-0012, Japan. 2Materials and
Structures Laboratory, Tokyo Institute of Technology,
4259 Nagatsuta, Midori, Yokohama 226-8503, Japan.
Fig. 1. Structure of InGaO3(ZnO)5. (A) Schematic of the crystal structure. A HRTEM lattice image is
shown for comparison. The InO2 layer (In3 ion locates at an octahedral site coordinated by oxygens)
and the GaO(ZnO)5 block (Ga3 and Zn2 ions share trigonal-bipyramidal and tetrahedral
sites) are alternately stacked along the 0001 direction at a period of 1.9 nm (d0003). (B and
C) Cross-sectional HRTEM images of a InGaO3(ZnO)5 thin lm grown on YSZ(111) by reactive
solid-phase epitaxy. Periodic stacking of the InO2 layer and the GaO(ZnO)5 block is clearly
visible, which is also conrmed in the electron diffraction image [(C), inset]. Single-crystalline
lm is formed over the entire observation area. The topmost layer of the lm is the InO2 layer.
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taxial layer at 700C on a (111) single-crystal
yttriastabilized zirconia ( YSZ ) substrate as
the template, followed by a 120-nm-thick
InGaO3( ZnO)5 layer at room temperature.
The resulting bilayer structure was covered
with a YSZ plate to suppress the evaporation
of film components and was then subjected to
thermal annealing at 1400C for 30 min in an
atmospheric electric furnace, resulting in the
growth of its single-crystalline phase (18).
Cross-sectional high-resolution transmission electron microscopy (HRTEM) images
of the InGaO3(ZnO)5 film (Fig. 1B) showed
the distinct layered lattice structure composed
of the periodic stacking of the InO2 layers
and GaO(ZnO)5 blocks. The film-substrate
interface is atomically flat without a reaction
layer despite the high-temperature annealing,
as confirmed by TEM energy-dispersive xray spectrum. The lattice mismatch is relaxed
in a few atomic layers at the film-substrate
interface, and field-emission scanning microscopic observation revealed no defect structure such as grain boundary and dislocation
over the entire area.
Figure 2 shows an atomic force microscope image of a single-crystalline
InGaO3(ZnO)5 thin film as fabricated, showing an atomically flat terraces-and-steps
structure. The step height (1.9 nm) corresponds to the separation between adjacent
InO2 layers in the InGaO3(ZnO)5 crystal.
The topmost layer is made of InO2, as observed by HRTEM. The film conductivity is
less than 105 S cm1. The carrier concentration is estimated to be 1013 cm3, as
derived from an electron mobility value of
80 cm2 V1 s1 (which is obtained as a
field-effect mobility).
We fabricated top-gate TFETs with the
use of a single-crystalline film grown on a 10
mm by 10 mm YSZ chip (Fig. 3A). The
source, drain, gate contacts, and gate insulator were defined by standard photolithography and lift-off techniques. An 80-nm-thick
amorphous HfO2 (a-HfO2 ) layer was used for
the gate insulator, and ITO (10% Sn) was
used for source, drain, and gate electrodes.
The ITO and a-HfO2 layers were deposited
by PLD at room temperature. The dielectric
constant of a-HfO2 films was measured to be
18, which is a reasonable value compared
with those reported previously (19). The
channel length and gate width were 50 m
and 200 m, respectively, corresponding to a
width-to-length ratio of 4 :1 (Fig. 3B). The
chip is optically transparent in the whole
visible-light region (Fig. 3B, inset). The optical transmittance is 80% in the wavelength range between 390 nm and 3200 nm
[including the effects of the YSZ(111) substrate], which indicates that transmission
losses due to the film and the TFETs are
negligible. The reproducibility of the device
characteristics was confirmed by measuring
more than 100 fabricated TFETs.
Fig. 3. (A) Illustration of the TFET device structure. The InGaO3(ZnO)5 channel layer and the
a-HfO2 gate insulator layer are 120 nm and 80 nm in thickness, respectively. Channel length and
gate width are 50 m and 200 m, respectively. (B) Optical transmission spectrum of a TFET chip.
Those of YSZ substrates with and without an InGaO3(ZnO)5 lm are given for comparison, showing
that the TFET is fully transparent to visible light. Inset: Photograph of a TFET chip placed on a
background text (left) and a magnied photograph of a TFET device (right). The light illumination
condition was tuned to make the TFET device structure visible.
Fig. 4. Typical TFET characteristics fabricated in a single-crystalline InGaO3(ZnO)5 lm. (A) Output
characteristics; (B) transfer characteristics. The TFET operates in the enhanced mode with a
threshold voltage of 3 V. A eld-effect mobility of 80 cm2 V1 s1 and an on-to-off current
ratio of 106 are obtained. The gate leak current is orders of magnitude less than the source-todrain current, which guarantees that the FET characteristics are not affected by the gate leak.
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an important factor for achieving good performance (20).
The off-current is very low, on the order of
109 A, and an on-to-off current ratio of 106
is obtained (Fig. 4B). The threshold gate voltage is 3 V, showing that the TFET operates in
the enhancement mode. These characteristics
are much improved over those reported for
TOS TFETs fabricated using SnO2 (9).
We examined the photoresponse against
the light illumination from a commercially
available 30-W fluorescent tube. A photoresponse of the off-current weaker than the
dark level (109 A) was observed under
typical room illumination conditions (1.6
W m2). At six times this intensity of illumination (10 W m2), the off-current increased only to 3 109 A.
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constructions (917), what controls the atomic arrangements within the dissociated layers
has been unclear. Resolving this issue is important because the processes that occur at
grain boundaries, such as the accommodation
of lattice strain or the segregation and diffusion of point defects and impurities, are fundamentally governed by the atomic-scale details of the interfacial structure.
Here, we consider the specific question of
how the ordering of stacking fault arrays at
dissociated grain boundaries is related to the
crystallographic orientations of the two joined
crystals. We focus on the formation of hexagonal close-packing (HCP), which is an important limiting case because it is the close-packed
arrangement that possesses the highest possible
density of stacking faults. Through atomic resolution electron microscopic observations, we
demonstrate the formation of local, intergranular regions of HCP at a grain boundary in
face-centered cubic (FCC) gold. From a detailed analysis of the topological defects required to connect this intergranular layer to the
neighboring FCC crystals, we show how these
observations, as well as the dissociated bound-