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Design of Low Power Pulsed Flip-Flop Using Sleep Transistor Scheme
Design of Low Power Pulsed Flip-Flop Using Sleep Transistor Scheme
I.
INTRODUCTION
II.
LITERATURE REVIEW
335
III.
B.
336
IV.
of the two helper sleep transistors are turned on. This makes
the output Q to be driven to any of the appropriate virtual rail
(virtual Vdd or virtual gnd). This scheme is referred to as
leakage feedback scheme since it reduced the leakage power
by operating the flip-flop in sleep mode by retaining the output
to the previous state. When operated in active mode, sleep
transistors are turned on and it works normally.
The operation in sleep mode and active mode is as per the
truth table specified in Table I. In the truth table, some
shorthand notations are used for easy understanding. The
notations are - represents no change in the state value,
? represents any level change (0 or 1), (01) represents
rising edge or positive edge trigger of the signal, and
(10) represents falling edge or negative edge of the signal.
SIMULATION RESULTS
TABLE I
TRUTH TABLE OF PROPOSED P-FF DESIGNS
CLK
?
?
(01)
(10)
?
D
?
(01)/(10)
?
?
?
Sleep
1
1
1
1
0
Q
-
Mode
Sleep
Sleep
Sleep
Sleep
Active
?
(01)
(01)
(10)
(01)/(10)
0
1
?
0
0
0
0
0
1
-
Active
Active
Active
Active
337
TABLE II
PERFORMANCE METRICS COMPARISON OF VARIOUS PTFF DESIGNS
Type of PTFF
# Transistors
# Clocked Transistors
Min. Data to Q Delay (ns)
Average Power (W)
Power Delay Product (PDP) (fJ)
ep-DCO
[6]
28
15
1.97
28.78
56.69
ip-DCO
[6]
23
10
1.68
22.13
37.17
MHLFF
[7]
19
7
1.83
35.96
65.80
CPE-PTFF
[8]
19
4
1.41
23.32
32.88
Proposed-1
(LFB-PFF)
23
4
1.39
20.54
28.55
Proposed-2
(LFF-PFF)
23
4
1.40
21.01
29.41
Table III
DATA SWITCHING ACTIVITY COMPARISON OF VARIOUS PTFF DESIGNS
Type of PTFF
Average Power (100% Activity, W)
Average Power (50% Activity, W)
Average Power (25% Activity, W)
Average Power (0% all-one, W)
Average Power (0% all-zero, W)
ep-DCO
[6]
32.23
28.78
16.00
34.26
15.47
ip-DCO
[6]
25.52
22.13
11.29
31.72
10.26
338
MHLFF
[7]
36.43
35.96
23.07
14.35
14.42
CPE-PTFF
[8]
25.67
23.32
12.30
8.41
8.42
Proposed-1
(LFB-PFF)
22.23
20.54
13.06
11.59
8.87
Proposed-2
(LFF-PFF)
22.39
21.01
12.98
14.57
8.41
Table IV
LEAKAGE POWER COMPARISON OF VARIOUS PTFF DESIGNS IN STANDBY MODE (nW)
ep-DCO
[6]
0.591
0.654
0.672
0.752
Type of PTFF
(CLK,D) = (0,0)
(CLK,D) = (0,1)
(CLK,D) = (1,0)
(CLK,D) = (1,1)
ip-DCO
[6]
0.313
0.465
0.501
0.481
70
D to Q Delay (ns)
60
50
40
MHLFF
[7]
0.318
0.302
0.429
0.418
CPE-PTFF
[8]
0.511
0.524
0.537
0.517
Proposed-1
(LFB-PFF)
0.340
0.421
0.366
0.435
Proposed-2
(LFF-PFF)
0.498
0.527
0.524
0.501
30
20
10
REFERENCES
[1]
LFBPFF
LFFPFF
ep-DCO
CPE-PTFF
ip-DCO
LFB-PFF
MHLFF
LFF-PFF
40
35
30
25
20
15
10
5
0
100%
50%
25%
0% All
Ones
Switching Activity
0% All
Zeros
V.
CONCLUSION
339
[12]
[13]
[14]
[15]
340