ARIZONA STATE UNIVERSITY

EEE 598: Serial Links

Final Project: Design of Phase Locked Loop (PLL)
Muhammad Ruhul Hasin (ASU ID: 1204162578)
Avinash Gadde (ASU ID: 1203581933)
Lun Li (ASU ID: 1204311623)
Ramachandran Sundaram (ASU ID: 1204102583)
Madhur Naredi (ASU ID: 1204142220)
Abhishek Gavankar (ASU ID: 1204115128)
Naveen Sai Jangala Naga (ASU ID: 1203574172)

Supervisor: Dr. Hongjiang Song

Design Specifications:
In this design project, we need to design a VLSI Phase-Locked Loop (PLL) circuit that is
targeted at an application shown in a VLSI high-speed I/O clock spec below:

Such a PLL should be able to generate a set of equally spaced 4-phase clocks that can be
programmable to two clock frequencies for above HS-G2 (A/B) applications.

Ck1 Ck2 Ck3 Ck4

T
26Mhz
Cki

Vc
PFD

LPF

Ck1
VCO

Ck2
Ck3
Ck4

Ckf

1/N

The key specification of the PLL for this project are as follows:

Input reference clock frequency: 26.00MHz (CMOS full-swing).

Output clock frequency 2.496Ghz or 2.912 Ghz (that is within 2000PPM of 2.9152Ghz)
(equally spaced 4-phase clocks) (with CMOS full-swing) programmable using Rate_Sel
input.
The bandwidth of the PLL is ~1Mhz.
Single 1.8 Volts supply.
0.18 um TSMC CMOS process technology.
A current reference of 10 A is also available on chip.

Introduction:
This project describes the design of a fully-integrated PLL for low power applications. PLLs are
used to generate on-chip clocks. A PLL is a feedback loop system that locks the on-chip clock
phase to the input clock from the crystal to generate a high frequency clock for on chip usage. A
series of clock buffers are used to increase the drive strength of the PLL and this can be used to
drive large loads of the circuit. PLLs are mostly used for two purposes: clock generation, and
timing recovery. For clock generation, since off-chip reference frequencies are limited by the
maximum frequency of a crystal frequency reference, a PLL receives the reference clock and
generates a high frequency clock in several Giga Hertz range. Timing recovery pertains to the
data communication between chips.

Fundamentals of PLL:
The basic block diagram of a PLL is shown in the below figure . A PLL is a closed-loop
feedback system that sets fixed phase relationship between its output clock phase and the phase
of a reference clock. A PLL tracks the phase changes that are within the bandwidth of the PLL.
A PLL also multiplies a low-frequency reference clock, to produce a high-frequency clock.

Basic Components of PLL:

The basic blocks of the PLL are :

Phase Frequency Detector

Charge Pump with loop filter

Voltage Controlled Oscillator (VCO)

Frequency Divider

Phase Frequency Detector (PFD):

The phase frequency detector (PFD) compares the phase difference between two input signals
and produces up and down signal that is proportional to the phase difference. If clock 1 leads the
clock 2 then exact phase difference is the difference between the rising edges of the up and down
signal. On the other hand, if clock 2 leads the clock 1 then phase difference is the distance
between the rising edges of the down and up signal. For the earlier case, the up signal will have a
wider pulse while down signal will have wider pulse for the later case. It is noticeable that PFD
can detect both frequency and phase of the incoming clocks. Because PFD can remember the
previous value of the up and down signal which gives us the frequency information also. This is
how PFD solves the problem of other phase detectors which would have failed if incoming
clocks have different frequency. Nonetheless, it should be mentioned that, if the phase difference
between the clocks is more than 360 degree then it cannot differentiate and it would repeat the
same pattern for the next 360 degrees. PFD gain is denoted as KPD which is IB/2 where IB is the
biasing current of the charge pump. In this project our IB is 20A which gives us KPD of 3.18.
Followings are the schematics and simulation results of PFD separately.

Figure 01: PFD complete schematic

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Figure 02: 2 input NAND

Figure 03: Transfer function of PFD

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Charge pump with loop filter:

The charge-pump circuit comprises of two switches that are driven with UP and DN outputs of
PFD. The charge-pump injects the charge into or out of the loop filter capacitor (C1). The
combination of charge-pump and C1 is an integrator that generates the average of UP (or DN)
pulses. This average voltage adjusts the frequency of the subsequent VCO circuit. Since the
VCO introduces another integrator, the loop gain of a charge-pump PLL has two poles at origin;
thus, the closed loop system is unstable. To stabilize the system, a zero, z = 1/RC1, is
introduced in the loop gain by adding a resistor, R, in series with C1.

Figure 04: 2nd order Charge pump with loop filter [1]
The PFD, charge pump and filter are often modeled with a linear continuous-time model. In
reality, the PFD acts as a pulse modulator system and drives the charge-pump for the duration of
pulse width which is equal to PFD input phase difference, . The actual phase response is not
linear because phase is cyclical. Furthermore, the phase information is discrete, sampled at the
clock reference frequency However, a linear continuous-time approximation is often used to
model the stability of an operating point. The error due to approximation is negligible if the PLL
bandwidth is 1/10th or smaller than the reference clock frequency .The reference frequency
determines the rate that PFD output is refreshed. With a linear approximation, Vc is equal to:
where Vc (s)/ = (IB/2) F(s); F(s) is the transfer function of the loop filter and IB is biasing
current of the charge pump. F(s) = (1/sC1) *(1+sRC1).

The charge pump has two gain components which are KP and KI where KP = R and KI = 1/sC1.
Our loop bandwidth specification is around 1 MHz and we know loop bandwidth

. Considering this equation, we calculated the KP = R = 26.5 k and KI = 1/C1 =

1/(5.24 pF) = 190.84 G to get acceptable loop bandwidth, when KPD = 3.18, KVCO = 24.57 G
rad/V-sec and N = 112. Followings are the simulation results for the charge pump with loop filter
when connected to a PFD output signals.

Figure 05: Whole schematic of loop filter with charge pump

Figure 06 (a): Control voltage Vc when ck1 leads ck2

Figure 06 (b): Control voltage Vc when ck2 leads ck1

Voltage Controlled Oscillator (VCO):

An oscillator is an autonomous system that generates a periodic output without any input. In this
project we have used a CMOS ring oscillator to generate high frequency clock signals. VCO is
controlled by the control voltage Vc coming from the loop filter. Ring oscillator based VCO has
three major components which are biasing circuit, bias buffer and VCDL (voltage controlled
delay line) elements. Biasing circuit is operated by an operational amplifier (Op-Amp) which
takes the control voltage Vc (from the loop filter) as an input. The Op-Amp modulates the tail
current source and the rail PMOS device to get the desired output voltage. This gate voltage of
the tail current source is connected to the gates of tail current sources of all subsequent VCDL
elements. Main purpose of the bias buffer is to separate the input side from the VCDL elements
such that any abrupt change in the input side does not affect the output signals. In each VCDL
element, two PMOS are connected in parallel, one of which is diode connected and the other one
is operated in the linear region so that it acts like a variable resistor. This variable resistance of
the PMOS is controlled indirectly by control voltage Vc to get the desired oscillation. Here,
phase oscillation is equal to

VCO = KVCO .Vc. dt; where KVCO is the gain of the VCO. Ideally,

for the linear analysis to apply over a large frequency range, KVCO, needs to be relatively
constant. KVCO is the found by sweeping the control voltage and observing the corresponding
output oscillation frequency. f/VC is the KVCO of that particular VCO. For our project the value
of KVCO is 24.57 G rad/V-sec. Followings are the schematics and simulated results of the VCO.

Figure 07: Complete schematic of the VCO

Figure 08: Biasing circuit and bias buffer of the VCO

Figure 09: Four fully differential VCDL element

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Figure 10: Internal circuit of the Op-Amp

Figure 11: Each stage of VCDL element

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At the output of the VCO, the signal swing is not rail to rail. That is why additional set of buffers
are used at each output to generate rail to rail swinging clock signals.

Figure 12: Schematic of full swing buffer of VCO

Figure 13: Four equally spaced clock pulses at 2.9 GHz for Vc = 0.55 V

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Figure 14: Four equally spaced clock pulses at 1.66 GHz for Vc = 0.9 V

Figure 15: VCO frequency tuning curve showing the KVCO to be 2*3.91 G rad/V-sec.

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Frequency Divider (FD):

In PLL design, frequency divider is needed to divide the high frequency clock signal and feed it
back to the input of the PFD which should have the same frequency as the input clock. In this
project, we designed a frequency divider circuit as shown in the schematic below which
performs frequency division by 96 and 112 based on the Select signal(S).

F/6 Divider

F/2 Divider
F/8 Divider
2:1 MUX
F/7 Divider

Figure 16: Schematic of Divide by 96 and 112 Frequency Divider

This Frequency divider circuit is implemented using three blocks The first block is an F/8 stage
whose output frequency is one eighth the input frequency. The F/8 division was implemented as
per the schematic below:

Figure 17: Schematic of Divide by 8-Frequency Divider

The second block has both F/6 and F/7 stages implemented separately and the output signals
with frequency F/6 and F/7 are inputs to a multiplexer. Based on the select signal(S) in the
multiplexer, it performs a frequency division of either F/6 or F/7.
Divide by 6 Frequency Divider Implementation: In the following circuit using an extra Flip
Flop and a NAND gate instead of an inverter in the first stage (as in F/4 frequency divider )we
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get two stretch cycles 0 and 1 on Q2,when Qx=0 which makes the circuit as a frequency
divider by 6.

Figure 18: Schematic of Divide by 6-Frequency Divider

Figure 19:Output plot of divide by 6 FD

Plot showing Frequency division by 6 using the schematic above: Input CLK Time period =
3.205ns and Output CLK Time period = 19.25ns (3.205*6)
Divide by 7 Frequency Divider Implementation: In the following circuit using four
synchronous TSPC D Flip-flops and a NAND gate we implement frequency division by 7.

Figure 20: Schematic of Divide by 7-Frequency Divider

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Figure 21:Output plot of divide by 7 FD

Plot showing Frequency division by 7 using the schematic above: Input CLK Time period =
3.205ns and Output CLK Time period = 22.43ns (3.205*7).
The third block has an F/2 stage which is implemented as a last stage to make sure the duty cycle
of the output clocks to be 50 percent.
Integrating the above three blocks, we obtain a Frequency division of 96 or 112 based on the
clock frequency and select signal.

Figure 22:Output plot of complete FD (2.496 GHz)

Plot showing Frequency division by 96. Input CLK Time period = 400.7ps (2.496GHz) and
Output CLK Time period = 38.47ns (400.7ps*96 or 26MHz).

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Figure 23:Output plot of complete FD (2.912 GHz)

Plot showing Frequency division by 112 Input CLK Time period = 343.4ps (2.912GHz) and
Output CLK Time period = 38.47ns (343.54ps*112 or 26MHz).

Figure 24:Schematic of the TSPC register

The flip-flop is the core part to design to satisfy high frequency operation. True Single Phase
Clock FF is chosen for its fast response. However, the sizing for the TSPC needs to be done very
carefully.

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Complete Phase locked loop (PLL) simulation:

In this project, we have designed a second order PLL which can generate output frequency of
2.496 GHz and 2.912 GHz. The control loop of second order PLL is given below:

Figure 25: Control loop of second order PLL [2]

This can be simplified into the following diagram.

Figure 26: Simplified Control loop [2]

Loop Bandwidth, Quality factor and Damping factor:
Here

n =

1/Q =

; which is the loop bandwidth and Q is the quality factor of the PLL;
= 2, is the damping factor. For our case the loop bandwidth is 1.29 MHz

and Quality factor is 0.62, damping factor is 0.80 when N = 112 and M = 1. Now complete
schematic and simulation results are shown below.

Figure 27: Schematic of complete PLL

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Figure 28: VCO output pulse frequency is 2.497 GHz and frequency divider output is 26 MHz
(when control bit S = 0)

Figure 29: Cki and Cko are locked as seen and Vc is settled; ck4 (2.496 GHz) is the output of
VCO (when S = 0)

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Figure 30: VCO output pulse frequency is 2.912 GHz and frequency divider output is 26 MHz
(when S = 1)

Figure 31: Cki and Cko are locked as seen and Vc is settled; ck4 (2.912 GHz) is the output of
VCO (when S = 1)
Figure 30 and 31 showed the locked states of the PLL for two different rates. Figure 32 shows
the all four equally spaced clock signals at 2.91 GHz. The phase difference between each
consecutive clocks should be aournd 85.85 ps (period/4) which is seen from the figure.

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Figure 32: Four equally spaced clocks at 2.91 GHz for Vc = 0.55 V

Figure 33: Four equally spaced clock pulses at 1.66 GHz for Vc = 0.9 V

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Key performance results:

Now all the key performance parameters will be shown in this section.
i) Jitter:
Here Jitter is the variation of time period of the high frequency clock output. For example, the
clock signal of 2.912 GHz should have a period of 343.4 ps. Any variation from that period is the
jitter. Following is the Jitter plot when frequency of the output clock is 2.912 GHz.

Figure 34: Absolute jitter plot when clock frequency is 2.912 GHz
Similarly, when clock frequency is 2.496 GHz, the absolute jitter plot is given below

Figure 35: Absolute jitter plot when clock frequency is 2.496 GHz
Following table shows the mean and standard deviation (STD) of absolute jitter (AJ), periodic
jitter (PJ) and cycle to cycle jitter (CCJ) for two different frequencies.

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Frequency
Of clock
2.912 GHz

AJ mean
(ps)
7.72516E-3

PJ mean
(ps)
7.76398E-5

CCJ mean
(ps)
3.88199E-5

AJ STD
(ps)
4.63928E-01

PJ STD
(ps)
2.11788E-01

CCJ STD
(ps)
2.1601E-01

2.496 GHz

1.97478E-1

1.63766E-4

9.24545E-1

7.1756E-1

8.54621E-1

Figure 36: Eye diagram of Clock 1 (wide open eye, less jitter)
ii) Phase Spacing Error (PSE):
Ideally the four output clocks must be 90 degree apart from each other. Any variation from that
ideal value is called phase spacing error (PSE). For clock frequency of 2.912 GHz, consecutive
clocks must be 85.85 ps apart from each other. Followings are the PSE plots when clock
frequency is 2.912 GHz.

Figure 37: Phase spacing error plot between clock 1 and clock 2
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Figure 38: Phase spacing error plot between clock 2 and clock 3

Figure 39: Phase spacing error plot between clock 3 and clock 4
Following is the table showing all the mean and standard deviation (STD) value for the three
different sets of PSE when frequency is 2.912 GHz.
Clocks
involved
ck1 and
ck2
ck2 and
ck3
ck3 and
ck4

PSE mean
(ps)
1.47035

PSE STD
(ps)
1.14599E-1

1.49221E-1

1.2382E-1

3.9462

1.6123E-1

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It is noticeable here that the PSE between clock 3 and clock 4 is slightly higher than the other
sets values. This is because, clock 4 has a load to drive (frequency divider) while others do not
have anything to drive.
Power Dissipation:
Total power dissipation is the average current times the supply voltage. So the average current
calculated is shown in the following figure.

Figure 39: Average current from the whole PLL circuit

So, total power dissipation = 1.8 * .0045665 = 8.22 mW.
Behavioral (s-domain) PLL counterpart:
This section covers all the analysis of the PLL in s-domain. Models of second order PLL from
EEE598Lib has been used to do all the simulations. For our project, followings are the all gain
values:
KPD = 3.18; KVCO = 24.57 G rad/V-sec; KI = 190.84 G; KP = 26.5k; N = 112.
The derivation of these values are already shown individually in each corresponding section.
Overall Loop Response:
To find out the overall loop response, following block has been used. The transfer function of
second order PLL is
1
S 1
where S = s/n. Values of n and Q
o
Q
H ( s)
i S 2 1 S 1
Q
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are given at the beginning of complete PLL section.

Figure 40: Loop response test bench

Figure 41: Internal block diagram of the second order PLL system with the gain values

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Figure 42: Overall Loop response of the PLL showing the bandwidth to be 1.29 MHz.
Previously calculated Quality factor, Q = 0.62 and damping factor, = 0.80.
S-domain noise response:
PLL can have three nodes at which noise can be injected. Those models and simulations are
shown below.

Figure 43: Test bench for noise response measurement

Figure 43 shows the setup for measuring noise response when noise injected at the PFD. Other
noise injection nodes and inputs are grounded to when noise at node n1 is measured. Same
concept has been applied while measuring the noise at node n2 and n3.
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Figure 44: Internal block diagram of the second order PLL system with noise injection nodes
1
S 1
If noise is injected at the PFD then the noise transfer function is
o
Q
H N1 ( s)
| 0
1
N1 i
S 2 S 1
Q
where S = s/n and n is the loop bandwidth.

Figure 45: Noise response when injected at the PFD (Low pass response)
If the noise is injected at the loop filter then noise transfer function is

H N 2 (s)

o
N2

|i 0

where S = s/n and n is the loop bandwidth. Here the response is a band pass response.

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S
1
S 2 S 1
Q

Figure 46: Noise response when injected at the loop filter (Band pass response)
If the noise is injected at the VCO then the noise transfer function is

H N3 ( s)

o
N3

|i 0

where S = s/n and n is the loop bandwidth. Here the response is high pass response.

Figure 47: Noise response when injected at the VCO (High pass response)

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S2
1
S 2 S 1
Q

Estimation of layout area:

Following table shows the total number of transistors used in individual blocks and their
estimated layout area. To estimate the area of interconnects, diffusion, n-wells and contacts, the
summation of the transistor sizes are multiplied by a factor of 6.
Name of the block or component
Phase Frequency Detector (PFD)
Charge pump
Voltage controlled oscillator (VCO)
Frequency Divider
Resistor (R = 26.5 k) in loop filter
Capacitor C1 in loop filter (5.24 pF)
Capacitor C2 in loop filter (0.524 pF)
Complete Phase locked loop (PLL)

Total number of transistors

44
15
138
143
340

Estimated Area (m2)

27.24
46.29
160.5
132.65
0.9
480
60
907.58

Summary:
So in this project, we have successfully met all the specifications. Our output frequencies were
2.912 GHz and 2.497 GHz which is within the range of 2000 PPM. Loop bandwidth is 1.29 MHz
which is close to 1 MHz, quality factor Q is 0.62 and damping factor is 0.80. All the jitters of the
output clock signal is way below pico seconds and the phase spacing errors are below 4 ps for
any combination of consecutive clock signals. The estimated layout area of the complete PLL is
907.58 m2. The eye diagram of the clock 1 is wide open suggesting very little presence of jitter.
S domain analysis also showed satisfactory response as noise response has been measured when
injected at different nodes.
References:
[1] Mozhgan Mansuri, PhD dissertation, " Low-Power Low-Jitter On-Chip Clock Generation",
University of California, Los Angeles, 2003.
[2] Hongjiang Song, class lecture 15, "Phase Locked Loop (PLL)", EEE 598, Serial Links,
Arizona State University, 2012.

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