Welcome to EE-166 Design of

CMOS Digital Circuits!

David W. Parent
dparent@email.sjsu.edu
Class 1

4-BIT ALU

Class 1

DSP Adder

Class 1

UPDOWN
COUNTER

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Course Aims
Prepare students to be productive members
of an industrial digital circuit design team.
Prepare students for graduate study or carry
out a senior design project in the VLSI field.
Provide an environment where students learn
to think critically.
Provide an environment where students learn
to enjoy the design and learning processes.
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Course Objectives
To be productive members of an industrial
digital circuit design team students
should be able to:
analyze circuits using both analytical and CAD tools
use a design flow to design a CMOS integrated circuit in a team
environment.
present results orally
interpret a design specification

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Course Objectives
To be prepared for graduate study in the VLSI area
students should be able to:
derive basic analytical MOS circuit equations
locate information not presented in class in the library

To be able to think critically students should be able to:

design test benches that can prove that a design
meet a specification
identify regions where circuit models are valid
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Course Objectives
For students to learn IC design using state
of the art design flows and CAD tools.
If you are good at this type of thing you can
make a very good salary.
It is fun too!

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IC Design LAB
In ENGR 291/289
50 linux stations running CDS IC50
Accounts will be given when enrollment
stabilizes.
We will need to spend some extra time in lab to
learn the tools.
Once you know the tools, the Homework and
project will be based on the tools.
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What does it take to succeed in

this course?
You will needs to spend 10 hours a week
outside of class.
You will need to be very organized.
Start projects/assignments early (lab fills up).

You need to know how to work on a team.

You will have to internalize the culture of a
design engineer.
I could try to make a list of this, but in the end you have
to do design to learn how to be a designer.
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What is my teaching philosophy?

I believe you learn by doing.

You will do a lot of real design in lab.

Apprentice model
Math is a tool, not an end.
EDA tools, are tools, not an end.

I believe that some of the best students at SJSU

take 166.
I believe that SJSU has some of the best students
in the world.
I believe that good students should be challenged.
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Why am I teaching EE166?

Industry needs engineers with the skills
taught in this course.
I want our graduates to be successful
engineers.
I think it is neat.
I love it.

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Academic Honesty
You are supposed to work on the homework
together.
You are not supped to copy solutions.
This class is based on trust.
Cheating will be reported. You final project
grade will be reduced, and you will be
reported.
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Block Diagram of EE166

Day 31

Digital System: ALU, Adders, IIR filters, Barrel Shifter,

SRAM, Gray-Code
Flip Flops: Setup,
hold, rise and fall time,
testbenches, power,
timing

Clock
Distribution:
Skew, fat tree,
H-Tree

Super
Buffer:
When to
use, power

Schmitt
Trigger:
Why,
How
Team Work

Design Flow

Complex Logic Gates: Noise, Delay (worst case, best case,

assign fast slow signals, chaining logic gates together) Layout
(euler path), Ring Oscillator, (nand, nor, aoi, mux), logic levels,
testbenches, power
Inverter: Noise, Delay, Layout, Ring Oscillator, power

Day 1

Circuit Modeling: Hand Calculations, Spice, Verlilog (HDL),

switch model
Device Physics: 2-D cross section, capacitances, linear,
saturation, resistances, short-channel
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True Design Flow

Receive a logic, timing, power, area and
noise specification
Choose an architecture that you think will
meet the specs
You have to do an adder that is optimized for
area, you choose ripple
You have to to an adder that is optimized for
time, you choose CLA
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True Design Flow

Choose the circuits to use based on your
architecture
AOI for area, nands for speed

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True Design Flow Note: The more

experience you
have the easier this
Evaluate your design
will be!
Use hand calculations for delay, power and area and
check: (make sure to assign late signals to best case
pins) (make sure you have the systems worst case in
mind.)
Negative Ws, increasing Cgs, area or power violations.

If there is a problem try to fix it (for example-steal time)

If there is a problem try to use the layout values of CD
If it still wont work try different circuits.
If it still wont work try different architectures
Try to see if the A and R values are correct by running some
simulations (check the Hand Calculation model)
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True Design Flow

If it still will not work go to your boss!
If it Does work:
Verify logic exhaustively in NC-verilog
Verify timing, logic, power in Spice
If it is too fast you can make Ws smaller.
You can take away 10% of your timing budget due to skew,
process tolerances, etc..
Make sure to add Cint to large designs!

Layout, DRC, extract (with caps) LV

Post extraction simulation
Evaluate design again for all specifications.
1 design!
If all is well, documentClass
the

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Lets get started

For the next few lectures we will review (learn for
first time?) MOS physics.
Why MOSFETs?
Really it should be why CMOS circuits. CMOS
circuits dissipate power only when switching (they do
use power when not switching, but is much much less
than other circuits, ECL for example)
This allows for more circuits to be placed on one die
without burning out.
MOSFETs do not suffer from thermal run away!
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Why are these topics important?

Electronic Design Automation is a highly
technical field, that is one of the driving forces
behind the local economy (Silicon Valley).
In order to interact (support) engineers it can be
helpful to understand the engineering language.
If you can speak the language your ideas will carry
more weight.

We will go over the fundamental items that will

help you understand the language of the EDA
industry.
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The way to pronounce

"EDA" is to say each letter.

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Control

Switches

A
B

Control

A switch is any device that can control current

flow between two points.
Kind of like a water faucet. Open the valve and water
flows from one side of the faucet to the other.
Control When we talk about switches we assume that we go
A
from completely off (no water flowing) to completely
on (maximum water flowing.)
Computer Chips are made of switches that are controlled with
electricity, not by a push of a button, or a twist of a handle.

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Transistors

Control
B

Transistors are electrically controlled switches

made out of semiconductors.
Conductors have a lot of free electrons so R is low and
the conduct current easily (wires).
Insulators do not have many free electrons so current
does not pass easily so R is very high (inside of
capacitors).
Semiconductors can be made to be insulators or
conductors by adding trace elements selectively.
Drain
Gate
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Source

Two Types of Transistors

NMOS, switch closes when a positive
voltage is applied to gate
Drain
Gate
Source

PMOS, switch closes when a zero volts are

applied to the gate.
Drain
Gate
Source
Some times drawn with a small bubble on the gate.
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Fabrication
http://jas.eng.buffalo.edu/education/fab/NMOS/nmos.html

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What are Boolean Logic Gates

made out of?
Switches!
Switches are made out of transistors

Lets do the truth table.

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Electronic Design Automation

EDA (Electronic Design Automation)
Using the computer to design, lay out,
verify and simulate the performance of
electronic circuits on a chip or printed
circuit board.

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How is the EDA Industry

Different?
The advancements in EDA and Processes
Technology go hand in hand.
A faster transistor process is designed with
computers and EDA software.
This allows faster computers.
This allows for better software
This allows for faster transistors to be designed
with computers and EDA software.
Repeat every 18 months since the 1960s
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Moores Law (Prediction)

The observation made in 1965 by Gordon Moore,
co-founder of Intel, that the number of transistors
per square inch on integrated circuits had doubled
every year since the integrated circuit was
invented.
Most experts, including Moore himself, expect
Moore's Law to hold for at least another two
decades.
The reason why Moore;s Law holds is that the
semiconductor industry used it as a goal!
This is a self fulfilling prophesy that drives the
local economy!
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Moores Law

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Scaling by 1/2

It would take 7 years to shrink this circuit 5 times!

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Scaling
Allows the same decision to be made using less power and
area! This drives/drove the electronic revolution. (Quite
different from Horsepower vs Engine displacement)
Full Scaling
Tries to maintain the same electric filed distribution in the
scaled device
Not always possible (The transistors still have to be able to
interface with the outside world.)
Noise!

Constant-Voltage Scaling
VDD, VT are unchanged
Power dissipation and density go up!
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Scaling
Allows the same decision to be made using less power and
area! This drives/drove the electronic revolution. (Quite
different from Horsepower vs Engine displacement)
Full Scaling
Tries to maintain the same electric filed distribution in the
scaled device
Not always possible (The transistors still have to be able to
interface with the outside world.)
Noise!

Constant-Voltage Scaling
VDD, VT are unchanged
Power dissipation and density go up!
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Scaling Exercise
Doubling the circuit density of is like
reducing all dimensions by half.
Lets try to scale a piece of paper 10 times,
by folding it in half ten times.

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Design Flow
A design flow is collection of procedures
and tools that are followed/used to make
sure a product works as intended.
Intimately related to process technology
As each process node shrinks the flow has to
handle
more transistors
more physical effects
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FPGAs
Field Programmable Gate Arrays are a cross
between Hardware and Software.
There have chips with many transistors and
blocks such as adders in which the
connections between the two can be
electrically programmed into new functions.

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Designing the parts

There are many methods used to design a a circuit.
Full custom (Fastest speed, lowest power, most exp
insert figure from kang
ASIC
Gate Array
FPGA

They all have advantages and disadvantages.

No one method is best.
The detailed process for designing with each
method is called a design flow.
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Full Custom Design Flow

Lets assume that on one of the ICs on our
cell phone needs an Arithmetic Logic Unit
(ALU) to be Full Custom Designed in
order to meet our power/speed/area
specification.

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Hand calculations for timing

CELL

We use some
Unit
simple models NOR2
NAND2
to roughly size AOI21
NOR2
the transistors, NOR2
INV
or even see if we NOR2
NOR2
can meet our
NAND2
NOR2
timing, area, and INV
NAND2
power
INV
INV
specification.

WN Load WP Load
(cm)
4.46E-04
9.93E-04
4.76E-04
4.74E-04
4.50E-04
5.42E-04
4.64E-04
4.67E-04
3.41E-04
2.62E-04
2.33E-04
8.50E-04
2.76E-04

Cint

(cm)
8.91E-04
9.93E-04
9.51E-04
9.49E-04
9.01E-04
9.69E-04
9.28E-04
9.34E-04
3.41E-04
5.24E-04
4.18E-04
8.50E-04
4.87E-04

F
2.00E-14
2.00E-14
2.00E-14
2.00E-14
2.00E-14
2.00E-14
2.00E-14
2.00E-14
2.00E-14
2.00E-14
2.00E-14
2.00E-14
2.00E-14
2.00E-14

Cg or Cin of
load
F
3.0000E-14
2.2442E-14
3.3331E-14
4.7883E-14
2.3886E-14
4.5357E-14
2.5358E-14
4.6702E-14
7.0500E-14
2.2899E-14
1.3179E-14
2.1864E-14
5.6000E-14
2.5610E-14

Cg+Cint
5.0000E-14
4.2442E-14
5.3331E-14
6.7883E-14
4.3886E-14
6.5357E-14
4.5358E-14
6.6702E-14
4.3000E-14
4.2899E-14
3.3179E-14
4.1864E-14
9.1000E-14
4.5610E-14

phl
s
1.70E-10
1.70E-10
3.90E-10
1.90E-10
1.60E-10
1.20E-10
1.60E-10
1.90E-10
2.90E-10
2.10E-10
1.39E-10
1.80E-10
2.60E-10
1.39E-10

WN
cm
4.46E-04
9.93E-04
4.76E-04
4.74E-04
4.50E-04
5.42E-04
4.64E-04
4.67E-04
3.41E-04
2.62E-04
2.33E-04
8.50E-04
2.76E-04
3.15E-04

WP
cm
8.91E-04
9.93E-04
9.51E-04
9.49E-04
9.01E-04
9.69E-04
9.28E-04
9.34E-04
3.41E-04
5.24E-04
4.18E-04
8.50E-04
4.87E-04
5.65E-04

No. of Logic Levels = 14 +4= 18

Total Tphl = 5 ns /18= 2.7ns

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Verilog Simulation
We ant to make sure that our ALU (made up of
NAND/ NOR/ADDER functionalities is logically
correct before we start
The computer software only decides if switches
are open or closed.
These functions are built into computer chips and
only take one cycle to decide
Simulations are faster than physical based
simulations so verification of the logic can
proceeded quickly.
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Verilog Verification
Checks when switches are open or closed only.

Widths do not matter.

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No timing data.

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SPICE verification
Simulation Program for Integrated Circuits
Emphasis.
Calculates all the voltages and currents in a circuit.
Physically based
Much slower than HDL, but shows timing and
power.
One can check almost all the functions of an ALU
quickly in verilog, but SPICE simulations would
takes too long.
Remeber things never work the first time. If it takes even
15 minutes for a simulation to show the problem, that
1 half an
means you can only fix one problem aboutClass
every
hour.

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Verifiy timing on the longest

Path only!
It is not enough to
have the correct logic.
The circuit must
perform the logic in
the allotted time.

We also make sure

that the power is with
in specification as well.
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Sample SPICE Waveform

The plots are not
straight up and down.
It takes time to go
from a high to a low.

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Layout
The layout of a circuit is the data that
actually sent to the fabrication house. It is
what is used to create the masks.
The are rules you must follow to ensure
your circuit will work according to you
simulation

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Design Rule Check

A DRC check is
performed to make
sure that what was
drawn can be
manufactured.
It does not imply
that the logic of the
circuit is correct.
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Layout view ALU.

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DRC Clean
This means there are no DRC errors

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Extract
Extraction algorithms are used to take the
layout view and make a schematic of what
Not what you
was drawn.
meant to draw!
It will also extract the resistances,
capacitances of the wired that connect the
transistors of the circuit together.
Remember RC is time, so in general the drawn
circuit will be slower than the schematic if you
have long wires.
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Extracted View

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LVS
Layout versus schematic
This is an equivalence check
Is what was drawn equal to the the schematic?
The logic
has
already
been
verified
for the
schematic!

=?

Class 1

If the answer is
yes, we just
have to
simulate
the longest path
in SPICE to
verify the delay!
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Post Extraction Simulation

We use SPICE again to verify the timing,
and power of the circuit.
In order to make sure the timing will come
out correct we have to predict what the
wiring delay will be before we lay out the
circuit!
Experienced people can do this well and not
overestimate too much.
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Full Custom Design

This method allows full control over each wire
and transistor width to make the fastest and
smallest implementation of a design.
Highly dependant on skilled engineers.
It is hard to do complex circuits because we
describe them with schematics and even a 100
gate schematic is hard to understand.
One uses this flow when you can not meet your
timing/area/power specification any other way.
When the design flow is followed properly your
circuit should come back
and
work
to
Class 1
specification.

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ASIC Design Flow

Application Specific Integrated Circuit.
Dealing with schematics is hard beyond 100 gates.
HDL languages allow use to write out what we
want the circuit to do in simple language
If this event occurs, do some action...

We want to automatically take a human

description of a circuit and turn it into a real
circuit.
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Circuits that
make it easier to
test the design
after fabrication
are also inserted.
(DFT, design for
test)

ASIC Design Flow

There is no wired

We write the code and make sure it behaves RC delay

information at
logically correct.
this point.
We then Synthesize the code (given a timing
specification) into NAND, NOR, XOR, and DFF
type gates.
I thought you said that HDLs had no timing
information?
The gates are chosen from a library that has been
though a full custom design flow, so the timing
information has been determined prior to the synthesis
step.
Class 1 a 1000 parts.
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The libraries can have over

ASIC Design Flow

This assumes
you have timing
closure.

Once the code is synthesized into a netlist we send

the netlist to a place and route program.
The place algorithm automatically places the
layout view of each part on the chip.
The route algorithm attempts to wire the parts
together.
Then an estimate of the RC delay is made and
checked, if timing closure is not meet the program
tries a different approach.
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Placed Cells

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After place and Route

The clock signals (clock tree) can be
automatically inserted to minimized
different arrival times of the clock edge due
to different lengths of the clock wires.
Power and ground can be routed as well
minimize voltage drops due to inductances and
resistances of wires.
The power and ground lines can be made
just wide enough to prevent electromigration
failure (Design for Manufacturability, Class
DFM)1

Wires can melt due to current flow

(electromigration).
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Signal Integrity
With each process node the wires are closer
together increasing the amount of noise between
signals.
We can extract this interaction from the layout
view and simulate it in spice, but for a large chip
the time for simulation would be too long to
provide useful feedback to the circuit designer.
A signal integrity can make sure the noise is
within specification with having to run a complete
spice deck.
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Completed Chip
This is an actual
processor. We are so high
up that we can not see the
individual transistors as
we did with the ALU.

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ASIC Flow
The main differences between full custom and
ASIC is that
ASIC automatically generates a circuit from library and
code. You can only control which parts you pick.
Design costs low and dependant on tools.
Full Custom nothing is automatically generated and you
can control which parts and how wide each transitory
is. Design costs are high, dependant on skilled
engineers.

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Other Flows
Gate Array
The transistors are and prefabricated and the
design only routes the signals from gate to gate.

Processor Based
Rather than write generic code, you write code
that is targeted to a microprocessor that can be
configured in many different ways
Design made of of many small
microprocessors.
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More design flows

Analog design is similar to the full custom
approach.
An ASIC style flow has been slow to catch on in
the analog world, but is changing (NEOCELL).
Printed Circuit Board
Chip placement
Wiring
RF noise
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Summary
A design flow is used to make sure a
product works as intended.
The flow has to be automated to reduce
human error.
The are many types of design flow each
with a cost in terms of engineering,
manufacture and support.
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Exercise
Each metal line has to be no less than 1m.
The minimum separation between metal
lines is 1m.
Each dot is separated by .5 1m.
Find the DRC errors

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Sample 1

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Sample 2

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Sample 3

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Sample 4

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Only 32 Signals!

Sample 5

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Automation makes it possible!

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