Professional Documents
Culture Documents
A8438 Datasheet
A8438 Datasheet
A8438 Datasheet
Description
The CHARGE pin enables the A8438 and starts the charging
of the output capacitor. When the designated output voltage
is reached, the A8438 stops the charging until the CHARGE
pin is toggled again. Pulling the CHARGE pin low stops
charging. The D
O
N
E
pin is an open-drain indicator of when
the designated output voltage is reached.
The A8438 can be used with two Alkaline/NiMH/NiCAD or one
single-cell Li+ battery connected to the transformer primary.
Connect the VIN pin to a 3.0 to 5.5 V supply, which can be
either the system rail or the Li+ battery, if used.
Typical Applications
Two Alkaline/NiMH/NiCAD or one Li+ battery
or 1.5 to 5.5 V
D1
VBATT
VOUT
T1
R5
100 k7
C1
0.1 F
R4
C2
4.7 F
10 k7
2.0 A
1.8 A (N.C.)
R1
SW
1.6 A
R5
100 k7
10 k7
TRIGGER
R7
IGBTDRV
GND
FB
DONE
To IGBT Gate
R6
10 k7
R3
A8438
TRIGGER
R7
IGBTDRV
GND
To IGBT Gate
10 k7
R1
SW
CHARGE
10 k7
D1
R2
VIN
ILIM
CHARGE
R6
C2
4.7 F
10 k7
1.6 A
R3
A8438
C1
0.1 F
R4
2.0 A
1.8 A (N.C.)
FB
DONE
T1
COUT
R2
VIN
ILIM
VOUT
COUT
A8438
Description (continued)
Applications include:
Selection Guide
Part Number
A8438EEJTR-T
Package
Packing*
10-pin TDFN/MLP
*Contact Allegro for additional packing options
Symbol
SW pin
Rating
Units
VSW
Notes
0.3 to 40
VIGBTDRV
FB pin
VFB
0.3 to VIN
VX
TA
IGBTDRV pin
Storage Temperature
0.3 to 7
40 to 85
TJ(max)
150
Tstg
55 to 150
Range E
Symbol
RJA
Test Conditions*
4layer PCB, based on JEDEC standard
Rating Units
45
C/W
A8438
VIN
Control Logic
CMP3
18 s
HL
Triggered Timer
1.2 V
40 V
DMOS
Q
S SET Q
CMP2
CLR Q
ILIM
Comparator
ILIM
Adjustable
Reference
ILIM Decoder
Enable
Q
Q
SET
CLR
FB
CMP1
CHARGE
1.2 V
DONE
VIN
TRIGGER
One-Shot
GND
IGBTDRV
NC
10 ILIM
IGBTDRV
FB
VIN
DONE
GND
TRIGGER
CHARGE
SW
Number
1
Name
NC
IGBTDRV
VIN
GND
Device ground
CHARGE
SW
TRIGGER
D
O
N
E
FB
10
ILIM
Function
No connection
IGBT driver gate drive output
A8438
ELECTRICAL CHARACTERISTICS Typical values at TA = 25C and VIN = 3.3 V (unless otherwise noted)
Characteristics
Supply Voltage*
Supply Current
Symbol
Test Conditions
VIN
IIN
ISWLIM
RDS(On)SW
ISWLKG
tOFF(Max)
tON(Max)
ICHARGE
VCHARGE(H)
VCHARGE(L)
D
O
N
E
Output Leakage Current*
IDONELKG
D
O
N
E
Output Low Voltage*
FB Voltage Threshold*
FB Input Current
UVLO Enable Threshold
UVLO Hysteresis
IGBT Driver
IGBTDRV On Resistance to VIN
IGBTDRV On Resistance to GND
TRIGGER Input Current
VDONE(L)
VFB
IFB
VUVLO
Charging
Charging done
Shutdown (VCHARGE = 0 V, VTRIGGER = 0 V)
VILIM < 1.0 V
ILIM pin floating
VILIM > VIN 1.3 V
VIN = 3.3 V, ID = 800 mA, TA = 25C
VSW = 35 V
VCHARGE = VIN
32 A into D
O
N
E pin
Min.
Typ.
1.6
5
1
0.01
1.6
1.8
2.0
0.27
0.2
18
18
5.5
10
1
2.0
0.8
V
mA
A
A
A
A
A
A
s
s
A
V
V
100
mV
1.187
2.55
VFB = 1.205 V
VIN rising
VUVLOHYS
RDS(On)I-V
VIN = 3.3 V, VIGBTDRV = 1.5 V
RDS(On)I-G
VIN = 3.3 V, VIGBTDRV = 1.5 V
ITRIGGER
VTRIGGER = VIN
VTRIGGER(H)
TRIGGER Input Voltage*
VTRIGGER(L)
Rgate=12 , CLOAD = 6500 pF, VIN = 3.3 V
Propagation Delay, Rising
tDr
Propagation Delay, Falling
tDf
Rgate=12 , CLOAD = 6500 pF, VIN = 3.3 V
Rgate=12 , CLOAD = 6500 pF, VIN = 3.3 V
Output Rise Time
tr
Output Fall Time
tf
Rgate=12 , CLOAD = 6500 pF, VIN = 3.3 V
*Guaranteed by design and characterization over operating temperature range, 40C to 85C.
Max. Units
1.205 1.223
120
2.65 2.75
150
5
6
30
30
70
70
0.8
V
nA
V
mV
A
V
V
ns
ns
ns
ns
A8438
VUVLO
VIN
CHARGE
SW
Target VOUT
VOUT
DONE
TRIGGER
IGBTDRV
A
Explanation of Events:
A.
Start charging by pulling CHARGE to high, provided that VIN is above the VUVLO level.
B.
N
E goes low, to signal the
completion of the charging process.
C.
Start a new charging process with a low-to-high transition at the CHARGE pin.
D.
E.
Charging does not start, because VIN is below VUVLO level when CHARGE goes high.
F.
After VIN goes above VUVLO, another low-to-high transition at the CHARGE pin is
required to start charging.
A8438
Performance Characteristics
Tests performed using application circuit shown in figure 4 (unless otherwise noted)
Symbol
C1
C4
t
Conditions
Parameter
VOUT
IBATT(Avg)
time
Parameter
VBATT
VBIAS
COUT
Units/Division
50 V
200 mA
1s
Value
2.0 V
3.3 V
100 F
IBATT
C4
C1
t
VOUT
Symbol
C1
C4
t
Conditions
Parameter
VOUT
IBATT(Avg)
time
Parameter
VBATT
VBIAS
COUT
Units/Division
50 V
200 mA
1s
Value
2.5 V
3.3 V
100 F
IBATT
C4
C1
t
VOUT
Symbol
C1
C4
t
Conditions
Parameter
VOUT
IBATT(Avg)
time
Parameter
VBATT
VBIAS
COUT
Units/Division
50 V
200 mA
1s
Value
3.0 V
3.3 V
100 F
IBATT
C4
C1
t
A8438
Performance Characteristics
Tests performed using application circuit shown in figure 4 (unless otherwise noted)
VOUT
Symbol
C1
C4
t
Conditions
Parameter
VOUT
IBATT(Avg)
time
Parameter
VBATT
VBIAS
COUT
Units/Division
50 V
200 mA
1s
Value
3.6 V
3.3 V
100 F
IBATT
C4
C1
t
VOUT
Symbol
C1
C4
t
Conditions
Parameter
VOUT
IBATT(Avg)
time
Parameter
VBATT
VBIAS
COUT
Units/Division
50 V
200 mA
1s
Value
4.5 V
3.3 V
100 F
IBATT
C4
C1
VOUT
Symbol
C1
C4
t
Conditions
Parameter
VOUT
IBATT(Avg)
time
Parameter
VBATT
VBIAS
COUT
Units/Division
50 V
200 mA
1s
Value
5.0 V
3.3 V
100 F
IBATT
C4
C1
t
A8438
Performance Characteristics
Tests performed using application circuit shown in figure 4 (unless otherwise noted)
Symbol
C1
C4
t
Conditions
Parameter
VOUT
IBATT(Avg)
time
Parameter
VBATT
VBIAS
IAVG
ILIM
COUT
Units/Division
50 V
200 mA
1s
Value
2.0 V
3.3 V
770 mA
1.8 A
140 F
IBATT
C4
C1
t
VOUT
Symbol
C1
C4
t
Conditions
Parameter
VOUT
IBATT(Avg)
time
Parameter
VBATT
VBIAS
IAVG
ILIM
COUT
Units/Division
50 V
200 mA
1s
Value
2.0 V
3.3 V
820 mA
2.0 A
140 F
IBATT
C4
C1
t
A8438
Charge Time
Efficiency
TA = 25C
6.5
90
5.5
80
Efficiency (%)
4.5
3.5
70
2.5
40
100
1.5
2.0
2.5
3.0
3.5
4.0
VBATT (V)
4.5
5.0
5.5
150
200
VOUT (V)
250
300
50%
50%
TRIGGER
t Dr
IGBTDRV
10%
tr
t Df
90%
90%
tf
10%
A8438
Rising Signal
VIGBTDRV
Symbol
C2
C3
t
Conditions
Parameter
VIGBTDRV
VTRIGGER
time
Parameter
tDr
tr
CLOAD
Rgate
Units/Division
1V
1V
50 ns
Value
22.881 ns
63.125 ns
6800 pF
12
C2
VTRIGGER
C3
tf
Falling Signal
Symbol
C2
C3
t
Conditions
Parameter
VIGBTDRV
VTRIGGER
time
Parameter
tDf
tf
CLOAD
Rgate
Units/Division
1V
1V
50 ns
Value
27.427 ns
65.529 ns
6800 pF
12
C2
VIGBTDRV
C3
VTRIGGER
t
10
A8438
Functional Description
Overview
Timer
Mode
IBATT(Avg)
VOUT
11
A8438
dISecondary
where:
dt
VOUT
LPrimary
N2
(1)
ILIM Pin
Connection
1.6
External ground
1.8
Float
2.0
Lower input current offers the advantage of a longer battery lifetime. For faster charging time, however, use the highest current
limit. ISWLIM may be adjusted during charging.
12
A8438
Transformer Design
Turns Ratio. The minimum transformer turns ratio, N,
VOUT + VD_Drop
40 VBATT
(2)
where:
VOUT (V) is the required output voltage level,
VD_Drop (V) is the forward voltage drop of the output diode(s),
VBATT (V) is the transformer battery supply, and
40 (V) is the rated voltage for the internal MOSFET switch,
representing the maximum allowable reflected voltage from the
output to the SW pin.
For example, if VBATT is 3.5 V and VD_Drop is 1.7 V (which could
be the case when two high voltage diodes were in series), and the
desired VOUT is 320 V, then the turns ratio should be at least 8.9.
In a worst case, when VBATT is highest and VD_Drop and VOUT are
at their maximum tolerance limit, N will be higher. Taking VBATT
= 5.5 V, VD_Drop = 2 V, and VOUT = 320 V 102 % = 326.4 V as
the worst case condition, N can be determined to be 9.5.
In practice, always choose a turns ratio that is higher than the
calculated value to give some safety margin. In the worst case
example, a minimum turns ratio of N = 10 is recommended.
Primary Inductance. The A8438 has a minimum switch off-time,
R5
100 k7
C1
0.1 F
R4
C2
4.7 F
10 k7
R1
150 k7
LPrimary
VOUT
COUT
100 F
330 V
SW
FB
DONE
R3
A8438
1.2 k7
CHARGE
R6
10 k7
TRIGGER
R7
IGBTDRV
GND
(3)
Symbol
C2
D1
T1
TDK LDT565630T-041,
LPrimary = 4.7 H, N = 10.2
R1, R2
R3
To IGBT Gate
10 k7
Rating
C1
150 k7
VIN
Ideally, the charging time is not affected by transformer primary inductance. In practice, however, it is recommended that a
primary inductance be chosen between 6 H and 20 H. When
LPrimary is much lower than 6 H, the converter operates at higher
frequency, which increases switching loss proportionally. This
leads to lower efficiency and longer charging time. When LPrimary
is greater than 20 H, the rating of the transformer must be dramatically increased to handle the required power density, and the
series resistances are usually higher. A design that is optimized
to achieve a small footprint solution would have an LPrimary of
7 to 14 H, with minimized leakage inductance and secondary
capacitance, and minimized primary and secondary series resistance. Please refer to the table Recommended Components for
more information.
R2
ILIM
1206 resistors, 1 %
0603 resistor, 1 %
R4, R5
Pull-up resistors
R6, R7
Pull-down resistors
Figure 4. Typical circuit for photoflash application. Configured for ISWLIM of 2.0 A.
13
A8438
R1 + R2 VOUT
=
1 .
R3
VFB
(4)
(6)
Ceramic capacitors with X5R or X7R dielectrics are recommended for the input capacitor, C2. It should be rated at least
4.7 F / 6.3 V to decouple the battery input, VBATT , at the primary
of the transformer. When using a separate bias, VBIAS , for the
A8438 VIN supply, connect at least a 0.1 F / 6.3 V bypass
capacitor to the VIN pin.
Layout Guidelines
Key to a good layout for the photoflash capacitor charger circuit
is to keep the parasitics minimized on the power switch loop
(transformer primary side) and the rectifier loop (secondary side).
Use short, thick traces for connections to the transformer primary
and SW pin.
Output voltage sensing circuit elements must be kept away from
switching nodes such as SW pin. Make sure that there is no GND
plane underneath R1 and R2, because parasitic capacitance to
ground will affect sensing accuracy. It is important that the DO
NE
signal trace be routed away from the transformer and other
switching traces, in order to minimize noise pickup. In addition,
high voltage isolation rules must be followed carefully to avoid
breakdown failure of the circuit board.
(5)
Part Number
GRM188R71C104KA01D
LMK212BJ475KG
Murata
Taiyo Yuden
EPH-331ELL101B131S
Chemi-Con
BAV23S
GSD2004S
9C12063A1503FKHFT
9T06031A1201FBHFT
ST-532517A
LDT565630T-041
DCT5EPL-UxxS002
T-16-103A
T-15-154M
Source
Philips Semiconductor,
Fairchild Semiconductor
Vishay
Yageo
Yageo
Asatech
TDK
TDK
Tokyo Coil Engineering
Tokyo Coil Engineering
14
A8438
3.15 .124
2.85 .112
A
B
10
3.15 .124
2.85 .112
A
1
SEATING
PLANE
0.30 .012
0.18 .007
0.80 .031
0.70 .028
0.10 [.004] M C A B
0.05 [.002] M C
0.20 .008
REF
0.50 .020
0.30 .012
NOM
0.50 .020
NOM
1
8X 0.20 .008
MIN
0.05 .002
0.00 .000
R0.20 .008
REF
C
1.64 .065
NOM
0.85 .033
NOM
3.10 .122
NOM
10
8X 0.20 .008
MIN
1.64 .065
NOM
0.50 .020
0.30 .012
2.38 .094
NOM
2.38 .094
NOM
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detailed specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
15