A System-On-Chip Radiation Hardened

Microcontroller ASIC With Embedded

SpaceWire Router
Richard Berger, Laura Burcin, David Hutcheson, Jennifer Koehler, Marla Lassa,
Myrna Milliser, David Moser, Dan Stanley, Randy Zeger, Ben Blalock, Mark Hale

International SpaceWire Conference 2007

Approved for Public Domain Release (VS07-0571)

2007 BAE Systems

All rights reserved

Introduction / Project Goals

The RAD6000MCTM microcontroller is being designed to consolidate all the
key elements needed for moderate levels of spaceborne computing into a
single ASIC
It is flexible enough for a wide variety of applications, from instrument
control to safe mode back-up
The RAD6000MC will be manufactured in BAE Systems RH15 150nm
radiation hardened technology, with a goal of 10x improvement in powerperformance vs. existing RAD600-based single board computers
Based on the space-proven RAD6000 CPU, it will include strong software
support for users
Green Hills Compiler
VxWorks operating system with possible addition of real time
embedded solution as well
Easy reuse/migration of existing RAD6000 application code
Reuse of existing RAD6000 infrastructure

Approved for Public Domain Release (VS07-0571)

2007 BAE Systems

All rights reserved

RAD6000MCTM Features
64KB

SRAM

PCI
PCI PCI
DMA

SpaceWire
4 port Router

Processor Units
RAD6000TM CPU
Selectable 33 or 66 MHz clock
Fixed and floating point execution units
Up to 3 instructions/cycle
8KB unified D/I cache
Embedded Microcontroller (EMC)

SRAM and Non-volatile Memory with controllers

128 KB synchronous SRAM on-chip memory
32 KB C-RAMTM non-volatile program store
External Memory controller for SRAM, DRAM,
C-RAM, etc.
Direct Memory Access (DMA) controller

I/O Bus and Communications Interfaces

33 MHz, 64-bit PCI interface (version 2.2)
16550 compatible UART
SpaceWire router with 4 serial links
Dual 1553 interface w/64 KB of on-chip SRAM

JTAG master and slave test controllers

Analog interfaces
12-bit, 8.25 Msps A-D converter
48 input programmable analog multiplexer
Three 12-bit 1 Ksps D-A converters

32KB

Mux/A/D
& D/As

- RAM

NVRAM

PCI

1553

Analog
EMC I/O
Control
EMCEMC CAT

DMADMA
6000 I/F
60006000
I/F I/F

CAT CAT
MISC

MCC

MISCMISC

MCCMCC
64KB

SRAM

64KB

SRAM

Planned Radiation Characteristics

Total Dose: 1Mrad (Si)
Single Event Effects
<1E-10 errors/bit-day
Latch-up immune

Conceptual layout shown

Approved for Public Domain Release (VS07-0571)

2007 BAE Systems

All rights reserved

RAD6000MC ASIC Block Diagram

External
Memory

COP

RAD6000MCTM
Microcontroller ASIC

RAD6000TM
CPU
I/O

33/66MHz

Memory

Embedded
32KB
Local Interface Memory
TM Microcontroller
C-RAM
Function (LIF) Control Memory
(EMC)
(MCTL)

COP
Master
OCB
Slave

OCB
OCB
Master Slave (2)

32

64

64

Reused
Minor Mod
Major Mod
New
JTAG

OCB Slave

OCB
Master

64

64

64

OCB
Slave

64KB
64KB
SRAM
SRAM
Memory
Memory

OCB OCB OCB

Master Master Slave
64

64 64

64

64

Clocks/Reset

Clock And PLL

Test (CAT)

JTAG Master
(JTAG)

Direct Memory
Access (DMA)

OCB Slave
OCB Slave

DDC IP

OCB Slave

OCB Slave

32

32

32

On-Chip Bus (OCB) Connection Medium

32

OCB OCB OCB

Master Master Slave

Analog I/O
Control (AIC)

64

32

64

64

32

OCB OCB OCB

OCB OCB OCB
Master Master Slave Master Master Slave

Router I/F (RIF) Router I/F (RIF)

D/A
A/D
Converter Converter

UART

64

Analog
Programmable
Multiplexer
Interrupt
Discretes
(PIDs)
3 External Up to 48 External
Analog Outputs Analog Inputs

SpaceWire
Router
and Links

64
OCB
Master

64
OCB
Slave

PCI-64

FIFO

MISC

64

FIFO

UART

OCB
Slave

64

FIFO

OCB Slave

32

FIFO

32

33 MHz
PCI 2.2

64

32

64

OCB Slave

64KB SRAM

D1553 Core

1553 A/B

OCB Master

JTAG Slave
(JTAG)

JTAG

SpaceWire I/F x4

Approved for Public Domain Release (VS07-0571)

2007 BAE Systems

All rights reserved

RAD6000 Microprocessor
COP Bus

Test and
Diagnostics
Unit

Memory Bus
w/ECC

Common On-Chip
Processor (COP)
Test Unit

Memory
Interface Unit

Controls
to/from
Other Units

Data

Data
Instruction Address
Instructions

Branch Processor&
Instruction Fetch
Instruction Queue &
Dispatch

Input / Output
Sequencer
Unit

Data
Instructions

Floating
Point
Execution
Unit (FPU)

Cntl

Pipeline
Control
Unit

Cntl

Unified
8KB Data /
Instruction
Cache

Data Address

I/O Bus

Data / Inst Addr

Unified
L1 cache

Up to 3
instructions
per cycle:
fixed, float,
and branch)

Fixed
Memory
Point
Virtual
Management
Execution Address
Unit (MMU)
Unit (FXU)

Fixed and Floating Point Execution Units

Approved for Public Domain Release (VS07-0571)

2007 BAE Systems

All rights reserved

Local Interface Function (LIF) Block Diagram

RAD6000
Memory Bus

RAD6000
Memory I/F
Contains Base
Address
Registers used
for Address
Translation, to
extend RAD6000
27-bit (128 MB)
address to 4 GB

RAD6000 I/O Bus

PIO
I/F

DMA
I/F

Configuration
Registers

OCB Master
I/F
OCB Master Stub

OCB Slave
(0) I/F

Wrap feature supports

use of on-chip Start-up
ROM using the C-RAM
core

Memory
Request
I/F

Memory
Controller
Request
Bus

Memory
Configuration
I/F

Memory
Controller
MC Bus

OCB Slave
(1) I/F

OCB Slave (0) Stub OCB Slave (1) Stub

Approved for Public Domain Release (VS07-0571)

Additional slave
OCB interface
supports direct
access to external
memory from other
on-chip cores

2007 BAE Systems

All rights reserved

RAD6000 Memory Address Translation

Base Address Registers

RSC_MEM_ADDR (0:23)

(8) 16 MB Pages

The complete RAD6000

(RSC) memory address
bus is 27 bits

Base Addr

Attr

0s

The complete address

space is 4 GB, but the
available address space
for the RAD6000 is 2 GB
The other 2 GB is
dedicated for the other
cores within the system

21

ADDR (31:0)

Only the 24 most

significant bits (MSBs) are
brought out, since the
RAD6000 accesses 64-bit
(8 byte) words from
memory
The 3 least significant bits
(LSBs) are shown padded
below with zeros

To OCB or Memory Controller

Approved for Public Domain Release (VS07-0571)

2007 BAE Systems

All rights reserved

On-Chip Bus Slave Memory Address Translation

OCB_ADDR (31:0)
Base Address Regs
(8) 16 MB Pages

Base Addr

For accesses above

the 128 MB RSC
addressable region:
The address is passed
directly to the Memory
Controller no
snooping

3 Bits (26:24)

Attr
Bits (31:24)

Rd Snoop Disable
Wr Snoop Disable

For accesses within the 128 MB RSC

addressable region: The Attr field for that
page determines if the access is snooped
Snooped accesses are passed directly to
the RSC I/O Bus
Non-snooped accesses pick up the Base
Addr field for the page and then are passed
to either the Memory Controller or OCB

24
ADDR (31:0)

To RSC I/O Bus, OCB, or Memory Controller

Approved for Public Domain Release (VS07-0571)

2007 BAE Systems

All rights reserved

SpaceWire Router Block Diagram and Features

Time Code
Data
Strobe

Serialize Tx Parity FIFO

Cmds
State
Machine

Strobe

Time
Code

Char detect Rx time

Deserialize Rx

FIFO

Clocks / Timers

Data
Strobe

Data

Tx time
Config /
Status

Time
Code

Char detect Rx time

Deserialize Rx

FIFO

Clocks / Timers

Data
Strobe

Strobe

Cmds

Tx time
Config /
Status

Time
Code

Char detect Rx time

Deserialize Rx

FIFO

Serialize Tx Parity FIFO

Cmds
State
Machine

Data
Strobe

Port
Arbiter

Rx

Rx

Tx

Tx

Port
Arbiter

Port
Arbiter

Rx

Rx

Tx time
Config /
Status

Time
Code

Char detect Rx time

Deserialize Rx
Clocks / Timers

Tx

Port
Arbiter

Crossbar
Routing
Switch

Rx

Clocks / Timers

Data
Strobe

Port
Arbiter

Serialize Tx Parity FIFO

State
Machine

Data

Tx

Serialize Tx Parity FIFO

Cmds
State
Machine

Strobe

Tx

FIFO

To RIF and OnChip Bus

Data

Tx time
Config /
Status

SpaceWire core implementation

Four SpaceWire ports include
External 32
integrated LVDS drivers /
Port
receivers with support for
Rx FIFO
cold sparing
Dual ports connected to OnTx FIFO
Chip Bus increase throughput
350 MHz maximum data rate
External 32
on SpaceWire link interfaces
Port
Tx FIFO

Rx FIFO

Clocks
Routing Table

Tx

Tx

Port
Arbiter

Port
Arbiter

Rx

Rx

Config.
Port
Reg File

Unique switch enhancements

Bypass Mode ignores
SpaceWire addressing and
fixes route assignment for
packet
Local header byte indicates
port # received from and
presence of Logical Address
Network blockage mitigation
by limiting packet length limits
risk of network stalling

Approved for Public Domain Release (VS07-0571)

2007 BAE Systems

All rights reserved

Programmable Multiplexer and A/D Converter

All (48)
Single
Ended
Inputs

32 Single
Ended
And 8
Differential

16 Single
Ended

and 16
Differential

All (24)
Differential
Inputs

Analog Multiplexer with programmable

input configurations, supporting singleended, differential, or mixed input signals
Select signals controlled from Analog I/O
Control digital core
12-bit Pipeline A/D converter with 1.5 bits per
stage (single stage shown)
High performance Sample and Hold circuit with
Operational Transconductance Amplifiers
Digital error correction tolerates 500 mV of
comparator offset
Supported by Bandgap Reference circuit to
generate differential reference voltage
Approved for Public Domain Release (VS07-0571)

2007 BAE Systems

All rights reserved

10

Wilkinson Architecture Three Channel D/A Converter

Ramp
Generator

4.125 MHz clock

12
Initiate
Digital
conversion Counter

Digital
Comparator
Track
and Hold
Amplifier

12
12-bit
digital
inputs

Digital
Comparator
Track
and Hold
Amplifier
Digital
Comparator
Track
and Hold
Amplifier

Wilkinson D/A
converter architecture
Shared ramp
generator and digital
counter
Repeated
comparators and
Analog
track and hold amps
out
Pipelined gray code
digital counter uses
4,096 cycles for 12 bit
resolution @ 1 Ksps
Analog
Track and Hold
out
samples ramp voltage
when comparator
pulses
Analog
out

Approved for Public Domain Release (VS07-0571)

Minimal die and power

dissipation for low
speed conversion
2007 BAE Systems
All rights reserved

11

Analog Circuit Test Chips

Analog
Multiplexer

BGR

DAC

Pipeline A/D Converter test chip

Wilkinson D/A Converter, analog

multiplexer, and Bandgap Reference
test chip

Approved for Public Domain Release (VS07-0571)

2007 BAE Systems

All rights reserved

12

Example Application Robotic Arm Control on

a System With Distributed Computing
The RAD6000 floating point
execution unit will be used
to calculate required turning
movements

The RAD6000 would

be booted from the onchip C-RAM nonvolatile memory
External
Memory

COP

RAD6000MCTM
Microcontroller ASIC

RAD6000TM
CPU
I/O

33/66MHz

Memory

COP
Master

Local Interface
Function (LIF)

OCB
Slave

OCB
OCB
Master Slave (2)

32

Embedded
32KB
TM Microcontroller
C-RAM
MCTL
(EMC)
Memory
OCB Slave
64

64

64

64

Always Operational
Operational for this application

OCB
Master
64

OCB
Slave

In Standby Mode for this application

DDC IP
64KB
64KB
SRAM
SRAM
Memory
Memory

OCB OCB OCB

Master Master Slave
64

64 64

64

Clock And PLL

Test (CAT)

JTAG Master
(JTAG)

DMA

OCB Slave
OCB Slave

Clocks/Reset

JTAG

64

OCB Slave

OCB Slave

32

32

32

On-Chip Bus (OCB) Connection Medium

64

32

OCB OCB OCB

Master Master Slave

Analog I/O
Control (AIC)

MISC

D/A
A/D
Converter Converter

UART Programmable
Interrupt
Discretes

Robotic arm control will

require control of
actuators for arm motion
using one or more joints
with turn/twist and
open/close capability that
can be supported by the
D/A converters

Analog Mux

3 External
48 External
Analog Outputs Analog Inputs

64

64

32

64

64

32

OCB OCB OCB

OCB OCB OCB
Master Master Slave Master Master Slave

Router I/F (RIF) Router I/F (RIF)

SpaceWire
Router
and Links

64
OCB
Master

64
OCB
Slave

PCI64

FIFO

UART

64

FIFO

OCB Slave

32
OCB
Slave

FIFO

32

FIFO

As a distributed
processor with
very specific
functions, a
microkernel
Operating System
is viable - external
memory is
probably not
required for this
application

Limited data is collected

and stored, so on-chip
memory should be sufficient
in this case

33 MHz
PCI 2.2

64

64

OCB Slave

64KB SRAM

D1553 Core

1553 A/B

SpaceWire I/F x4

Tactile feedback for contact and grip

pressure use pressure sensors that
will feed into the A/D converter
through the multiplexer

SpaceWire serial links are

used to support high speed
data transfers, with routing
to other subsystem
elements as required

Approved for Public Domain Release (VS07-0571)

32
OCB Master

JTAG Slave
(JTAG)

The 1553
interface is not
required so it is
shut off,
freeing up an
additional onchip 64 KB
memory block

JTAG

The PCI bus would not

be used transfers
to/from the main
processor would occur
across SpaceWire links

2007 BAE Systems

All rights reserved

13

Example Application Small Satellite Flight Computer

The RAD6000
would run a
robust realtime Operating
System,
necessitating
use of
additional
external
memory

The DMA core would perform block

memory transfers between on-chip
and external memory
External
Memory

COP

RAD6000MCTM
Microcontroller ASIC

RAD6000TM
CPU
I/O

33/66MHz

Memory

COP
Master

Local Interface
Function (LIF)

OCB
Slave

OCB
OCB
Master Slave (2)

32

64

64

Always Operational
Operational for this application

Embedded
32KB
TM
MCTL C-RAM Microcontroller
(EMC)
Memory
OCB Slave
64

64

OCB
Master
64

OCB
Slave

In Standby Mode for this application

DDC IP
64KB
64KB
SRAM
SRAM
Memory
Memory

OCB OCB OCB

Master Master Slave
64

64 64

64

Clock And PLL

Test (CAT)

JTAG Master
(JTAG)

DMA

OCB Slave
OCB Slave

Clocks/Reset

JTAG

64

OCB Slave

OCB Slave

32

32

32

On-Chip Bus (OCB) Connection Medium

MISC

32

OCB OCB OCB

Master Master Slave

Analog I/O
Control (AIC)
D/A
A/D
Converter Converter

UART

Programmable
Interrupt
Discretes

Analog Mux

3 External
48 External
Analog Outputs Analog Inputs

64

64

32

64

64

32

OCB OCB OCB

OCB OCB OCB
Master Master Slave Master Master Slave

Router I/F (RIF) Router I/F (RIF)

SpaceWire
Router
and Links

64
OCB
Master

64
OCB
Slave

PCI64

FIFO

UART

64

FIFO

OCB Slave

64

FIFO

32
OCB
Slave

FIFO

32

33 MHz
PCI 2.2

SpaceWire I/F x4

Analog interfaces will be used in both directions: actuator or

thruster control (D/A) and sensor health monitoring (multiplexed
A/D), with the EMC assisting in management of collected sensor
data to memory

64

64

OCB Slave

64KB SRAM

D1553 Core

1553 A/B

32
OCB Master

JTAG Slave
(JTAG)

JTAG

1553 bus used

for GNC units
such as star
trackers, inertial
measurement
units (IMU), and
reaction wheels

Traffic between subsystems would travel across the

SpaceWire links and through the router, requiring
operation of the PLL associated with the serial links
and the EMC used to control transfers between the
router and on-chip memory blocks

Approved for Public Domain Release (VS07-0571)

2007 BAE Systems

All rights reserved

14

Summary
The RAD6000MC is a flexible microcontroller supported by a robust set of
digital and analog interfaces
A redundant MIL-STD-1553 is provided, with embedded SRAM that can
be used elsewhere if the interface is not used
A SpaceWire router with 4 serial links and dual internal ports is provided
for high speed transfer with minimal connections
A 64-bit PCI interface offers increased parallel bus throughput
Analog/Digital conversion is supported by a programmable multiplexer
A novel approach was employed to achieve multiple channels of
Digital/Analog conversion with very low power dissipation
Enhancements have been made to address previous limitations in the
RAD6000 microprocessors addressable memory space
The ASIC is built around a reusable core architecture and heavily leverages
reuse of validated and flight proven designs
RAD6000MC configuration can be matched to user applications, optimizing
features and power dissipation

Approved for Public Domain Release (VS07-0571)

2007 BAE Systems

All rights reserved

15