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VHDL - Verilog Simulation Tutorial PDF
VHDL - Verilog Simulation Tutorial PDF
VHDL - Verilog Simulation Tutorial PDF
this script modifies your environment (sets PATH and exports variables). To see your current environment type the following at the prompt:
set
For this tutorial you will need a few extra files, please download the following files in the HDL directory:
accu.cmd
accu.v
accu_test.v
from:
http://www.ee.virginia.edu/~mrs8n/soc/files
From the tutorial directory type:
nclaunch &
The command nclaunch &starts NCSim in the background and you should get the NCLaunch startup window:
Please click on Multiple Stepand you should now get the main NCLauch window:
then click on Create cds.lib File and click Save (you should only need to do this once when you run the tool for the first time)
Finally, making sure that worklib has appeared for Work Library click OK on the Set Design Directory pop-up window. Please notice that the Library Browser
window (right side) of NCLaunch has become populated now.
There are 3 steps that we need to perform now (remember we chose multistep):
Compile
Elaborate
Simulate
In order to compile you first need to select the various files in the File Browser (left side) by clicking on the mouse left button (simultaneously press on shift for
multiple selections), then click on the corresponding buttons in the Menu Bar (in this case the VLOG button) or explicitly go to Tools -> Verilog Compiler....
Now is actually a good time to look at these files as well, you can do that for example by clicking on the file, then going to File -> Edit, you should see the actual
file in a text editor:
Close the text editor without modifying the file. Now compile both accu.v and accu_test.v in that order.
Caution! The order of compilation is important in case there are dependencies among the files. In the case the testbench is the "top" file and
needs to be compiled last!
Make sure there are no errors in the Console Window (always keep an eye on that window for errors and warnings).
In order to elaborate first click on the + in front of the worklib on the Library Browser window in order to see it's contents:
Now select the top file under worklib (stimulus) then click on the Elaborate button in the Menu (immediately to the right of the VLOG button), or go to Tools > Elaborator....
Finally we can simulate! Click on the + sign in front of the Snapshots library to expand its contents, then select worklib.stimulus:module and click on Simulate
(next to the right of elaborate) or go to Tools -> Simulator.... This should launch the Simvision Design Browser and Console windows:
Click on stimulus on the left window, then on the Waveform button (the one that looks like a set of white digital waveforms on a black background, sixth from the
right), this should open a new Waveform window. Now press on the Run button on the Design Browser window (first on the left, looks like a Play button on a
CD player). This should now display the signal waveforms that validate correct functionality for the accumulator (increment by one for every clock cycle):