Professional Documents
Culture Documents
Ies Digital Electronics Notes
Ies Digital Electronics Notes
For
GATE/IES/PSU-2014
KNOW UR weaker areas in Prep and for
Free Practice thousands of Qns., Online tests,
Downloads, Discussion forums
www.GateIesPsu.com
INDEX
Topics
---
1. Basics
--2. Combinational logic
---
Page No.
-----
1 to 20
21 to 47
From:
Branch :--EC/EE/IN/CS/IT
Subject:Digital Electronics
Topic:Basics
. [QDigA047] .. (
. [QDigA048] .. (
[B] 6, 2
[D]7, 2
an
ga
lo
re
[A]
[C]
3)How many memory Ics of 4k x 2 capacity are required to construct a memory of 22k x 8 capacity ?
[A] 22
[C]24
. [QDigA054] .. (
[B] 20
[D]20
[A] P, Q, R
[C]R, S, T
S,
B
IE
[A] 256
[C]8
. [QDigA068] .. (
. [QDigA079] .. (
[B] 64
[D]4
. [QDigA064] .. (
[B] Q, R, S
[D]P, R, T
is independent of variables
[B] x
[D]z and x
[A]
[C]
[B]
[D]
Page.No.1
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
8)The Karnaugh map of 4 variable Boolean functions A, B C, D is shown in figure X indicates dont care
combinations. The minimal SOP expression for the function is
[A]
[C]
. [QDigA088] .. (
. [QDigA099] .. GATE-ECE/TCE-2001(
[B]
[D]
an
ga
lo
re
[A] 101110
[C]111110
is equivalent to
. [QDigA100] .. GATE-ECE/TCE-1999(
. [QDigA102] .. GATE-ECE/TCE-1999(
. [QDigA116] .. GATE-ECE/TCE-2002(
. [QDigA122] .. GATE-ECE/TCE-2003(
[B]
[D]Y = A + B
[B]
[D]
[B] 0
[D]-8
[A] 16
[C]1024
S,
B
[B] 256
[D]65536
14)Two 2s complement numbers having sign bits x and y are added and the sign bit of the result is z.
Which Boolean function indicates the occurrence of the overflow?
IE
[A] xyz
[C]
. [QDigA481] .. IES-ECE/TCE-2008(
[B]
[D]xy+yz+zx
. [QDigA487] .. IES-EEE-2012(
[A]
[C]
[B]
[D]
17)The range of signed decimal numbers that can be represented by 6-bite 1s complement number is
. [QDigA135] .. GATE-ECE/TCE-2004(
[A] 31 to + 31
[C] 64 to + 63
[B] 63 to + 63
[D] 32 to + 31
Page.No.2
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
18)A digital system is required to amplify a binary-encoded audio signal. The user should be able to control
the gain of the amplifier from a minimum to a maximum in 100 increments. The minimum number of bits
required to encode, in straight binary, is
[A] 8
[C]5
. [QDigA136] .. GATE-ECE/TCE-2004(
. [QDigA202] .. IES-ECE/TCE-2000(
. [QDigA203] .. IES-ECE/TCE-2000(
. [QDigA208] .. IES-ECE/TCE-2000(
[B] 6
[D]7
[B] 194
[D]269
[A] (3320)16
[C](FF50)16
[D](3520)16
an
ga
lo
re
[D]design gates
. [QDigA139] .. GATE-ECE/TCE-2004(
is equivalent to
[B]
[D]
S,
B
[A]
[C]
. [QDigA222] .. IES-ECE/TCE-2000(
[B] D 403
[D]C 403
24)11001, 1001 and 111001 correspond to the 2s complement representation of which one of the following
sets of number?
[A] 25, 9 and 57 respectively
[C]-7, -7 and -7 respectively
. [QDigA140] .. GATE-ECE/TCE-2004(
IE
. [QDigA142] .. GATE-ECE/TCE-2004(
. [QDigA143] .. GATE-ECE/TCE-2005(
[B] 4 Unit
[D]2 Unit
Page.No.3
For Free Online tests/Materials Register at www.gateiespsu.com & Site: www.onlineies.com
For Regular udpates: www.facebook.com/onlineies Groups: http://groups.google.com/group/onlineies
Contact: (+91) 99003 99699 E-mail: onlineies.com@gmail.com
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
an
ga
lo
re
. [QDigA146] .. GATE-ECE/TCE-2005(
[A]
[C]
[B]
[D]
IE
S,
B
28)The number of product terms in the minimized sum of product expression obtained through the following
K-map is (where, d denotes dont care states)
[A] 2
[C]4
. [QDigA151] .. GATE-ECE/TCE-2005(
[B] 3
[D]5
29)A new Binary coded Pentary (BCP) number system is proposed in which every digit of a base- 5 number is
represented by its corresponding 3-bit binary code. For example, the base- 5 number 24 will be
represented by its BCP code 010100. In this numbering system, the BCP code 100010011001
corresponds to the following number in base-5 system
. [QDigA152] .. GATE-ECE/TCE-2006(
[A] 423
[C]2201
[B] 1324
[D]4231
30)X = 01110 and Y = 11001 are two 5-bit binary numbers represented in twos complement format. The sum
of X and Y represented in twos complement format using 6 bits is
. [QDigA158] .. GATE-ECE/TCE-2007(
[A] 100111
[C]000111
[B] 001000
[D]101001
Page.No.4
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
31)The Boolean function Y = AB + CD is to be realized using only 2-input NAND gates. The minimum number
of gates required is
. [QDigA159] .. GATE-ECE/TCE-2007(
[A] 2
[C]4
[B] 3
[D]5
Can be minimized to
. [QDigA160] .. GATE-ECE/TCE-2007(
[A]
[C]
[B]
[D]
33)The two numbers represented in signed 2s complement form are P = 11101101 and Q = 11100110. If Q is
subtracted from P, the value obtained in signed 2s complement form is
. [QDigA168] .. GATE-ECE/TCE-2008(
[A] 100000111
[C]11111001
[A] Y=Z
[C]Z=1
[D]111111001
, then
an
ga
lo
re
[B] 00000111
. [QDigA176] .. GATE-ECE/TCE-2009(
. [QDigA187] .. IES-ECE/TCE-1999(
. [QDigA190] .. IES-ECE/TCE-1999(
[B]
[D]Z=0
corresponds to
[B]
[D]
[A]
[C]
[A] 8
[C]10
S,
B
. [QDigA233] .. IES-ECE/TCE-2001(
[B] 9
[D]12
38)If the output of a logic gate is 1 when all its inputs are at logic 0 the gate is either
IE
39)For the Karnaugh map shown in the given figure, the minimum Boolean function is
[A] xy + z + yz
[C]xy + z + yz
. [QDigA234] .. IES-ECE/TCE-2001(
. [QDigA236] .. IES-ECE/TCE-2001(
[B] xz + z +zy
[D]xz + z + yz
[B]
[D]
Page.No.5
For Free Online tests/Materials Register at www.gateiespsu.com & Site: www.onlineies.com
For Regular udpates: www.facebook.com/onlineies Groups: http://groups.google.com/group/onlineies
Contact: (+91) 99003 99699 E-mail: onlineies.com@gmail.com
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
[A]
[C]
[B]
[D]
42)In signed magnitude representation, the binary equivalent of 22.5625 is (the bit before comma represents
the sign)
[A] 0, 10110. 1011
. [QDigA244] .. IES-ECE/TCE-2001(
. [QDigA245] .. IES-ECE/TCE-2002(
[C]1, 10101.1001
[D]1, 10110.1001
[C](2BC)16 (1DE)16
an
ga
lo
re
[D](200)16 (11D)16
. [QDigA248] .. IES-ECE/TCE-2002(
. [QDigA250] .. IES-ECE/TCE-2002(
[B] 256
[B] Giving input to one input line and logic zero to the
other line
[D]inversion cannot be achieved using EX-OR gate.
IE
S,
B
46)The minimized expression for the given K map (x: dont care) is
[A]
[C]C+AB
. [QDigA253] .. IES-ECE/TCE-2002(
. [QDigA254] .. IES-ECE/TCE-2002(
[B] B+AC
[D]ABC
[A]
[C]CD
[B] BC
[D]BC
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
. [QDigA255] .. IES-ECE/TCE-2002(
49)A number is expressed in binary twos complement as 10011. Its decimal equivalent value is
[A] 19
[C]-19
. [QDigA258] .. IES-ECE/TCE-2002(
. [QDigA259] .. IES-ECE/TCE-2003(
[B] 13
[D]-13
50)The output of a logic gate is 1 when all its input 0 then the gate is either
[A] A NAND or an EX-OR gate
[B] A NOR or an EX-NOR gate
[C]An OR or an EX-NOR gate
51)Match List-I with List-II and select the correct answer using the codes given below the lists:
List-I List-II
1.
B.
2. A = B
C.
3. A =1 or B = 1
D.
4. A = 1 or B = 0
an
ga
lo
re
A.
. [QDigA260] .. IES-ECE/TCE-2003(
. [QDigA261] .. IES-ECE/TCE-2003(
Simplifies to
[B]
[D]
[A] zero
[C]4
S,
B
53)The minimum number of NAND gates required to implement the Boolean function
to
is equal
. [QDigA262] .. IES-ECE/TCE-2003(
. [QDigA276] .. GATE-ECE/TCE-2010(
[B] 1
[D]7
IE
55)How many 1s are present in the binary representation of (4 x 4096) + (9 x 256)+ (7 x16) + 5?
. [QDigA278] .. IES-ECE/TCE-2004(
[A] 8
[C]10
[B] 9
[D]11
Page.No.7
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
56)Assume that only x and y logic inputs are available and the complements
is the minimum number of 2-input NAND gates required to implement
[A] 2
[C]4
[B] 3
[D]5
57)A, B and C are three Boolean variables which one of the following Boolean expressions cannot be
minimized any further?
. [QDigA280] .. IES-ECE/TCE-2004(
[A]
[C]
[B]
[D]
?
. [QDigA282] .. IES-ECE/TCE-2004(
[A] 0
[C]4
[B] 1
[D]7
59)The output of a two level AND-OR gate network is F. what is the output when all the gates are replaced by
NOR gates?
an
ga
lo
re
. [QDigA286] .. IES-ECE/TCE-2004(
[A] F
[C]
[B]
[D]
. [QDigA306] .. IES-ECE/TCE-2005(
[A] 10.1
[C]10.2
[B] 10.01
[D]1.02
61)The number of 1 in 8-bits representation of -127 in 2s complement from is m and that in 1s complement
form is n. what is the value of m:n?
[A] 2: 1
[C]3 : 1
. [QDigA307] .. IES-ECE/TCE-2005(
. [QDigA308] .. IES-ECE/TCE-2005(
. [QDigA318] .. GATE-EEE-2003(
[B] 1 : 2
[D]1 : 3
[A] 5
[C]12
S,
B
62)Given
(135)base x+ (144)base x = (323)base x
What is the value of base x?
IE
[A]
[C]
[B] 3
[D]6
can be simplified to
[B]
[D]
can be written as
. [QDigA321] .. GATE-EEE-2004(
. [QDigA330] .. GATE-EEE-2007(
. [QDigA333] .. IES-EEE-2001(
[B]
[D]
[B] 253.632
[D]526.632
[B]
[D]
Page.No.8
For Free Online tests/Materials Register at www.gateiespsu.com & Site: www.onlineies.com
For Regular udpates: www.facebook.com/onlineies Groups: http://groups.google.com/group/onlineies
Contact: (+91) 99003 99699 E-mail: onlineies.com@gmail.com
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
[A] 17670
[C]17067
. [QDigA342] .. IES-EEE-2002(
. [QDigA343] .. IES-EEE-2002(
. [QDigA345] .. IES-EEE-2002(
. [QDigA346] .. IES-EEE-2003(
[B] 17607
[D]10767
[B] NOT
[D]EXCLUSIVE OR
[B] AB
[D]
is
an
ga
lo
re
. [QDigA347] .. IES-EEE-2003(
. [QDigA356] .. IES-EEE-2003(
[B]
[D]
[B] 2 and 3
[D]2 and 4
S,
B
73)Match List-I (Circuit symbols) with List-II (Nomenclature) and select the correct answer using the codes
given below :
List-I List-II
B.
C.
1. NAND
IE
A.
D.
2. NOR
3. Buffer
4. Schmitt trigger
. [QDigA359] .. IES-EEE-2004(
74)If x and y are Boolean variables, which one of the following is the equivalent of
?
. [QDigA360] .. IES-EEE-2004(
[A]
[C]0
[B] x + y
[D]1
in the expression
Page.No.9
For Free Online tests/Materials Register at www.gateiespsu.com & Site: www.onlineies.com
For Regular udpates: www.facebook.com/onlineies Groups: http://groups.google.com/group/onlineies
Contact: (+91) 99003 99699 E-mail: onlineies.com@gmail.com
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
. [QDigA363] .. IES-EEE-2004(
[A] 8, 16
[C]6, 16
[B] 16, 8
[D]12, 8
[A] w = 0 , y = 0 , z = 1
[C]w = 1 , y = 1 , z = 1
[B] w = 0 , y = 1 , z = 1
[D]w = 1 , y = 1 , z = 0
[A] 1, 2 and 4
[C]2, 3 and 4
an
ga
lo
re
. [QDigA370] .. IES-EEE-2005(
. [QDigA371] .. IES-EEE-2005(
. [QDigA372] .. IES-EEE-2005(
. [QDigA377] .. IES-EEE-2007(
[B] 1 and 3
[D]1, 2 and 3
[B]
[D]
[A]
[C]
[B]
[D]
S,
B
81)The function
is logically equivalent to
[A] F = A
[C]F = ABC
[B] F = AB
[D]F = B
IE
82)If the input to the digital circuit of the below figure consisting of a cascade of 20 XOR gates is X , then
what is the output Y ?
. [QDigA380] .. IES-EEE-2007(
[A] 0
[C]X'
[B] 1
[D]X
Page.No.10
For Free Online tests/Materials Register at www.gateiespsu.com & Site: www.onlineies.com
For Regular udpates: www.facebook.com/onlineies Groups: http://groups.google.com/group/onlineies
Contact: (+91) 99003 99699 E-mail: onlineies.com@gmail.com
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
83)What is the minimized logic expression corresponding to the given Karnaugh Map?
. [QDigA387] .. IES-ECE/TCE-2005(
[A] xz
[C]
[B]
[D]
[A] (x+y)(y+z)
[C]
[B]
[D]
[A]
[C]
an
ga
lo
re
85)
Which one of the following is the dual form of the Boolean identity given above?
. [QDigA389] .. IES-ECE/TCE-2005(
. [QDigA390] .. IES-ECE/TCE-2005(
. [QDigA407] .. IES-EEE-2008(
. [QDigA408] .. IES-ECE/TCE-2006(
. [QDigA409] .. IES-ECE/TCE-2006(
[B]
[D]
[D]Alphanumeric code
[A]
[C]XY
S,
B
[B]
[D]
[B] 110101
[D]111110
IE
[A] 101011
[C]011111
90)The Boolean expression Y (A, B, C) = A + BC is to be realized using 2-input gates of only one type. What
is the minimum number of gates required for the realization?
. [QDigA411] .. IES-ECE/TCE-2006(
[A] 1
[C]3
[B] 2
[D]4 or more
Page.No.11
For Free Online tests/Materials Register at www.gateiespsu.com & Site: www.onlineies.com
For Regular udpates: www.facebook.com/onlineies Groups: http://groups.google.com/group/onlineies
Contact: (+91) 99003 99699 E-mail: onlineies.com@gmail.com
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
91)Match List-I (Expression-I ) with List-II (Expression-II) and select the correct answer using the code given
below the lists :
List-I List-II
A.
1.
B.
2. A(B + C)
C.
3.
D.
4. AB + BC + AC
. [QDigA412] .. IES-EEE-2008(
92)The AND function can be realized by using only n number of NOR gates . What is n equal to ?
. [QDigA413] .. IES-EEE-2008(
[A] 2
[C]4
[B] 3
[D]5
an
ga
lo
re
. [QDigA415] .. IES-EEE-2008(
[A] 1 and 2
[C]1 and 3
[B] 2 and 3
[D]None of these
94)The Boolean expression X(P,Q,R) = (0,5) is to be realized using only two 2-input gates. Which are these
gates?
[A] AND and OR
[C]AND and XOR
. [QDigA417] .. IES-ECE/TCE-2006(
. [QDigA427] .. IES-ECE/TCE-2006(
. [QDigA429] .. IES-ECE/TCE-2006(
IE
S,
B
95)What is the Boolean expression for the truth table shown below?
[A]
[C]
[B]
[D]
[B] AD+A
[D]
) equal to?
Page.No.12
For Free Online tests/Materials Register at www.gateiespsu.com & Site: www.onlineies.com
For Regular udpates: www.facebook.com/onlineies Groups: http://groups.google.com/group/onlineies
Contact: (+91) 99003 99699 E-mail: onlineies.com@gmail.com
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
[A] B
[C]A+B
. [QDigA430] .. IES-ECE/TCE-2006(
. [QDigA431] .. IES-ECE/TCE-2007(
[B] A
[D]AB
equivalent to ?
[A]
[C]B
[B]
[D]
99)Assume that only x and y logic inputs are available and the complements and are not available. What
is the minimum number of 2-input NAND gates required to implement
?
. [QDigA438] .. IES-ECE/TCE-2007(
[A] 2
[C]4
[B] 3
[D]5
100)Which one of the following is the correct sequence of the numbers represented in the series given below?
(2)3, (10)4, (11)5, (14)6, (22)7 .........
. [QDigA439] .. IES-ECE/TCE-2007(
[B] 2,4,6,8,10,......
[D]2,4,6,10, 16.....
an
ga
lo
re
[A] 2,3,4,5,6.......
[C]2,4,6,10,12.....
. [QDigA440] .. IES-ECE/TCE-2007(
. [QDigA441] .. IES-ECE/TCE-2007(
[B] (16)16
[D](01000000)2
[B] 0
[D]x3
103)By inspecting the Karnaugh map plot of the switching function F(x1x2 x3) = (1, 3, 6, 7) one can say that
the redundant prime implicant is
S,
B
. [QDigA443] .. IES-ECE/TCE-2007(
[A]
[C]x1x2
[B] x2x3
[D]x3
IE
104)For a function F , the Karnaugh map is shown in the figure below . Then minimal representation of F is
. [QDigA444] .. IES-EEE-2010(
[A]
[C]A + B + C
[B]
[D]
105)Match list-I (Boolean logic Function) with List-II (Inverse of Function) and select the correct answer using
the code given below the lists:
List-I List-II
A. ab+bc+ca+abc 1.
B.
2.
C. a + bc 3.
D. .
4.
. [QDigA446] .. IES-ECE/TCE-2007(
[A] A-3 B- 2 C- 1 D- 4
[C]A- 3 B- 2 C- 4 D- 1
[B] A- 2 B- 3 C- 1 D- 4
[D]A- 2 B- 3 C- 4 D- 1
Page.No.13
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
106)Match List-I with List-II and select the correct answer using the codes given below the lists :
List-I List-II
A.
1. AB
B.
2.
C.
3. A + B
4.
an
ga
lo
re
D.
. [QDigA449] .. IES-EEE-2010(
. [QDigA454] .. IES-ECE/TCE-2007(
. [QDigA457] .. IES-EEE-2011(
[A]
[C]
S,
B
108)The Boolean expression for the shaded area in the Venn diagram shown is
[B]
[D]
IE
109)The Boolean functions can be expressed in canonical SOP (sum of products) and POS (product of sums)
form. For the functions.
which are such two forms
. [QDigA463] .. IES-ECE/TCE-2008(
110)The Boolean function A+BC is a reduced form of which one of the following
[A] AB+BC
[C](A+B) (A+C)
. [QDigA464] .. IES-ECE/TCE-2008(
. [QDigA465] .. IES-ECE/TCE-2008(
[B]
[D]None of the above
[B]
[D]
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
[A] 11000
[C]11110
113)AND operation of
. [QDigA467] .. IES-ECE/TCE-2008(
. [QDigA480] .. IES-EEE-2011(
[B] 10100
[D]11111
and
results in
[A] 50 H
[C]42 H
[B] 48 H
[D]08 H
115)If
[B] 6
[D]9
an
ga
lo
re
[A] 5
[C]7
116)In VHDL all the statements written inside a process statement are .......
[A] Concurrent
[C]Both of the above
. [QISRA088] .. ISRO-ECE/TCE-2011(
. [QISRA102] .. ISRO-ECE/TCE-2011(
. [QISRA130] .. ISRO-ECE/TCE-2011(
[B] Sequential
[D]None of the above
[B] [D]&
S,
B
119)The greatest negative number which can be stored in a 8-bit register using 2's complement arithmetic is
IE
[A] - 256
[C]- 127
. [QISRA131] .. ISRO-ECE/TCE-2011(
. [QISRA144] .. ISRO-ECE/TCE-2011(
[B] - 255
[D]- 128
121)When using a sequential code to design a combinational logic in VHDL , if complete truth table is not
defined , the synthesis tool will implement a ................ which is not required
[A] Clock buffer
[C]Flip flop
. [QISRA156] .. ISRO-ECE/TCE-2011(
. [QISRA167] .. ISRO-ECE/TCE-2010(
[B] Buffer
[D]Latch
122)The purpose of Design For Test (DFT) process in ASIC design flow is
[A] To capture functional errors
[C]To capture timing violations
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
123)Which one of the following is the lowest level of abstraction for representation of a digital system ?
[A] VHDL / Verilog
[C]Gate level netlist
. [QISRA180] .. ISRO-ECE/TCE-2010(
. [QISRA226] .. ISRO-ECE/TCE-2010(
. [QISRA259] .. ISRO-ECE/TCE-2009(
. [QISRA260] .. ISRO-ECE/TCE-2009(
[B] GDS-II
[D]System C
124)How many adders are required to realize a 256 point radix-2 FET using
[A] 256
[C]4096
[B] 1024
[D]2048
[B] ASIC
[D]PLD
126)Which is the correct order of different process steps for a typical FPGA design ?
[B] Functional simulation , Timing Verification ,
Synthesis , Place &Route
[D]Synthesis , Functional simulation , Timing
Verification , Place &Route
an
ga
lo
re
127)The greatest negative number which can be stored in a computer that has 8-bit word length and uses 2's
complement arithmetic is
[A] - 256
[C]- 128
. [QISRA274] .. ISRO-ECE/TCE-2009(
. [QISRA331] .. ISRO-ECE/TCE-2008(
[B] - 255
[D]- 127
S,
B
storage element is
129)
. [QISRA336] .. ISRO-ECE/TCE-2008(
. [QISRA341] .. ISRO-ECE/TCE-2008(
. [QISRA342] .. ISRO-ECE/TCE-2008(
. [QISRA423] .. ISRO-ECE/TCE-2007(
IE
[A] XNOR
[C]Sequential
[B] XOR
[D]OR
[B] EEPROM
[D]None of these
[B] 1101111.111
[D]110110.011
133)Assuming that only the X and Y logic inputs are available and their complements
available , what is the minimum number of two-input NAND gates requires to implement
are not
?
. [QISRA498] .. ISRO-ECE/TCE-2006(
[A] 2
[C]4
[B] 3
[D]5
Page.No.16
For Free Online tests/Materials Register at www.gateiespsu.com & Site: www.onlineies.com
For Regular udpates: www.facebook.com/onlineies Groups: http://groups.google.com/group/onlineies
Contact: (+91) 99003 99699 E-mail: onlineies.com@gmail.com
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
. [QISRA499] .. ISRO-ECE/TCE-2006(
[A]
[B]
[D]
[C]
. [QISRA506] .. ISRO-ECE/TCE-2006(
. [QISRA509] .. ISRO-ECE/TCE-2006(
[B] 9
[D]11
[A] 1100
[C]0110
an
ga
lo
re
137)For the switch circuit , taking open as 0 and closed as 1 , the expression for the circuit is Y .
[A] A + (B + C)D
[C]A (BC + D)
. [QISRA511] .. ISRO-ECE/TCE-2006(
. [QISRA512] .. ISRO-ECE/TCE-2006(
[B] A + BC + D
[D]None of these
IE
S,
B
138)The Boolean expression for the shaded area in the Venn diagram is
[A]
[C]X + Y + Z
[B]
[D]
139)Given the decimal number - 19 , an eight bit two's complement representation is given by
. [QISRA514] .. ISRO-ECE/TCE-2006(
[A] 11101110
[C]11101100
[B] 11101101
[D]None of these
140)The function shown in the figure when simplified will yield a result with
Page.No.17
For Free Online tests/Materials Register at www.gateiespsu.com & Site: www.onlineies.com
For Regular udpates: www.facebook.com/onlineies Groups: http://groups.google.com/group/onlineies
Contact: (+91) 99003 99699 E-mail: onlineies.com@gmail.com
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
[A] 2 terms
[C]7 terms
. [QISRA515] .. ISRO-ECE/TCE-2006(
. [QISRA531] .. ISRO-ECE/TCE-2006(
[B] 4 terms
[D]16 terms
142)The number of product terms in the minimized sum-of-product expression obtained through the following
k-map is (where " d " denotes don't care states )
. [QDigA002] .. (
. [QDigA009] .. (
[B] 3
[D]5
an
ga
lo
re
[A] 2
[C]4
[B]
[D]
144)In a given switching function the number of variables are 4 , the number of prime implications are 'm' and
the number of essential prime implicants are (m-1) then the number of minimal expressions are
[A] 4
[C]1
. [QDigA021] .. (
[B] 2
[D]The data in the problem is not enough to decide
[A] 23
[C]31
[A]
[C]
. [QDigA022] .. (
. [QDigA023] .. (
. [QDigA025] .. (
[B] 32
[D]13
IE
146)If
S,
B
145)In the following series the same integer is expressed in different number system 10000, 121, 100 , ? , 24 ,
22, 20 ,....... The missing member of the series is
[B]
[D]
148)If
[A]
[C]
149)Let
[A]
[C]xy + z
and
then
is
. [QDigA031] .. (
. [QDigA032] .. (
[B]
[D]
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
150)A digital circuit is monitoring three pumps whenever majority pumps fails the circuit panel LED must glow ,
otherwise LED must OFF . The digital circuit output must be zero whenever the majority of the pumps fails
. The possible minimal SOP expression of the circuit is [ Consider the Boolean variables assigned to
pumps are x , y, z ]
. [QDigA035] .. (
. [QDigA036] .. (
[B]
[D]
[A]
[C]xy + yz + zx
an
ga
lo
re
IE
S,
B
Page.No.19
For Free Online tests/Materials Register at www.gateiespsu.com & Site: www.onlineies.com
For Regular udpates: www.facebook.com/onlineies Groups: http://groups.google.com/group/onlineies
Contact: (+91) 99003 99699 E-mail: onlineies.com@gmail.com
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
Key Paper
D
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.
36.
37.
38.
39.
40.
41.
42.
43.
44.
45.
46.
47.
48.
49.
50.
51.
52.
53.
54.
55.
56.
57.
58.
59.
60.
61.
62.
63.
64.
65.
66.
67.
68.
69.
70.
71.
72.
73.
74.
75.
76.
77.
78.
79.
80.
81.
82.
83.
84.
85.
86.
87.
88.
89.
90.
91.
92.
93.
94.
95.
96.
97.
98.
99.
100.
101.
102.
103.
104.
105.
106.
107.
108.
109.
110.
111.
112.
113.
114.
115.
116.
117.
118.
119.
120.
121.
122.
123.
124.
125.
126.
127.
128.
129.
130.
131.
132.
133.
134.
135.
136.
137.
138.
139.
140.
141.
142.
143.
144.
145.
146.
147.
148.
149.
150.
151.
IE
S,
B
ng
al
or
e
1.
Page.No.20
For Free Online tests/Materials Register at www.gateiespsu.com & Site: www.onlineies.com
For Regular udpates: www.facebook.com/onlineies Groups: http://groups.google.com/group/onlineies
Contact: (+91) 99003 99699 E-mail: onlineies.com@gmail.com
Branch :--EC/EE/IN/CS/IT
1)The point Z in the following figure is stuck at -1 . The output f will be ..........
. [QDigA003] .. (
. [QDigA008] .. (
[B]
[D]A
an
ga
lo
re
[A]
[C]
IE
S,
B
3)A combinational circuit using a 8-to-1 mux is shown in the following figure . The minimized expression for
the output (Z) is
. [QDigA010] .. (
[A]
[C]
[B] C (A + B)
[D]
Page.No.21
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
. [QDigA013] .. (
. [QDigA015] .. (
. [QDigA016] .. (
an
ga
lo
re
. [QDigA019] .. (
8)The minimum number of 2 input NAND gates required to implement the following Boolean function
[A] 3
[C]5
. [QDigA026] .. (
. [QDigA027] .. (
. [QDigA029] .. (
[B] 4
[D]6
IE
[A]
[C]
S,
B
[B] x + y
[D]xy + x
10)Match List-I with List-II and select the correct answer by using the code given below the lists :
List-I List-II
P. Multiplexer 1. Sequential memory
Q.De-Multiplexer 2. Converts decimal number to binary
R. Shift-Register 3. Data selector
S. Encoder 4. Routes out many data output with single input
[A] P-3, Q-4, R-1, S-2
[C]P-4, Q-3, R-1, S-2
Page.No.22
For Free Online tests/Materials Register at www.gateiespsu.com & Site: www.onlineies.com
For Regular udpates: www.facebook.com/onlineies Groups: http://groups.google.com/group/onlineies
Contact: (+91) 99003 99699 E-mail: onlineies.com@gmail.com
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
11)Consider the circuit shown in figure . The output of 2 : 1 MUX is given by the function ac + bc . Which of
the following is true ?
[A]
[C]
. [QDigA030] .. (
. [QDigA034] .. (
. [QDigA039] .. (
[B]
[D]
an
ga
lo
re
[A]
[C]
[B]
[D]
[B]
[C]
S,
B
[A]
[D]
IE
14)It is possible to realize 32 x 1 MUX by using (Consider A, B, C, D and E are select variables of 32 x 1 MUX
and A is MSB variable and 'E' is LSB variable
[A] 4 x 1 MUX 11 number while connecting A and B
variable at level-1 MUX and C and D at level-2
and E at level-3
[C]4 x 1 MUX 11 number while connecting D and E
variables at level-1 and B and C at level-2 and A
at level-3
. [QDigA042] .. (
15)A 4-bit binary adder is adding two BCD numbers . The output from the adder is with variables DCBA (D is
MSB) and carry . If it is required to develop a checking circuit its output must be zero , when the binary
adder result is valid BCD otherwise output is 1 . The possible Boolean expression f of the checking circuit
is
. [QDigA043] .. (
[A]
[C]f = DC + DB
[B]
[D]
Page.No.23
For Free Online tests/Materials Register at www.gateiespsu.com & Site: www.onlineies.com
For Regular udpates: www.facebook.com/onlineies Groups: http://groups.google.com/group/onlineies
Contact: (+91) 99003 99699 E-mail: onlineies.com@gmail.com
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
16)Consider the logic circuit shown below has four bit binary number
as output the circuit implements
. [QDigA044] .. (
an
ga
lo
re
17)The block box in the following figure consists of a minimum complexity circuit that uses only AND , OR and
NOT gates
The function f(x, y, z) = 1 whenever x, y are different and '0' otherwise in addition the 3 inputs x, y and z
are never all the same value . Which of the following equation lead to the correct design for the minimum
complexity circuit ?
[A]
[C]
. [QDigA045] .. (
. [QDigA046] .. (
[B]
[D]
IE
S,
B
and
is open
are closed
are open
Page.No.24
For Free Online tests/Materials Register at www.gateiespsu.com & Site: www.onlineies.com
For Regular udpates: www.facebook.com/onlineies Groups: http://groups.google.com/group/onlineies
Contact: (+91) 99003 99699 E-mail: onlineies.com@gmail.com
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
[A]
[B]
[C]
[D]
an
ga
lo
re
[A]
[C]
. [QDigA056] .. (
[B]
[D]
[A] 1, 2, 3
[C]3, 4 &5
S,
B
. [QDigA058] .. (
[B] 2, 3 &4
[D]1,3 &5
IE
22)Find the input conditions needed to produce X = 1 in the logic shown below
[A] 111
[C]011
[B] 101
[D]101
Page.No.25
For Free Online tests/Materials Register at www.gateiespsu.com & Site: www.onlineies.com
For Regular udpates: www.facebook.com/onlineies Groups: http://groups.google.com/group/onlineies
Contact: (+91) 99003 99699 E-mail: onlineies.com@gmail.com
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
23)A 3-line to 3-line decoder , with active low outputs is used to implement a 3-variable Boolean function as
shown in the figure
The simplified form of Boolean function f(x, y, z) implemented in sum of products form is
[A] xy + yz + zx
[C]
. [QDigA059] .. (
. [QDigA062] .. (
[B]
[D]
an
ga
lo
re
[A]
[C]
IE
S,
B
. [QDigA072] .. (
[B]
[D]
Page.No.26
For Free Online tests/Materials Register at www.gateiespsu.com & Site: www.onlineies.com
For Regular udpates: www.facebook.com/onlineies Groups: http://groups.google.com/group/onlineies
Contact: (+91) 99003 99699 E-mail: onlineies.com@gmail.com
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
. [QDigA074] .. (
an
ga
lo
re
. [QDigA082] .. (
. [QDigA083] .. (
. [QDigA086] .. (
[A] 8
[C]10
S,
B
28)Minimum number of two input NAND gates required to implement above circuit
[B] 9
[D]11
IE
[A]
[C]
[B]
[D]
30)For a binary half-subtractor having two inputs A and B, the correct set of logical expressions for the
outputs D (= A minus B) and X (= borrow) are
. [QDigA103] .. GATE-ECE/TCE-1999(
[A]
[C]
[B]
[D]
Page.No.27
For Free Online tests/Materials Register at www.gateiespsu.com & Site: www.onlineies.com
For Regular udpates: www.facebook.com/onlineies Groups: http://groups.google.com/group/onlineies
Contact: (+91) 99003 99699 E-mail: onlineies.com@gmail.com
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
31)For the logic circuit shown in the figure, the required input condition (A, B, C) to make the output (X) = 1 is
. [QDigA107] .. GATE-ECE/TCE-2000(
[A] 1, 0, 1
[B] 0, 0, 1
[C]1, 1, 1
[D]0, 1, 1
[A] A+B+C
[C]B
an
ga
lo
re
32)For the logic circuit shown in the figure, the simplified Boolean expression for the output y is
. [QDigA108] .. GATE-ECE/TCE-2000(
. [QDigA112] .. GATE-ECE/TCE-2001(
[B] A
[D]C
S,
B
IE
34)If the input to the digital circuit (in the figure) consisting of a cascade of 20 XOR- gates is X, then the
output Y is equal to
. [QDigA117] .. GATE-ECE/TCE-2002(
[A] 0
[C]
[B] 1
[D]X
35)The gates G1and G2 in the figure have propagation delays of 10nsec and 20 nsec respectively. If the input
Vi makes an abrupt change from logic 0 to 1 at time t = t0, then the output waveform V0 is
Page.No.28
For Free Online tests/Materials Register at www.gateiespsu.com & Site: www.onlineies.com
For Regular udpates: www.facebook.com/onlineies Groups: http://groups.google.com/group/onlineies
Contact: (+91) 99003 99699 E-mail: onlineies.com@gmail.com
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
[A]
[B]
[C]
[D]
. [QDigA119] .. GATE-ECE/TCE-2002(
. [QDigA125] .. GATE-ECE/TCE-2003(
an
ga
lo
re
37)The circuit shown in the figure has 4 boxes each described by inputs P, Q, R and outputs Y, Z with
. [QDigA127] .. GATE-ECE/TCE-2003(
IE
S,
B
. [QDigA132] .. GATE-ECE/TCE-2003(
[A] 1
[C]3
[B] 2
[D]4
Page.No.29
For Free Online tests/Materials Register at www.gateiespsu.com & Site: www.onlineies.com
For Regular udpates: www.facebook.com/onlineies Groups: http://groups.google.com/group/onlineies
Contact: (+91) 99003 99699 E-mail: onlineies.com@gmail.com
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
40)The Boolean function f implemented in the figure using two input multiplexers is
. [QDigA144] .. GATE-ECE/TCE-2005(
[A]
[C]
[B]
[D]
an
ga
lo
re
. [QDigA157] .. GATE-ECE/TCE-2006(
. [QDigA162] .. GATE-ECE/TCE-2007(
[B]
[D]A
[A]
[C]
[B]
[D]
S,
B
[A]
[C]
IE
43)Which of the following Boolean Expressions correctly represents the relation between P, Q, R and M1 ?
. [QDigA169] .. GATE-ECE/TCE-2008(
[A] M1 = (P OR Q) XOR R
[C]M1 = (P NOR Q) XOR R
Page.No.30
For Free Online tests/Materials Register at www.gateiespsu.com & Site: www.onlineies.com
For Regular udpates: www.facebook.com/onlineies Groups: http://groups.google.com/group/onlineies
Contact: (+91) 99003 99699 E-mail: onlineies.com@gmail.com
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
44)For the circuit shown in the following figure I0- I3 are input to the 4:1 multiplexer. R (MSB) and S are
control bits.
[B]
[D]
an
ga
lo
re
[A]
[C]
45)What are the minimum number of 2-to-1 multiplexers required to generate a 2-input AND gate and a 2input Ex-OR gate?
. [QDigA177] .. GATE-ECE/TCE-2009(
[A] 1 and 2
[C]1 and 1
[B] 1 and 3
[D]2 and 2
S,
B
46)Two products are sold from a vending machine, which has two push buttons P1 and P2. When a button is
pressed, the price of the corresponding product is displayed in a 7-segment display. If no buttons are
pressed 0 is displayed, signifying Rs. 0. If only P1 is pressed 2 is displayed signifying Rs.2
If only P2is pressed 5 is displayed signifying Rs. 5. If both P1 and P2are pressed E is
displayed.Signifying Error the names of the segments in the 7-segment display, and the glow of the
display for 0, 2 5 and E are shown below:
[A]
[C]
IE
Consider
(i) push button pressed/not pressed in equivalent to logic 1/0 respectively.
(ii) a segment glowing/not glowing in the display is equivalent to logic 1/0 respectively.
If segments a to g are considered as functions of P1 and P2, then which of the following is correct?
. [QDigA180] .. GATE-ECE/TCE-2009(
[B]
[D]
47)What are the minimum numbers of NOT gates and 2-input OR gates required to design the logic of the
driver for this 7-segment display?
[A] 3 NOT and 4 OR
[C]1 NOT and 3 OR
. [QDigA181] .. GATE-ECE/TCE-2009(
. [QDigA182] .. IES-ECE/TCE-1999(
Page.No.31
For Free Online tests/Materials Register at www.gateiespsu.com & Site: www.onlineies.com
For Regular udpates: www.facebook.com/onlineies Groups: http://groups.google.com/group/onlineies
Contact: (+91) 99003 99699 E-mail: onlineies.com@gmail.com
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
[B] Both A and R are true but R is not the correct
[A] Both A and R are true and R is the correct
explanation of A
explanation of A
[C]A is true but R is false
49)The given figure shows a NAND gate with input waveforms A and B
[B]
an
ga
lo
re
[A]
[D]
[C]
. [QDigA186] .. IES-ECE/TCE-1999(
[B] zero
[D]
IE
S,
B
[A] 1
[C]X
Page.No.32
For Free Online tests/Materials Register at www.gateiespsu.com & Site: www.onlineies.com
For Regular udpates: www.facebook.com/onlineies Groups: http://groups.google.com/group/onlineies
Contact: (+91) 99003 99699 E-mail: onlineies.com@gmail.com
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
an
ga
lo
re
51)The input waveform Vi and the output waveform V0 of a Schmitt NAND are shown in the given figures.
The duty cycle of the output waveform will be
[A] 100%
[C]72.2%
. [QDigA193] .. IES-ECE/TCE-1999(
. [QDigA195] .. IES-ECE/TCE-1999(
. [QDigA206] .. IES-ECE/TCE-2000(
[B] 85.5%
[D]25%
[C]
IE
[A]
S,
B
52)The logic circuit realized by the circuit shown in the given figure will be
[B]
[D]
[C]
[B]
[D]
Page.No.33
For Free Online tests/Materials Register at www.gateiespsu.com & Site: www.onlineies.com
For Regular udpates: www.facebook.com/onlineies Groups: http://groups.google.com/group/onlineies
Contact: (+91) 99003 99699 E-mail: onlineies.com@gmail.com
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
54)Which one of the following circuits is the minimized logic circuit for the circuit shown in figures I?
. [QDigA209] .. IES-ECE/TCE-2000(
[A]
[B]
[C]
[D]
an
ga
lo
re
. [QDigA210] .. IES-ECE/TCE-2000(
[A]
[C]
[B]
[D]
56)The logic operations of two combinational circuits given in Figure-I and Figure-II are
Figure-I
S,
B
Figure-II
. [QDigA211] .. IES-ECE/TCE-2000(
. [QDigA213] .. IES-ECE/TCE-2000(
[B] identical
[D]dual
IE
Page.No.34
For Free Online tests/Materials Register at www.gateiespsu.com & Site: www.onlineies.com
For Regular udpates: www.facebook.com/onlineies Groups: http://groups.google.com/group/onlineies
Contact: (+91) 99003 99699 E-mail: onlineies.com@gmail.com
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
[A] P = 0 and Q = 0
[C]P =1 and Q = 0
[D]P = 1 and Q = 1
an
ga
lo
re
. [QDigA216] .. IES-ECE/TCE-2000(
[A] 1, 2 and 4
[C]1, 3 and 4
[D]1, 2 and 3
. [QDigA226] .. IES-ECE/TCE-2000(
S,
B
IE
. [QDigA235] .. IES-ECE/TCE-2001(
62)The number of 4-line to-16 line decoders required to make an 8-line to 256 line decoder is
Page.No.35
For Free Online tests/Materials Register at www.gateiespsu.com & Site: www.onlineies.com
For Regular udpates: www.facebook.com/onlineies Groups: http://groups.google.com/group/onlineies
Contact: (+91) 99003 99699 E-mail: onlineies.com@gmail.com
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
. [QDigA238] .. IES-ECE/TCE-2001(
[A] 16
[C]32
[B] 17
[D]64
an
ga
lo
re
63)Consider the following circuits (Assume all gates to have a finite propagation delay)
. [QDigA252] .. IES-ECE/TCE-2002(
[A] 1 and 2
[C]2, 3 and 4
[B] 3 and 4
[D]1, 2, 3 and 4
S,
B
64)The addition of two binary variables A and B results into a SUM and a CARRY output . Consider the
following expressions for the SUM and CARRY outputs.
IE
[A] 1 and 3
[C]2 and 4
. [QDigA263] .. IES-ECE/TCE-2003(
[B] 2 and 3
[D]1 and 4
65)for a binary half- subtractor having two inputs A and B, the correct sets of logical expression for the output
D (= A minus B) and X (= borrow) are
. [QDigA264] .. IES-ECE/TCE-2003(
[A]
[C]
[B]
[D]
Page.No.36
For Free Online tests/Materials Register at www.gateiespsu.com & Site: www.onlineies.com
For Regular udpates: www.facebook.com/onlineies Groups: http://groups.google.com/group/onlineies
Contact: (+91) 99003 99699 E-mail: onlineies.com@gmail.com
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
. [QDigA265] .. IES-ECE/TCE-2003(
[B] OR gate
[D]NAND gate
67)For the output F to be 1 in the logic circuit shown , the input combination should be
. [QDigA277] .. GATE-ECE/TCE-2010(
[A] A = 1 , B = 1 , C = 0
[C]A = 0 , B = 1 , C = 0
[B] A = 1 , B = 0 , C = 0
[D]A = 0 , B = 0 , C = 1
an
ga
lo
re
. [QDigA281] .. GATE-ECE/TCE-2011(
IE
S,
B
69)The logic function implemented by the circuit below is (ground implies a logic " 0 " )
. [QDigA284] .. GATE-ECE/TCE-2011(
[B] F = OR (P, Q)
[D]F = XOR (P, Q)
. [QDigA285] .. IES-ECE/TCE-2004(
[A] (1,0,1)
[C](1,1,1)
[B] (0,0,1)
[D](0,1,1)
71)The output Y of a 2-bit comparator is logic 1 whenever the 2-bit input A is greater than the 2-bit input
B . The number of combinations for which the output is logic 1 , is
Page.No.37
For Free Online tests/Materials Register at www.gateiespsu.com & Site: www.onlineies.com
For Regular udpates: www.facebook.com/onlineies Groups: http://groups.google.com/group/onlineies
Contact: (+91) 99003 99699 E-mail: onlineies.com@gmail.com
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
. [QDigA288] .. GATE-ECE/TCE-2012,GATE-EEE-2012(
[A] 4
[C]8
[B] 6
[D]10
an
ga
lo
re
. [QDigA295] .. GATE-ECE/TCE-2010(
[B]
[A]
[C]
[D]
75)A 1-bit full adder takes 20 ns to generate carry-out bit and 40 ns for the sum bit. What is the maximum rate
of addition per second when four 1-bit full adders are cascade?
S,
B
[A] 107
[C]6.25 x 106
. [QDigA304] .. IES-ECE/TCE-2005(
. [QDigA314] .. IES-ECE/TCE-2005(
IE
[B] 1 only
[D]None of the above
77)What is the output f (x,y) of the multiplexer resulting from the input logical values?
Page.No.38
For Free Online tests/Materials Register at www.gateiespsu.com & Site: www.onlineies.com
For Regular udpates: www.facebook.com/onlineies Groups: http://groups.google.com/group/onlineies
Contact: (+91) 99003 99699 E-mail: onlineies.com@gmail.com
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
. [QDigA315] .. IES-ECE/TCE-2005(
an
ga
lo
re
78)Figure shows a 4 to 1 MUX to be used to implement the sum S of a 1-bit full adder with input bits P and Q
and the carry input
. Which of the following combinations of inputs to
of the MUX will
realize the sum S ?
. [QDigA317] .. GATE-EEE-2002(
[A]
[C]
[B]
[D]
S,
B
IE
. [QDigA322] .. GATE-EEE-2004(
80)A 4 x 1 MUX is used to implement a 3-input Boolean function as shown in figure. The Boolean function
F(A, B, C) implemented is
. [QDigA328] .. GATE-EEE-2006(
[A]
[C]
[B]
[D]
Page.No.39
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
81)A, B, C, and D are input, and Y is the output bit in the XOR gate circuit of the figure below. Which of the
following statements about the sum S of A, B, C, D and Y is correct ?
. [QDigA329] .. GATE-EEE-2006(
82)For the circuit shown in the below figure, the output F will be
. [QDigA334] .. IES-EEE-2001(
[B] zero
[D]
an
ga
lo
re
[A] 1
[C]X
[A]
[C]
. [QDigA339] .. IES-EEE-2002(
. [QDigA340] .. IES-EEE-2002(
. [QDigA341] .. IES-EEE-2002(
. [QDigA344] .. IES-EEE-2002(
[B] ABC
[D]
84)To add two m-bit numbers , the required number of half adders is
[A] 2 m - 1
[C]2 m + 1
[B]
[D]2 m
IE
[A] 1 , 2 and 3
[C]2, 3 and 4
S,
B
[B] 1, 3 and 4
[D]1, 2 and 4
All the output lines of the chip will be high, when all the inputs 1, 2 and 3
,
,
are low
are high
is low , is high
is high , is low
Page.No.40
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
87)Which one of the following statements is not correct ? Conversion of EXCESS-3 code to BCD can be
achieved by using
. [QDigA353] .. IES-EEE-2003(
[B] 4 : 16 de-multiplexer
[D]A 4-bit half adder
88)Match List-I (operation) with List-II (Associated Device) and select the correct answer using the codes
given below :
List-I List-II
A. Counting 1. ROM
B. Decoding 2. Multiplexer
C. Data selection 3. Demultiplexer
D. Code conversion 4. Register
. [QDigA362] .. IES-EEE-2004(
an
ga
lo
re
. [QDigA364] .. IES-EEE-2004(
[A] n
[C]
[B]
[D]
Which one of the following gives the function implemented by the MUX based digital circuit ?
S,
B
. [QDigA365] .. IES-EEE-2004(
[A]
[C]
[B]
[D]
[A]
[C]
IE
91)A range decode is a digital circuit which outputs as 1 whenever an m-bit number X falls within the range
X , 0 P, q m 1.
Which one of the following functions describes the range decoder?
. [QDigA367] .. IES-EEE-2004(
[B]
[D]
92)What are the output bits S (sum) and C (Carry) of a Half adder having inputs A = 1 and B = 1 ?
[A] S = 1, C=1
[C]S = 0 , C = 1
. [QDigA381] .. IES-EEE-2007(
. [QDigA383] .. IES-ECE/TCE-2005(
[B] S = 1, C= 0
[D]S = 0 , C = 0
93)Which one of the following functions realized by the circuit shown below?
[A]
[C]AB+C+DE
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
. [QDigA384] .. IES-ECE/TCE-2005(
an
ga
lo
re
96)What is the number of selector lines required in a single input n-output demultiplexer?
[A] 2
[C]2n
. [QDigA395] .. IES-ECE/TCE-2006(
. [QDigA414] .. IES-ECE/TCE-2006(
. [QDigA419] .. IES-EEE-2009(
[B] n
[D]log2n
97)I =1, J = B
S,
B
IE
98)Which one of the following is the correct output ( f ) of the below circuit ?
[A]
[C]
[B]
[D]
99)Which one of the following logical operations is performed by the digital circuit shown below?
. [QDigA424] .. IES-ECE/TCE-2006(
[A] NOR
[B] NAND
Page.No.42
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
[D]OR
[C]EX-OR
100)When two 16-input multiplexers drive a 2-input MUX, what is the result?
[A] 2-input MUX
[C]16-input MUX
. [QDigA432] .. IES-ECE/TCE-2007(
. [QDigA436] .. IES-ECE/TCE-2007(
101)For the logic circuit given above, what is the simplified Boolean function?
[A] X=AB+C
[C]X=AB+AC
[B] X=BC+A
[D]X=AC+B
an
ga
lo
re
. [QDigA442] .. IES-ECE/TCE-2007(
. [QDigA447] .. IES-EEE-2010(
IE
[A]
[C]
S,
B
[B] 0
[D]
104)For logic circuit shown , the required inputs A, B and C to make the output X = 1 are respectively
. [QDigA456] .. IES-EEE-2011(
[A] 1, 0 and 1
[C]1 , 1 and 1
[B] 0, 0 and 1
[D]0 , 1 and 1
Page.No.43
For Free Online tests/Materials Register at www.gateiespsu.com & Site: www.onlineies.com
For Regular udpates: www.facebook.com/onlineies Groups: http://groups.google.com/group/onlineies
Contact: (+91) 99003 99699 E-mail: onlineies.com@gmail.com
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
105)The black box in the above figure consists of a minimum complexity circuit that uses only AND OR and
NOT gates.
The function f (x,y,z) = 1 whenever x,y are different and 0 otherwise. In addition the 3 inputs x,yz are never
all the same value which one of the following equations leads to the correct design for the minimum
complexity circuit?
. [QDigA459] .. IES-ECE/TCE-2007(
[A]
[C]
[B]
[D]
an
ga
lo
re
106)
. [QDigA460] .. IES-ECE/TCE-2007(
. [QDigA461] .. IES-ECE/TCE-2007(
[B] OR gate
[D]NAND gate
S,
B
. [QDigA474] .. IES-ECE/TCE-2008(
[B] 2, 3 and 4
[D]2 and 3 only
IE
[A] 1, 3 and 4
[C]1 and 2 only
109)For the logic circuit shown in the below figure. What is the required input condition (A.B,C) to make output
X = 1?
. [QDigA478] .. IES-ECE/TCE-2008(
[A] 1, 0, 1
[C]1, 1, 1
[B] 0, 0, 1
[D]0, 1, 1
Page.No.44
For Free Online tests/Materials Register at www.gateiespsu.com & Site: www.onlineies.com
For Regular udpates: www.facebook.com/onlineies Groups: http://groups.google.com/group/onlineies
Contact: (+91) 99003 99699 E-mail: onlineies.com@gmail.com
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
. [QDigA479] .. IES-ECE/TCE-2008(
[A] 0
[C]
[B] 1
[D]
an
ga
lo
re
. [QISRA067] .. ISRO-ECE/TCE-2012(
[A]
[C]
[B]
[D]None of above
112)Minimum number of 2-input NAND gates that will be required to implement the function :
Y = AB + CD + EF is
. [QISRA358] .. ISRO-ECE/TCE-2008(
. [QISRA360] .. ISRO-ECE/TCE-2008(
[B] 5
[D]7
S,
B
[A] 4
[C]6
114)A half-adder can be constructed using two 2-input logic gates . One of them is an AND-gate , the other is
IE
[A] OR
[C]NOR
. [QISRA418] .. ISRO-ECE/TCE-2007(
. [QISRA424] .. ISRO-ECE/TCE-2007,ISRO-ECE/TCE-2007(
[B] NAND
[D]EX-OR
115)The Boolean expression for the output of the logic circuit shown in the figure is
[A]
[C]
[B]
[D]
[A]
[C]
[B]
[D]
Page.No.45
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
117)The combinational logic circuit shown in the given figure has an output Q which is
. [QISRA431] .. ISRO-ECE/TCE-2007(
[A] ABC
[C]
[B] A + B + C
[D]A.B + C
118)The sum S of A and B in a half Adder can be implemented by using K NAND gates . The value of K is
. [QISRA437] .. ISRO-ECE/TCE-2007(
[A] 3
[C]5
[B] 4
[D]None of these
into
an
ga
lo
re
. [QISRA516] .. ISRO-ECE/TCE-2006(
IE
S,
B
Page.No.46
For Free Online tests/Materials Register at www.gateiespsu.com & Site: www.onlineies.com
For Regular udpates: www.facebook.com/onlineies Groups: http://groups.google.com/group/onlineies
Contact: (+91) 99003 99699 E-mail: onlineies.com@gmail.com
Institute of Engineering Studies (IES,Bangalore), leading Institute for Engineers in Bangalore (Jayanagar & Malleshwaram)
Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
www.youtube.com/onlineies
Key Paper
D
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.
36.
37.
38.
39.
40.
41.
42.
43.
44.
45.
46.
47.
48.
49.
50.
51.
52.
53.
54.
55.
56.
57.
58.
59.
60.
61.
62.
63.
64.
65.
66.
67.
68.
69.
70.
71.
72.
73.
74.
75.
76.
77.
78.
79.
80.
81.
82.
83.
84.
85.
86.
87.
88.
89.
90.
91.
92.
93.
94.
95.
96.
97.
98.
99.
100.
101.
102.
103.
104.
105.
106.
107.
108.
109.
110.
111.
112.
113.
114.
115.
116.
117.
118.
119.
an
ga
lo
re
1.
IE
S,
B
Page.No.47
For Free Online tests/Materials Register at www.gateiespsu.com & Site: www.onlineies.com
For Regular udpates: www.facebook.com/onlineies Groups: http://groups.google.com/group/onlineies
Contact: (+91) 99003 99699 E-mail: onlineies.com@gmail.com