Spring 2014

Name: SOLUTIONS + grading instructions

I.D.:_______________________________

EE 2301 INTRODUCTION TO DIGITAL SYSTEMS DESIGN

Test #1

Problem 1

_______________

(15 pts.)

Problem 2

_______________

(20 pts.)

Problem 3

_______________

(15 pts.)

Problem 4

_______________

(20 pts.)

Problem 5

_______________

(20 pts.)

Total

_______________

(90 pts.)

Remember to put your name and I.D.# on this exam.

**

Show all your work (except for multiple choice problems).

Check that you have completed all parts of all five problems. Do not spend all your time
on one problem, since time is limited.

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Write solutions only on the front side of the exam sheets and only on the page associated
with the problem. Solutions given in other locations will not be graded. The last page is
intentionally left blank you can use it as scratch paper and can tear it off.

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Read and solve each problem carefully, since partial credit will be limited!

Problem 1
The following statements can be interpreted as Boolean variables with truth values 0/1(true/false)
A ~ The lecturer is one with hand in your pocket
B ~ The lecturer is one with his tongue in your ear
C ~ The lecturer is not one with his faith in your patience
Consider the following compound statement:
Z ~ The lecturer is EITHER (one with hand in your pocket AND his tongue in your ear) OR one
with his faith in your patience.
Note: EITHER OR connective (in plain English) corresponds to Exclusive-OR operation in
Boolean algebra
(a) Show the Boolean expression for Z as a function of A, B, C
Z = (AB) C = ABC +AC + BC
(b) Implement Z found in (a) using only 3 two-input NAND gates and one three-input NAND
gate. Assume that input variables A,B,C are available in direct and complemented form.
Z = ABC + C(A+B) = [(ABC)[C(AB)]]
A
B
C
Z
A
B
C

Then convert to NAND gate network by adding bubbles.

A
B
C
Z
A
B
C

(c) Show the minterm canonical form for Z (A,B,C)

Note: use decimal notation for minterms in your final answer
Z = ABC +AC + BC= ABC +ABC + ABC + ABC= m(0,2,4,7)
Grading: (a) (c) ~ 5 points each

Problem 2
(a) Show the Boolean expression Z (A,B,C,D) for this switching network:
A

Show all input-output paths:

Z (A,B,C,D) = ABC + ACA + DCBC + AD = ABC + AD

(b) Simplify the Boolean expression found in (a) to a minimal standard form, using algebraic
manipulations:
Min standard form, in this case, is min SOP form ABC + AD

(c) Implement the expression found in part (b) using two-level NAND or two-level NOR gate
network (whichever is more appropriate):
Min SOP form gives the two-level NAND gate network
Z = [(ABC+AD)] = [(ABC)(AD)]

(d) Does your implementation in part (c) have static-1 hazards or static-0 hazards? If so, identify
these hazards using K-map technique and then show how to remove them.
01

11

00

01

AB
CD

00

10

11
10

Static-1 hazard: ABCD

1100
0100
This static-1 hazard can be removed by including additional NAND gate that implements
the product term BCD
Grading: 5 points each part (a) (d)

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Problem 3
Consider Boolean function specified as a product of maxterms f(w,x,y,z)= M(1,3,4,6,9,11) .
For this function:
a) Show its minterm canonical form (using decimal notation for minterms).
b) Using K-map, find all prime implicants of f(w,x,y,z).
c) Show the prime implicant chart, then find essential prime implicants (using this
chart), and show a minimal sum-of-products expression for f .

(a) f(w,x,y,z) = m(0,2,5,7,8,10,12-15)

(b)
wx
yz
00

00

01

11

10

01

11

10

Prime implicants are wx, xz, xz, wz

(c)
0
wx
xz
xz
wz

10 12 13 14 15
X X X X
X X
X
X
X X
X X
X
X X X
X

Unique minterms and the corresponding essential prime implicants are shown in red.
Minterms 12 and 14 are not covered by these two essential PIs.
Hence, min SOP form can be formed by adding either the term wx or wz to essential PIs
f(w,x,y,z) = xz + xz + wx
= xz + xz + wz
(both solutions are correct).
Grading: (a) 4 points, (b) 6 points (c) 5 points

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Problem 4
(a) Using algebraic manipulations, show that the following two circuits realize the same function,
i.e., show that f =G.
(i)
x
y

(ii)
X
Y
Z

F = (x+y)z + xyz = (x+y)z + (x+y)z = (x+y+z)(x+z)(y+z) = G

(b) Assuming the circuit in Fig. (i) above has a logic stuck-at-1 fault on the internal line m, find
all tests that can detect this fault.
True f = (x+y)z + xyz
faulty output f = (x+y)z + yz
The fault is detected when f f = 1
f = 1 and f = 0. This can never happen since the condition f = (x+y)z + yz implies f =0
f = 0 and f = 1. This can happen only when (x+y)z =0 and x=1 and yz=1.
This condition is satisfied for xyz = 110 this is the only test to detect this fault.
(c) Identify all static hazards (if they exist) for the circuit shown in Fig. (ii) above.
This circuit can have only static-0 hazards. K-map shows that there are no static-0
hazards.

YZ
X
0

00
0

01

11
0

Grading: (a) 8 points, (b) 6 points (c) 6 points

10

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Problem 5
(a) Consider a simple comparator circuit that compares two binary inputs, X and Y, and
generates a binary output Z, such that Z=1 if and only if these inputs are equal (i.e. X=Y).
Implement this comparator using discrete (AND, OR, NOT) gates.
Z = ( X Y ) = ( X Y ) ' = XY + X ' Y '

(b) Show how to implement the comparator in Part (a) using 3-input minority gates defined as
follows: M(x,y,z) = 1 if and only if the total number of input 1s is smaller than 0s (that is,
output M=1 if there are no input 1s or just a single input 1 among gate inputs x,y,z)
Hint: you can use logic 1 and logic 0 as inputs to M gate(s).
Note that M(1,x,y) = xy , M(0,x,y) = x+y and M(0,1,x) = x
So the comparator function Z = xy + xy can be implemented using only M gates as
shown below.
1
X
Y

XY

0
1
X

X
0

0
1
Y

Z = X Y + XY

X + Y

0
1

XY

(c) Show how to implement the comparator in part (a) using a full adder (FA) shown below.
Note that a full adder implements the following Boolean functions:
S = (A B) Ci
Co = (A B)Ci + AB

X
A

1
B

Ci

FA
Co

S
Z

Use output S = A B Ci to implement the comparator Z = X Y 1 = ( X Y ) ' .

Grading: (a) 6 points, (b) 8 points (c) 6 points