LAB VI.

SMALL SIGNAL MODELS

OF PN JUNCTION DIODES
1. OBJECTIVE
In this lab, you will study the small signal models of the p-n junction diodes. Using the
measurements made, we will obtain the small signal elements, and use them to construct a circuit
model of the diode around the operating point.

2. OVERVIEW
There are many cases where diodes are operated with small AC signals around a DC offset
voltage. In such a case, we can use a linear small-signal diode model. In forward bias, a diode is
modeled with two components: a diode resistance (rd), and charge storage capacitance (CCS). In
reverse bias, a diode is represented with only the depletion capacitance (CD). In the lab, you will
use the testing station to find the values of these components at a specific operating point.
Information essential to your understanding of this lab:
1. The characteristics of p-n junction diodes
2. Piecewise-linear approximations of p-n junction diodes (Section 5.4.3 in Streetman
and Banerjee)
3. Basic background from Network Analysis and Physics
Materials necessary for this Experiment:
1. Standard testing station
2. One rectifier diode
3. Three resistors: 10 , two 10 k resistors
4. One capacitor: 1 F
5. One inductor: 560 H

3. BACKROUND INFORMATION
3.1 CHART OF SYMBOLS
Here is a chart of symbols used in this lab manual. This list is not all inclusive; however, it
does contain the most common symbols and their units.

Table 1. Chart of the symbols used in this lab.

Symbol
+
h

Symbol Name
Hole

Units
Positive charge particle

e
Q
P

electron

Negative charge particle

magnitude of electronic charge

hole density

1.6 x 10 C
+
3
(number h / cm )

N
ni
NA
ND
kb
T
Eg
A

electron density
intrinsic electron density
Acceptor
Donor
Boltzmann's constant
Temperature
energy gap of semiconductor
junction area

(number e / cm )
3
(number e / cm )
3
(number acceptors / cm )
3
(number donors / cm )
-23
1.38 x 10 joules / K
K
eV
2
cm

6-1

-19

g
w
Vbi
VD
vd
vD
0
r
pn
np

general carrier lifetime

depletion width
built in voltage

sec
cm
V

DC diode voltage
AC diode voltage
total diode voltage
permittivity of free space
relative dielectric constant
hole concentration at depletion edge
electron concentration at depletion edge

V
V
V
-14
8.85 x 10 F / cm
Scalar(varies on material)
3
h / cm
3
e / cm

3.2 CHART OF EQUATIONS

All of the equations from the background portion of the manual are shown in the
table below.
Table 2. Chart of the equations used in this lab.
Equation Name
1
Ideal Diode Equation

Formula

Effective Resistance
Approximation

1 i D

rd v D

Effective Resistance
Approximation from Ideal
Diode Equation
Charge Storage
Capacitance

Charge Storage in p-type

and n-type Regions due to
Holes and Electrons

I D I 0 e ( qVD / nkT ) 1

rd

( I D ,VD )

i D
v D

( I D ,VD )

7
8

Charge Storage
Capacitance from the Ideal
Diode Equation
General Recob. Life
Time
Definition of Depletion
Capacitance for Small
Signal Model
Formula for the Depletion
width around 0 V

10

Formula for the Contact

Potential or Built in Voltage

11

Equilibrium Depletion
Capacitance

( I D ,VD )

nk bT
qI D

CCS

p n Qtotal

v D
v D

Qp ID p qAL p ( pn e

qVD

kb T

qVD

Qn ID n qALn (n p e
6

id
vd

CCS

kb T

1)

1)

q g I D

nk bT
g rd CCS

CD

dQd Qd

dvd
vd

N ND
2 0 r
(Vbi VD ) A
q
NAND

k T N N
Vbi b ln D 2 A
q ni
0 r A
C D (VD 0)
w(VD 0)

6-2

12

13

Depletion Capacitance for

an Abrupt Junction

CD

Depletion Capacitance for a

linearly graded junction

CD

CD (VD 0)
1

V 2
D
1
V

bi
CD (VD 0)
1

V 3
D
1
Vbi

3.3 SMALL SIGNAL DIODE MODELS

The current response of a diode
is approximated as:

I D I 0 e ( qVD / nkT ) 1 .

(1)

This is clearly a non-linear function. However, in many applications, a diode is operated at a fixed
DC voltage with an accompanying small AC voltage and in such a small variation of the input, the
diode I-V characteristics can be treated as a linear function. For example, your diode may be
operating at 0.5 V DC and you need to know what the current response of the circuit is due to a 10
mV AC signal that is added to the DC offset. In such a case, you could use a small signal diode
model which has a linear I-V characteristic. The approximated small signal diode model consists
of a parallel combination of resistors and capacitors as shown in Figure 1, where VA is dc signal, va
is ac signal. The transition region can be represented by a parallel connection of CD the depletion
capacitance, CCS the charge storage capacitance, and rd the junction resistance. Note that the series
resistance RS discussed in the Lab 4 represents the contact resistance and the resistance in the
neutral regions (outside of the transition region) of the diode. Assuming that the contact resistance
of the diode is negligible, in the forward bias, Rs is negligible unless the diode is operated in high
level injection region.

CD

CCS

rd
Figure 1. Small signal approximation models for a p-n junction diode.

3.4 JUNCTION RESISTANCE rd

When modeling a forward or reverse biased diode, you will have to take into account the
resistance. It is important to note that the model resistance that we are using is not the actual
resistance of the n-type and p-type semiconductor regions but is the effective resistance
experienced by the circuit in an operating region. Remember this is a circuit model
approximation. To develop this effective resistance we apply the following equation to the I-V
characteristic.

6-3

1 i D

rd v D

( I D ,VD )

i D
v D

( I D ,VD )

id
vd

(2)
( I D ,VD )

Equation 2 simply states that the slope at the DC offset voltage and current pair (ID,,VD) gives our
models conductance (1/rd). The conductance may be approximated by the change in iD (total
current) divided by the change in vD (total voltage) at the DC operating point (ID,VD). The
conductance is effectively equal to the small signal current over the small signal voltage at the DC
operating point.

Figure 2. A small signal linear model of the diode, where GP is conductance (1/rd) of the diode.
It is essential that you note the I-V characteristic of a diode in all the regions of operation.
Recall that the current in the reverse bias region of operation is very small, therefore in reverse bias
the resistance will be extremely large. For this reason, the resistance rd is often neglected and
treated as an open circuit for the reverse biased diode model. In forward bias, you will need to find
rd as it will make an impact on your diode model. In the preparation section, you will be asked to
prove that rd can be expressed as,

rd

nk bT
qI D

(3)

where ID is the current point at which the resistance is being found.

3.5 CHARGE STORAGE CAPACITANCE CCS

In the forward biased diode model, there are two elements to consider: the charge storage
capacitance (CCS), and junction resistance (rd). The charge storage capacitance arises in a diode
due to minority carriers that diffuse across the junction and are stored on the other side of the
junction.
Examine Figure 3. This figure shows hole concentration distribution in the n-side near the
transition region. When a diode is forward biased, it will inject an excess hole concentration into
the n-type edge of the depletion region by diffusion. Likewise, the excess electron concentration at
the p-type edge of the depletion region will increase by diffusion. Recombination of minority
carriers causes the carrier concentration curves p(xn) and n(xp) to decrease exponentially until they
reach the equilibrium minority carrier concentrations np0 and pn0 as they extend from the edges of
the depletion region. The difference in charge between the carrier concentration curves and the

6-4

equilibrium minority carrier concentrations is the charge storage that occurs due to diffusion of
each type of minority carrier, which we will denote as Qn and Qp. If the diode is forward biased
with a DC voltage V, steady supply of minority charge carriers into the other sides will maintain
the stored charge as constant. Now, suppose you apply small ac signal with the forward bias (DC
offset V). The depletion region will shrink and the charge stored in the diffused carrier
concentration will increase as the diode is increasingly forward biased by the small signal voltage
vd. The opposite is true as well, if vd reduces the forward bias then the stored charge will be
reduced. .

Figure 3. The stored charge carriers.

If the total voltage is found to change by vD then the excess minority charge carriers
change the stored charge by Qn and Qp. Using the definition of capacitance we find that,

CCS

Q p Qn
v D

Qtotal
,
v D

(4)

where CCS is the charge storage capacitance. Qn and Qp can be found by the following equations:
qVD

Qp ID p qAL p ( pn e
Qn ID n qALn (n p e

kb T

qVD

kb T

1)
(5)

1)

Notice that the charge in each region is equal to the current times the carrier lifetime in its
respective region. It follows from these equations that the charge storage capacitance is:

CCS

q g I D
nk bT

(6)

Here ID is the current flowing at the DC operating point and g is the general or average minority
carrier lifetime as a whole, not the individual hole or electron lifetimes. Using equations (3) and
(6), the value of g is found to be:
g = rdCCS

(7)

3.6 DEPLETION CAPACITANCE CD

The depletion region consists of ionized acceptors (- charge) and ionized donors (+
charge). This can be approximated as a parallel plate capacitance with the effective gap of W
(depletion region width) as shown in Figure 4. When a diode is forward biased, the depletion
region will be narrowed and the depletion capacitance (CD) will be increased. When a diode is
reverse biased, the depletion region will be widened and the depletion capacitance (CD) will be
decreased.

6-5

It should be noted that the depletion capacitance does not play a major role in the forward bias
diode model. This is because the depletion capacitance (CD) and the charge storage capacitance
( CCS ) are in parallel with each other. Capacitors in parallel combine like resistors in series. The
charge storage capacitance will become extremely large as the diode is forward biased.
Consequently, when you combine the two capacitors, you will find that only the CCS plays a role in
our diode model.
When a diode is reverse biased, the charge storage capacitance (CCS) would be zero, the
junction resistance rd would approach infinity and only Depletion Capacitance (CD) plays a role.

Figure 4. A graphical depiction of the depletion width of a p-n diode in reverse bias.
Capacitance is defined to be the derivative of the charge with respect to the voltage. If we
apply the definition of capacitance to the junction of a diode you find

CD

dQd Qd
,

dvd
vd

(8)

where vd is the small signal voltage and Qd is the charge in the depletion region. In order to find
the space charge in the depletion region, you must find how far the depletion region width extends
into both the n-type and the p-type materials and sum up the charge density profile for the depletion
region. The depletion region width W is given by:

N ND
2 0 r
(Vbi v D ) A
q
NAND

(9)

where W is the depletion region width, the 0 is the permittivity of free space, r is the relative
permittivity of the diode material, Vbi is the contact potential (built in voltage), and vD is the sum of
the DC and AC voltage signals. Vbi may be calculated by:

k T N N
Vbi b ln D 2 A .
q ni

(10)

We will assume the depletion capacitance (CD) can be approximated by the parallel plate
capacitance equation. The depletion capacitance at equilibrium (applied voltage of 0 V) is

C D (VD 0)

0 r A

W (VD 0)

(11)

When analyzing an abrupt junction diode, the charge concentration on both sides of the junction is
a constant and does not vary with movement in the lattice. For an abrupt junction, the small
signal depletion capacitance is:

CD

CD (VD 0)
1

V 2
D
1
V

bi

6-6

(12)

ND - N A
ND > NA in this
region. Notice
how the doping
density does
not change up
to the junction

NA > ND in this
region. Notice
how it too is
constant up to
x the junction
Junction

Figure 5. One dimensional view of the doping profile of an abrupt junction diode.
Many practical semiconductor devices have doping densities that are non-uniform in the
region of the junction, as in Figure 6. In some cases where a junction is created by diffusing a
dopant into a uniformly doped substrate, the charge density may be approximated as a linearly
graded junction. In a linearly graded junction the depletion capacitance is

CD

CD (VD 0)

ND - N A

ND > NA in this
region. Notice
how the doping
density falls off
exponentially
as it approaches
the junction.

(13)

V 3
D
1
V

bi

The depletion width is small compared to the

width of the doping profile in the area of the red
line, which shows that the doping density can be
approximated as linear for that region.
x

Junction

NA - ND in this
region. Notice
how it decays
to a constant
away from the
junction area.

Figure 6. One dimensional view of the doping profile of a linearly graded junction diode.

4. PREPARATION
1. Suppose you have a diode which has the following characteristics: an abrupt junction, the
room temperature is 300 K, NA = 1018 cm-3, ND = 1013 cm-3, its made of Si, cross sectional
area of the junction A=10-5 cm2, r = 11.8, and ni (300 K) = 1.5 x 1010 cm-3.
a.) Calculate the built in voltage of the diode.
b.) Calculate the depletion region width of your diode without any bias.
c.) How much of the depletion width extends into the n-type material and how much
of it extends into the p-type material with no bias voltage applied?
d.) Find the depletion capacitance without any bias (CD (VD=0)).
e.) If you applied -10 V to the anode and the cathode is grounded, what is the
depletion capacitance of your diode?
2. Outline sections 3.3 3.6 of the lab manual. Take note of main concepts contained in each
section.

6-7

5. PROCEDURE
5.1 FORWARD BIAS DIODE
Examine Figure 7 below. The function generator puts out the small signal voltage vd which
passes through the capacitor C1. The capacitor C1 blocks all DC voltages and only passes AC
signals. The lower Keithley supplies a DC offset voltage which passes through L1, which then
supplies the voltage VD to the top node. When you sum the two aforementioned voltages together
they form the voltage vD (DC + AC) at the top node. The voltage vD is applied to the 10 ohm
resistor (R1) and is measured by Channel 1 of the oscilloscope. Channel 2 of the oscilloscope
measures the voltage signal across the diode. The current iD generated across the resistor can be
calculated by subtracting the voltage measured across the diode by Channel 2 from the voltage D
measured across the entire branch by Channel 1 divided by the value of R1. The current will have
to remain the same throughout the branch due to Kirchoffs current law so you now have the
voltage and current though your diode at a set DC offset. The program will calculate the value of
rd from equation (2) by using the slope of the I-V curve and then output rd versus the diode current.
C1

L1
560 H
inductor

1 F

Function
Generator
50mVpp

Oscilloscope
Channel 1

R1

10
Lower
Keithley

Oscilloscope
Channel 2

D1

1N4002

Figure 7. Circuit for the measurement of junction resistance rd and charge storage
capacitance CCS.
Measure rd: Load Smallsignal RD.vi. Program the equipment to the following settings.
1. Set the bottom Keithley to the following values using the Smallsignal RD.vi program.
(Start: 1.5V, Increment: 0.05 V, Final: 3.0 V).
2. Set the function generator to 50 mV, and 1000 Hz.
3. Build the circuit shown in Figure 7 and run the program.
The program will give you rd as a function of ID.
Measure CCS: Load Smallsignal CD.vi. Program the equipment with the following settings.
1. Set the bottom Keithley to the following values using the aforementioned program.
(Start: 1.5V, Increment: 0.05 V, Final: 3.0 V).
2. Set the function generator to 50 mV, and 100 kHz.
3. Build the circuit shown in Figure 7 and run the program.
The output will be a graph CCS as a function of ID.
If you integrate current with respect to time you have the charge. By using equation (4), the
computer can calculate CCS.

6-8

5.2 REVERSE BIAS DIODE

Examine Figure 8 below. Change the diode direction as shown in the Figure. Replace R1
with 10 k, and L1 with 10 k resistor as well. Like the previous circuit, the function generator
puts out the small signal voltage vd which passes through the capacitor C1 and the lower Keithley
supplies a DC voltage which passes through R2, which then supplies the voltage D to the top node.
The current is calculated by the difference of the voltages measured through Channel 1 and
Channel 2 divided by R1 and the voltage across the diode is measured by Channel 2, so now you
have both the small signal voltage and current. Recall that in reverse bias, the junction resistance is
extremely large (close to an open circuit) and a diode can be modeled with only the depletion
capacitance. In the phasor domain, Ohms Law for capacitor is:

v d id

(14)

j (2 f )C

The computer then solves for CD using (14).

Function
Generator
50 mVpp

C1

R2

1 F

10 k

Oscilloscope
Channel 1

R1

10 k
Lower
Keithley

Oscilloscope
Channel 2

D1

1N4002

Figure 8: This schematic is to be use to determine CD.

Measure CD: Load Smallsignal CT.vi. Program the equipment with the following settings.
1. Set the bottom Keithley to the following values using the program:
Increment: 0.05 V, Final: 3.0 V).
2. Set the function generator to 50 mV, and 100 kHz.
3. Build the circuit shown in Figure 8.

(Start: 0V,

The output will be a graph of CD as a function of VD.

6. LAB REPORT

Write a summary of the experiment.

Small Signal Effective Resistance
o Create a Linear vs. Linear plot for rd as a function of the diode current. Make sure
both axes are labeled and the graph is appropriately titled.
o Explain why the diode resistance rd decreases as the diode current increases.
o Calculate theoretical rd (Id) based on the equation (3) and compare with the measured
results. Use both ideality factor n=1 and n=2 for this calculation. Plot both the

6-9

measured rd (Id) and the theoretical rd (Id) based on equation (3) with the best matching
ideality factor. Does the measured rd (Id) found agree with the theoretical rd (Id)?
Small Signal Charge Storage Capacitance
o Create a Linear vs. Linear plot for the CCS measurements as a function of the diode
current. Make sure both axes are labeled and the graph is appropriately titled.
o Explain why Ccs increases as the diode current increases.
o Use your data for rd and CCS to plot the rd x CCS product. According to equation (7),
this should yield the general carrier lifetime in your diode. Is the plot a constant
independent of the diode current? Should it be? Estimate the carrier lifetime from the
plot.
Small Signal Depletion Capacitance
o Create a Linear vs. Linear plot for the CD measurements as a function of the reverse
bias voltage. Make sure both axes are labeled and the graph is appropriately titled.
o Explain why CD decreases as the reverse bias increases.
o Determine the depletion capacitance CD at VD = 0.

6-10