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Ad5253 5254
Ad5253 5254
Data Sheet
FEATURES
APPLICATIONS
Mechanical potentiometer replacement
Low resolution DAC replacement
RGB LED backlight control
White LED brightness adjustment
RF base station power amp bias control
Programmable gain and offset control
Programmable attenuators
Programmable voltage-to-current conversion
Programmable power supply
Programmable filters
Sensor calibrations
GENERAL DESCRIPTION
RDAC EEMEM
VDD
VSS
DGND
EEMEM
POWER-ON
REFRESH
RAB TOL
RDAC0
RDAC0
REGISTER
A0
W0
B0
WP
SCL
SDA
AD0
AD1
DATA
I2C
SERIAL
INTERFACE
CONTROL
COMMAND
DECODE LOGIC
ADDRESS
DECODE LOGIC
RDAC1
RDAC1
REGISTER
A1
W1
B1
RDAC2
RDAC2
REGISTER
A2
W2
B2
CONTROL LOGIC
RDAC3
RDAC3
REGISTER
AD5253/AD5254
A3
W3
B3
03824-0-001
Figure 1.
Document Feedback
AD5253/AD5254
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
1 k Version.................................................................................. 3
REVISION HISTORY
9/12Rev. B to Rev. C
9/05Rev. 0 to Rev. A
10/09Rev. A to Rev. B
Rev. C | Page 2 of 32
Data Sheet
AD5253/AD5254
ELECTRICAL CHARACTERISTICS
1 k VERSION
VDD = +3 V 10% or +5 V 10%, VSS = 0 V or VDD/VSS = 2.5 V 10%, VA = VDD, VB = 0 V, 40C < TA < +105C, unless otherwise noted.
Table 1.
Parameter
DC CHARACTERISTICS
RHEOSTAT MODE
Resolution
Symbol
Conditions
AD5253
AD5254
RWB, RWA = NC, VDD = 5.5 V, AD5253
RWB, RWA = NC, VDD = 5.5 V, AD5254
RWB, RWA = NC, VDD = 2.7 V, AD5253
RWB, RWA = NC, VDD = 2.7 V, AD5254
RWB, RWA = NC, VDD = 5.5 V, AD5253
RWB, RWA = NC, VDD = 5.5 V, AD5254
RWB, RWA = NC, VDD = 2.7 V, AD5253
RWB, RWA = NC, VDD = 2.7 V, AD5254
TA = 25C
R-DNL
Resistor Nonlinearity2
R-INL
RAB/RAB
(RAB/RAB) 106/T
RW
Channel-Resistance Matching
DC CHARACTERISTICS
POTENTIOMETER DIVIDER MODE
Differential Nonlinearity 3
0.5
1.00
0.75
1.5
0.5
2.0
1.0
2
30
DNL
INL
(VW/VW) 106/T
VWFSE
Zero-Scale Error
VWZSE
VA, VB, VW
CA, CB
Capacitance5 W
CW
ICM
AD5253
AD5254
AD5253
AD5254
Code = half scale
Code = full scale, VDD = 5.5 V, AD5253
Code = full scale, VDD = 5.5 V, AD5254
Code = full scale, VDD = 2.7 V, AD5253
Code = full scale, VDD = 2.7 V, AD5254
Code = zero scale, VDD = 5.5 V, AD5253
Code = zero scale, VDD = 5.5 V, AD5254
Code = zero scale, VDD = 2.7 V, AD5253
Code = zero scale, VDD = 2.7 V, AD5254
Typ 1
0.2
0.25
0.30
0.3
0.2
0.5
+2.5
+9
650
75
200
0.15
IW = 1 V/R, VDD = 5 V
IW = 1 V/R, VDD = 3 V
RAB1/RAB2
Integral Nonlinearity3
RESISTOR TERMINALS
Voltage Range 4
Capacitance 5 A, B
Min
0.5
1.00
0.5
2.0
5
16
6
23
0
0
0
0
0.1
0.25
0.2
0.5
25
3
11
4
16
3
11
4
15
VSS
f = 1 kHz, measured to GND,
code = half scale
f = 1 kHz, measured to GND,
code = half scale
VA = VB = VDD/2
Rev. C | Page 3 of 32
Max
Unit
6
8
+0.5
+1.00
+0.75
+1.5
+0.5
+2.0
+4.0
+14
+30
Bits
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
%
ppm/C
130
300
+0.5
+1.00
+0.5
+2.0
0
0
0
0
5
16
6
20
VDD
LSB
LSB
LSB
LSB
ppm/C
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
85
V
pF
95
pF
0.01
1.00
AD5253/AD5254
Parameter
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Output Logic High (SDA)
Output Logic Low (SDA)
WP Leakage Current
A0 Leakage Current
Input Leakage Current
(Other than WP and A0)
Input Capacitance5
POWER SUPPLIES
Single-Supply Power Range
Dual-Supply Power Range
Positive Supply Current
Negative Supply Current
EEMEM Data Storing Mode Current
EEMEM Data Restoring Mode
Current 6
Power Dissipation 7
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS5, 8
Bandwidth 3 dB
Total Harmonic Distortion
VW Settling Time
Resistor Noise Voltage
Data Sheet
Symbol
Conditions
Min
VIH
VDD = 5 V, VSS = 0 V
VDD/VSS = +2.7 V/0 V or VDD/VSS = 2.5 V
VDD = 5 V, VSS = 0 V
VDD/VSS = +2.7 V/0 V or VDD/VSS = 2.5 V
RPULL-UP = 2.2 k to VDD = 5 V, VSS = 0 V
RPULL-UP = 2.2 k to VDD = 5 V, VSS = 0 V
WP = VDD
A0 = GND
VIN = 0 V or VDD
2.4
2.1
VIL
VOH
VOL
IWP
IA0
II
IDD_STORE
IDD_RESTORE
4.9
0.4
8
3
1
5
VSS = 0 V
BW
THD
tS
eN_WB
RAB = 1 k
VA =1 V rms, VB = 0 V, f = 1 kHz
VA = VDD, VB = 0 V
RWB = 500 , f = 1 kHz
(thermal noise only)
VA = VDD, VB = 0 V, measure VW with
adjacent RDAC making full-scale
change
Signal input at A0 and measure the
output at W1, f = 1 kHz
CT
Analog Coupling
CAT
2.7
2.25
PDISS
PSS
Digital Crosstalk
Max
0.8
0.6
CI
VDD
VDD/VSS
IDD
ISS
Typ 1
5
5
+0.010
+0.02
V
V
V
V
V
V
A
A
A
pF
5.5
2.75
15
15
35
2.5
0.025
0.04
Unit
V
V
A
A
mA
mA
0.075
+0.025
+0.04
mW
%/%
%/%
4
0.05
0.2
3
MHz
%
s
nV/Hz
80
dB
72
dB
Rev. C | Page 4 of 32
Data Sheet
AD5253/AD5254
10 k, 50 k, 100 k VERSIONS
VDD = +3 V 10% or +5 V 10%, VSS = 0 V or VDD/VSS = 2.5 V 10%, VA = VDD, VB = 0 V, 40C < TA < +105C, unless otherwise noted.
Table 2.
Parameter
DC CHARACTERISTICS
RHEOSTAT MODE
Resolution
Resistor Differential Nonlinearity 2
Symbol
Conditions
Min
Typ 1
Max
Unit
N
R-DNL
AD5253/AD5254
RWB, RWA = NC, AD5253
RWB, RWA = NC, AD5254
RWB, RWA = NC, AD5253
RWB, RWA = NC, AD5254
TA = 25C
0.75
1.00
0.75
2.5
20
0.10
0.25
0.25
1.0
6/8
+0.75
+1.00
+0.75
+2.5
+20
Bits
LSB
LSB
LSB
LSB
%
ppm/C
75
200
0.15
0.05
130
300
%
%
Resistor Nonlinearity2
R-INL
RAB/RAB
(RAB/RAB) 106/T
Channel-Resistance Matching
RAB1/RAB2
DC CHARACTERISTICS
POTENTIOMETER DIVIDER MODE
Differential Nonlinearity 3
RW
DNL
Integral Nonlinearity3
INL
Voltage Divider
Temperature Coefficient
Full-Scale Error
(VW/VW) 106/T
Zero-Scale Error
VWZSE
RESISTOR TERMINALS
Voltage Range 4
Capacitance 5 A, B
Capacitance5 W
Common-Mode Leakage Current
DIGITAL INPUTS AND OUTPUTS
Input Logic High
VWFSE
VA, VB, VW
CA, CB
CW
ICM
VIH
VIL
VOH
VOL
IWP
IA0
II
650
IW = 1 V/R, VDD = 5 V
IW = 1 V/R, VDD = 3 V
RAB = 10 k, 50 k
RAB = 100 k
AD5253
AD5254
AD5253
AD5254
Code = half scale
0.5
1.0
0.50
1.5
0.1
0.3
0.15
0.5
15
+0.5
+1.0
+0.50
+1.5
LSB
LSB
LSB
LSB
ppm/C
1.0
3
0
0
0.3
1
0.3
1.2
0
0
1.0
3.0
LSB
LSB
LSB
LSB
VDD
85
V
pF
95
pF
VSS
f = 1 kHz, measured to GND,
code = half scale
f = 1 kHz, measured to GND,
code = half scale
VA = VB = VDD/2
VDD = 5 V, VSS = 0 V
VDD/VSS = +2.7 V/0 V or VDD/VSS = 2.5 V
VDD = 5 V, VSS = 0 V
VDD/VSS = +2.7 V/0 V or VDD/VSS = 2.5 V
RPULL-UP = 2.2 k to VDD = 5 V, VSS = 0 V
RPULL-UP = 2.2 k to VDD = 5 V, VSS = 0 V
WP = VDD
A0 = GND
VIN = 0 V or VDD
CI
0.01
2.4
2.1
0.8
0.6
4.9
0.4
8
3
1
5
Rev. C | Page 5 of 32
A
V
V
V
V
V
V
A
A
A
pF
AD5253/AD5254
Parameter
POWER SUPPLIES
Single-Supply Power Range
Dual-Supply Power Range
Positive Supply Current
Negative Supply Current
EEMEM Data Storing Mode
Current
EEMEM Data Restoring Mode
Current 6
Power Dissipation 7
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS5, 8
3 dB Bandwidth
Total Harmonic Distortion
VW Settling Time
Data Sheet
Typ 1
Max
Unit
5
5
V
V
A
A
IDD_STORE
5.5
2.75
15
15
35
mA
IDD_RESTORE
2.5
mA
PDISS
PSS
BW
THDW
tS
Symbol
Conditions
Min
VDD
VDD/VSS
IDD
ISS
VSS = 0 V
2.7
2.25
eN_WB
Digital Crosstalk
CT
Analog Coupling
CAT
0.005
0.010
+0.002
+0.002
0.075
+0.005
+0.010
mW
%/%
%/%
400/80/40
0.05
1.5/7/14
kHz
%
s
9/20/29
nV/Hz
80
dB
72
dB
Rev. C | Page 6 of 32
Data Sheet
AD5253/AD5254
Symbol
fSCL
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
tEEMEM_STORE
tEEMEM_RESTORE1
tEEMEM_RESTORE2
Conditions
Min
Typ2
Max
Unit
400
kHz
s
s
1.3
0.6
1.3
0.6
0.6
0
100
26
300
s
s
s
s
ns
ns
ns
s
ms
s
300
540
100
K cycles
Years
0.9
300
300
0.6
VDD rise time dependent. Measure without
decoupling capacitors at VDD and VSS.
VDD = 5 V.
tEEMEM_REWRITE
100
Rev. C | Page 7 of 32
AD5253/AD5254
Data Sheet
Rating
0.3 V, +7 V
+0.3 V, 7 V
7V
VSS, VDD
20 mA
5 mA
5 mA
5 mA/500 A/
100 A/50 A
0 V, 7 V
40C to +105C
150C
65C to +150C
300C
215C
220C
143C/W
ESD CAUTION
Rev. C | Page 8 of 32
Data Sheet
AD5253/AD5254
W0 1
B0 2
AD5253/
AD5254
A0 3
19 W3
18 B3
17 A3
TOP VIEW
WP 5 (Not to Scale) 16 AD1
W1 6
15 DGND
B1 7
14 SCL
A1 8
13 W2
SDA 9
12 B2
VSS 10
11 A2
03824-0-002
AD0 4
Mnemonic
W0
B0
A0
AD0
WP
W1
B1
A1
SDA
10
VSS
11
12
13
14
A2
B2
W2
SCL
15
16
17
18
19
20
DGND
AD1
A3
B3
W3
VDD
Description
Wiper Terminal of RDAC0. VSS VW0 VDD.
B Terminal of RDAC0. VSS VB0 VDD.
A Terminal of RDAC0. VSS VA0 VDD.
I2C Device Address 0. AD0 and AD1 allow four AD5253/AD5254 devices to be addressed.
Write Protect, Active Low. VWP VDD + 0.3 V.
Wiper Terminal of RDAC1. VSS VW1 VDD.
B Terminal of RDAC1. VSS VB1 VDD.
A Terminal of RDAC1. VSS VA1 VDD.
Serial Data Input/Output Pin. Shifts in one bit at a time upon positive clock edges. MSB loaded first. Open-drain
MOSFET requires pull-up resistor.
Negative Supply. Connect to 0 V for single supply or 2.7 V for dual supply, where VDD VSS +5.5 V. If VSS is used
rather than grounded in dual supply, VSS must be able to sink 35 mA for 26 ms when storing data to EEMEM.
A Terminal of RDAC2. VSS VA2 VDD.
B Terminal of RDAC2. VSS VB2 VDD.
Wiper Terminal of RDAC2. VSS VW2 VDD.
Serial Input Register Clock Pin. Shifts in one bit at a time upon positive clock edges. VSCL (VDD + 0.3 V). Pull-up
resistor is recommended for SCL to ensure minimum power.
Digital Ground. Connect to system analog ground at a single point.
I2C Device Address 1. AD0 and AD1 allow four AD5253/AD5254 devices to be addressed.
A Terminal of RDAC3. VSS VA3 VDD.
B Terminal of RDAC3. VSS VB3 VDD.
Wiper Terminal of RDAC3. VSS VW3 VDD.
Positive Power Supply Pin. Connect +2.7 V to +5 V for single supply or 2.7 V for dual supply, where VDD VSS +5.5 V.
VDD must be able to source 35 mA for 26 ms when storing data to EEMEM.
Rev. C | Page 9 of 32
AD5253/AD5254
Data Sheet
1.0
0.8
0.8
TA = 40C, +25C, +85C, +125C
0.6
0.4
0.2
0.2
DNL (LSB)
0.4
0.2
0
0.2
0.4
0.4
0.6
0.6
0.8
0.8
1.0
0
32
64
96
128
160
192
224
256
CODE (Decimal)
1.0
0
32
64
128
160
192
224
256
CODE (Decimal)
10
1.0
0.8
0.6
0.4
0.2
IDD (A)
0.2
0.4
0.6
0.8
32
64
96
128
160
192
224
256
CODE (Decimal)
10
40
03824-0-016
1.0
20
20
40
60
80
100
03824-0-019
R-DNL (LSB)
96
03824-0-018
03824-0-015
R-INL (LSB)
0.6
120
TEMPERATURE (C)
1.0
10
0.8
0.6
VDD = 5.5V
0.4
IDD (mA)
0
0.2
0.1
0.01
0.4
VDD = 2.7V
0.6
0.001
1.0
0
32
64
96
128
160
CODE (Decimal)
192
224
256
0.0001
Rev. C | Page 10 of 32
03824-0-020
0.8
03824-0-017
INL (LSB)
0.2
Data Sheet
AD5253/AD5254
240
50
200
DATA = 0x00
VDD = 2.7V
TA = 25C
180
RWB ()
160
140
120
VDD = 5.5V
TA = 25C
100
80
60
40
03824-0-021
20
6
VBIAS (V)
VDD = 5V
TA = 40C TO +85C
VA = VDD
VB = 0V
45
40
35
30
25
20
100k
15
10k
10
50k
5
0
32
64
96
128
160
192
256
0xFF
0x20
18
GAIN (dB)
0x80
0x40
12
2
RWB (%)
224
CODE (Decimal)
03824-0-024
220
0x10
24
30
0x08
36
0x04
0x02
42
0x01
0x00
48
20
40
60
80
100
120
60
TEMPERATURE (C)
10
950
VDD = 5V
TA = 40C TO +85C
VA = VDD
VB = 0V
850
800
100k
700
50k
0x10
30
0x08
36
0x04
42
550
54
96
128
160
192
224
256
CODE (Decimal)
03824-0-023
48
64
0x20
24
600
32
10M
0x40
18
10k
1M
0x80
12
750
650
100k
0xFF
GAIN (dB)
900
10k
1000
RHEOSTAT MODE TEMPCO (ppm/C)
1k
FREQUENCY (Hz)
500
100
0x01
0x00
0x02
60
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Rev. C | Page 11 of 32
03824-0-026
20
03824-0-022
6
40
03824-0-025
54
AD5253/AD5254
Data Sheet
1.2
0xFF
6
12
1.0
0x40
18
0.8
0x20
24
IDD (mA)
0x10
30
0x08
36
0x04
42
VDD = 5.5V
0.6
0.4
0x02
48
0x01
VDD = 2.7V
0.2
54
0x00
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
0
1
10
100
1k
10k
100k
1M
03824-0-030
60
03824-0-027
GAIN (dB)
TA = 25C
0x80
10M
0
0x80
VDD = 5V
0x40
12
0x20
18
GAIN (dB)
CLK
0xFF
0x10
24
0x08
30
VW
0x04
36
0x02
42
DIGITAL FEEDTHROUGH
0x01
MIDSCALE TRANSITION
7FH 80H
48
54
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
400ns/DIV
Figure 16. Gain vs. Frequency vs. Code, RAB = 100 k, TA = 25C
100
VDD = 5.5V
80
100k
60
10k
40
20
RESTORE RDAC0
SETTING TO 0xFF
MIDSCALE
PRESET
1k
RESTORE RDAC3
SETTING TO 0xFF
20
50k
MIDSCALE
PRESET
40
60
100
0
32
64
96
128
160
192
CODE (Decimal)
224
256
Rev. C | Page 12 of 32
VDD
(NO DECOUPLING
CAPS)
VWB0
(0xFF
STORED
IN EEMEM)
VWB3
(0xFF
STORED
IN EEMEM)
03824-0-046
80
03824-0-029
RAB ()
03824-0-031
10
03824-0-028
0x00
60
Data Sheet
AD5253/AD5254
6
RAB = 1k
VA = VB = OPEN
TA = 25C
RAB = 10k
RAB = 50k
RAB = 100k
0
0
16
24
32
RAB = 1k
40
48
CODE (Decimal)
56
64
03824-0-033
VA = VB = OPEN
TA = 25C
RAB = 10k
RAB = 50k
RAB = 100k
0
0
32
64
96
128
160
192
CODE (Decimal)
Rev. C | Page 13 of 32
224
256
03824-0-034
AD5253/AD5254
Data Sheet
I2C INTERFACE
t8
t6
t2
t9
SCL
t4
t3
t2
t8
t7
t10
t5
t9
03824-0-003
SDA
t1
P
SLAVE ADDRESS
(7-BIT)
R/W
INSTRUCTIONS
(8-BIT)
DATA
(8-BIT)
A/A
03824-0-004
DATA TRANSFERRED
(N BYTES + ACKNOWLEDGE)
0 WRITE
SLAVE ADDRESS
(7-BIT)
R/W
DATA
(8-BIT)
DATA
(8-BIT)
03824-0-005
DATA TRANSFERRED
(N BYTES + ACKNOWLEDGE)
1 READ
SLAVE ADDRESS
(7-BIT)
R/W
READ OR WRITE
A/A
DATA
(N BYTES +
ACKNOWLEDGE)
SLAVE ADDRESS
REPEATED START
R/W
READ
OR WRITE
DATA
(N BYTES +
ACKNOWLEDGE)
Rev. C | Page 14 of 32
A/A
P
03824-0-006
Data Sheet
AD5253/AD5254
S = start condition
P = stop condition
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
AD1, AD0 = I2C device address bits, must match with the logic states at Pins AD1, AD0
R/W= read enable bit at logic high; write enable bit at logic low
CMD/REG = command enable bit at logic high; register access bit at logic low
EE/RDAC = EEMEM register at logic high; RDAC register at logic low
A4, A3, A2, A1, A0 = RDAC/EEMEM register addresses
A
D
1
A
D
0
CMD/
REG
SLAVE ADDRESS
EE/
RDAC
A
4
A
3
A
2
A
1
DATA
A/
A
(1 BYTE +
ACKNOWLEDGE)
INSTRUCTIONS
AND ADDRESS
0 WRITE
A
0
03824-0-007
0 REG
A
D
1
A
D
0
CMD/
REG
SLAVE ADDRESS
EE/
RDAC
A
4
A
3
A
2
A
1
A
0
INSTRUCTIONS
AND ADDRESS
0 WRITE
RDAC_N
DATA
RDAC_N + 1
DATA
(N BYTE +
ACKNOWLEDGE)
A/
A
03824-0-008
0 REG
Table 6. Addresses for Writing Data Byte Contents to RDAC Registers (R/W = 0, CMD/REG = 0, EE/RDAC = 0)
A4
0
0
0
0
0
:
:
0
A3
0
0
0
0
0
:
:
1
A2
0
0
0
0
1
:
:
1
A1
0
0
1
1
0
:
:
1
A0
0
1
0
1
0
:
:
1
RDAC
RDAC0
RDAC1
RDAC2
RDAC3
Reserved
:
:
Reserved
Rev. C | Page 15 of 32
AD5253/AD5254
Data Sheet
RDAC/EEMEM Write
Setting the wiper position requires an RDAC write operation.
The single write operation is shown in Figure 27, and the
consecutive write operation is shown in Figure 28. In the
consecutive write operation, if the RDAC is selected and the
address starts at 0, the first data byte goes to RDAC0, the second
data byte goes to RDAC1, the third data byte goes to RDAC2,
and the fourth data byte goes to RDAC3. This operation can be
continued for up to eight addresses with four unused addresses;
it then loops back to RDAC0. If the address starts at any of the
eight valid addresses, N, the data first goes to RDAC_N,
RDAC_N + 1, and so on; it loops back to RDAC0 after the
eighth address. The RDAC address is shown in Table 6.
RDAC/EEMEM Read
The AD5253/AD5254 provide two different RDAC or EEMEM
read operations. For example, Figure 29 shows the method of
reading the RDAC0 to RDAC3 contents without specifying the
address, assuming Address RDAC0 was already selected in the
previous operation. If an RDAC_N address other than RDAC0
was previously selected, readback starts with Address N,
followed by N + 1, and so on.
Figure 30 illustrates a random RDAC or EEMEM read
operation. This operation allows users to specify which RDAC
or EEMEM register is read by issuing a dummy write command
to change the RDAC address pointer and then proceeding with
the RDAC read operation at the new address location.
A4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Users can store any of the 64 RDAC settings for AD5253 or any of the 256
RDAC settings for the AD5254 directly to the EEMEM. This is not limited to
current RDAC wiper setting.
Rev. C | Page 16 of 32
Data Sheet
AD5253/AD5254
S = start condition
P = stop condition
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
AD1, AD0 = I2C device address bits, must match with the logic states at Pins AD1, AD0
R/W = read enable bit at logic high; write enable bit at logic low
CMD/REG = command enable bit at logic high; register access bit at logic low
C3, C2, C1, C0 = command bits
A2, A1, A0 = RDAC/EEMEM register addresses
A
D
1
A
D
0
RDAC_N OR EEMEM_N
REGISTER DATA
SLAVE ADDRESS
RDAC_N + 1 OR EEMEM_N + 1
REGISTER DATA
03824-0-009
(N BYTES + ACKNOWLEDGE)
1 READ
Figure 29. RDAC Current Read (Restricted to Previously Selected Address Stored in the Register)
INSTRUCTIONAL AND
ADDRESS
SLAVE ADDRESS
RDAC OR
EEMEM DATA
A/A
(N BYTES + ACKNOWLEDGE)
0 WRITE
REPEATED START
1 READ
A
D
1
A
D
0
CMD/
REG
C
3
C
2
C
1
C
0
A
2
A
1
1 CMD
Rev. C | Page 17 of 32
A
0
03824-0-010
SLAVE ADDRESS
03824-0-011
AD5253/AD5254
Data Sheet
Table 9. RDAC-to-EEMEM Interface and RDAC Operation Quick Command Bits (CMD/REG = 1, A2 = 0)
C3
0
0
0
0
0
0
0
0
1
1
1
1
1
:
:
1
1
C2
0
0
0
0
1
1
1
1
0
0
0
0
1
:
:
1
C1
0
0
1
1
0
0
1
1
0
0
1
1
0
:
:
1
C0
0
1
0
1
0
1
0
1
0
1
0
1
0
:
:
1
Command Description
NOP
Restore EEMEM (A1, A0) to RDAC (A1, A0) 1
Store RDAC (A1, A0) to EEMEM (A1, A0)
Decrement RDAC (A1, A0) 6 dB
Decrement all RDACs 6 dB
Decrement RDAC (A1, A0) one step
Decrement all RDACs one step
Reset: restore EEMEMs to all RDACs
Increment RDACs (A1, A0) 6 dB
Increment all RDACs 6 dB
Increment RDACs (A1, A0) one step
Increment all RDACs one step
Reserved
:
:
Reserved
This command leaves the device in the EEMEM read power state, which consumes power. Issue the NOP command to return the device to its idle state.
Rev. C | Page 18 of 32
Data Sheet
AD5253/AD5254
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
D7
D6
D5
D4
D3
D2
D1
D0
SIGN
26
25
24
23
22
21
20
SIGN
D7
D6
D5
D4
D3
D2
D1
D0
21
22
23
24
25
26
27
28
03824-0-012
A4
1
1
1
1
1
1
1
1
Figure 32. Format of Stored Tolerance in Sign Magnitude Format with Bit Position Descriptions (Unit is Percent, Only Data Bytes Are Shown)
Rev. C | Page 19 of 32
AD5253/AD5254
Data Sheet
SDA
START BY
MASTER
X
1 AD1 AD0 R/W
ACK. BY
AD525x
X
D7 D6
ACK. BY
AD525x
D5
D3
D2
D1
D0
ACK. BY
AD525x
STOP BY
MASTER
FRAME 1
DATA BYTE
FRAME 2
INSTRUCTION BYTE
FRAME 1
SLAVE ADDRESS BYTE
D4
03824-0-013
SCL
SCL
0
D7
D6
D5
D4
D3
D2
ACK. BY
AD525x
START BY
MASTER
D1
D0
NO ACK. BY
MASTER
FRAME1
SLAVE ADDRESS BYTE
FRAME 2
RDAC REGISTER
STOP BY
MASTER
03824-0-014
SDA
2.
3.
4.
Data Sheet
AD5253/AD5254
THEORY OF OPERATION
The AD5253/AD5254 are quad-channel digital potentiometers
in 1 k, 10 k, 50 k, or 100 k that allow 64/256 linear resistance step adjustments. The AD5253/AD5254 employ doublegate CMOS EEPROM technology, which allows resistance
settings and user-defined data to be stored in the EEMEM
registers. The EEMEM is nonvolatile, such that settings remain
when power is removed. The RDAC wiper settings are restored
from the nonvolatile memory settings during device power-up
and can also be restored at any time during operation.
The AD5253/AD5254 resistor wiper positions are determined
by the RDAC register contents. The RDAC register acts like a
scratch-pad register, allowing unlimited changes of resistance
settings. RDAC register contents can be changed using the
devices serial I2C interface. The format of the data-words and
the commands to program the RDAC registers are discussed in
the I2C Interface section.
The four RDAC registers have corresponding EEMEM memory
locations that provide nonvolatile storage of resistor wiper
position settings. The AD5253/AD5254 provide commands to
store the RDAC register contents to their respective EEMEM
memory locations. During subsequent power-on sequences, the
RDAC registers are automatically loaded with the stored value.
Whenever the EEMEM write operation is enabled, the device
activates the internal charge pump and raises the EEMEM cell
gate bias voltage to a high level; this essentially erases the
current content in the EEMEM register and allows subsequent
storage of the new content. Saving data to an EEMEM register
consumes about 35 mA of current and lasts approximately
26 ms. Because of charge-pump operation, all RDAC channels
may experience noise coupling during the EEMEM writing
operation.
The EEMEM restore time in power-up or during operation is
about 300 s. Note that the power-up EEMEM refresh time
depends on how fast VDD reaches its final value. As a result, any
supply voltage decoupling capacitors limit the EEMEM restore
time during power-up. For example, Figure 20 shows the
power-up profile of the VDD where there is no decoupling
capacitors and the applied power is a digital signal. The device
initially resets the RDACs to midscale before restoring the
EEMEM contents. The omission of the decoupling capacitors
should only be considered when the fast restoring time is
absolutely needed in the application. In addition, users should
issue a NOP Command 0 immediately after using Command 1
to restore the EEMEM setting to RDAC, thereby minimizing
supply current dissipation. Reading user data directly from
EEMEM does not require a similar NOP command execution.
Description
NOP.
Restore EEMEM content to RDAC. User should
issue NOP immediately after this command to
conserve power.
Store RDAC register setting to EEMEM.
Decrement RDAC 6 dB (shift data bits right).
Decrement all RDACs 6 dB (shift all data bits right).
Decrement RDAC one step.
Decrement all RDACs one step.
Reset EEMEM contents to all RDACs.
Increment RDAC 6 dB (shift data bits left).
Increment all RDACs 6 dB (shift all data bits left).
Increment RDAC one step.
Increment all RDACs one step.
Reserved.
6 dB ADJUSTMENTS
(DOUBLING/HALVING WIPER SETTING)
The AD5253/AD5254 accommodate 6 dB adjustments of the
RDAC wiper positions by shifting the register contents to left/
right for increment/decrement operations, respectively. Command 3, Command 4, Command 8, and Command 9 can be
used to increment or decrement the wiper positions in 6 dB
steps synchronously or asynchronously.
Incrementing the wiper position by +6 dB essentially doubles
the RDAC register value, whereas decrementing the wiper
position by 6 dB halves the register content. Internally, the
AD5253/AD5254 use shift registers to shift the bits left and
right to achieve a 6 dB increment or decrement. The
maximum number of adjustments is nine and eight steps for
incrementing from zero scale and decrementing from full scale,
respectively. These functions are useful for various audio/video
level adjustments, especially for white LED brightness settings
in which human visual responses are more sensitive to large
adjustments than to small adjustments.
AD5253/AD5254
Data Sheet
AD0
0
1
0
1
Device Addressed
U1
U2
U3
U4
5V
RP
RP
SDA
VDD
MASTER
SCL
SDA
SCL
AD1
SCL
AD0
03824-0-035
AD5253/
AD5254
VDD
INPUTS
03824-0-036
WP
GND
SDA
SCL
AD1
AD0
AD5253/
AD5254
5V
SDA
SCL
AD1
AD0
AD5253/
AD5254
SDA
SCL
AD1
AD0
AD5253/
AD5254
GND
5V
03824-0-037
5V
Rev. C | Page 22 of 32
Data Sheet
AD5253/AD5254
VDD
+5V
4
R1
24
DECODER
N1
AD1
AD0
W
B
R2X
VSS
AD1
24
DECODER
03824-0-039
+5V
N2X
+5
AD0
P2Y
+5V
4
P3X
AD1
R3X
R3Y
AD0
N3Y
24
DECODER
+5V
4
P4
AD1
AD0
03824-0-038
R4
AD5253/AD5254
VDD
C3
10F
C4
VSS
VDD
C1
0.1F
C2
10F
0.1F
VSS
GND
03824-0-040
24
DECODER
Rev. C | Page 23 of 32
AD5253/AD5254
Data Sheet
AX
SW (2N 1)
RDAC
WIPER
REGISTER
AND
DECODER
W
B
SW(0)
BX
03824-0-041
SWB
03824-0-042
W
B
/2N
DIGITAL
CIRCUITRY
OMIITTED FOR
CLARITY
(1)
(2)
where:
D is the decimal equivalent of the data contained in the
RDAC latch.
RAB is the nominal end-to-end resistance.
SW(1)
RS = RAB
W
B
SW (2N 2)
RS
RS
WX
RS
Rev. C | Page 24 of 32
Data Sheet
AD5253/AD5254
PROGRAMMABLE POTENTIOMETER OPERATION
100
RWA
If all three terminals are used, the operation is called potentiometer mode (see Figure 44); the most common configuration
is the voltage divider operation.
RWB
VI
50
VC
W
B
25
03824-0-044
RAB (%)
75
0
0
10
32
48
63
D (Code in Decimal)
03824-0-043
D
V AB + V B
64
(5)
AD5254: VW =
D
V AB + V B
256
(6)
(3)
(4)
D
R AB + RW
N
VW (D) = 2
VA
R AB + 2RW
(7)
Rev. C | Page 25 of 32
AD5253/AD5254
Data Sheet
APPLICATIONS INFORMATION
RGB LED BACKLIGHT CONTROLLER
FOR LCD PANELS
Because high power (>1 W) RGB LEDs offer superior color
quality compared with cold cathode florescent lamps (CCFLs)
as backlighting sources, it is likely that high-end LCD panels
will employ RGB LEDs as backlight in the near future. Unlike
conventional LEDs, high power LEDs have a forward voltage of
2 V to 4 V and consume more than 350 mA at maximum
brightness. The LED brightness is a linear function of the
conduction current, but not of the forward voltage. To increase
the brightness of a given color, multiple LEDs can be connected
in series, rather than in parallel, to achieve uniform brightness.
For example, three red LEDs configured in series require an
average of 6 V to 12 V headroom, but the circuit operation
requires current control. As a result, Figure 45 shows the
implementation of one high power RGB LED controller using a
AD5254, a boost regulator, an op amp, and power MOSFETs.
IR =
V RR
RR
Rev. C | Page 26 of 32
(8)
Data Sheet
AD5253/AD5254
+5V
C10
10F
U1
U2
R1
R5
VDD
R6
C1
0.1F
R7
RDAC3
22k 22k
SCL
SDA
U3D
10k
B3
CLK
SDI
RC
VREF = 2.5V
AD8594
R4
10k 10k
A3
R3
R2
100k
CC
AD5254
390F
IN
10F
L1
ADP1610
D1
SW
FB
SD
COMP
SS RT GND
10F
+5V
CSS 10F
DB1
DG1
DR1
DB2
DG2
DR2
DB3
DG3
DR3
C11
8
A2
W2
RDAC2
VOUT
C3
VB
0.1F
IB
N3
U3C
V+
AD8594
V
4
10k B2
R10
4.7
IRFL3103
IG
VRB
VG
A1
U3B
W1
RDAC1
RB
0.1
N2
R9
10k B1
AD8594
IRFL3103
4.7
A0
RDAC0
RG
W0
VRG
0.1
VR
N1
R8
10k B0
AD8594
4.7
IRFL3103
SD
Rev. C | Page 27 of 32
0.1
03824-0-045
L1 - SLF6025-100M1R0
D1 - MBR0520LT1
U3A
IR
AD5253/AD5254
Data Sheet
OUTLINE DIMENSIONS
6.60
6.50
6.40
20
11
4.50
4.40
4.30
6.40 BSC
1
10
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
COPLANARITY
0.10
0.30
0.19
0.20
0.09
SEATING
PLANE
8
0
Rev. C | Page 28 of 32
0.75
0.60
0.45
Data Sheet
AD5253/AD5254
ORDERING GUIDE
Model 1, 2, 3
AD5253BRU1
AD5253BRU1-RL7
AD5253BRUZ1
AD5253BRUZ1-RL7
AD5253BRU10
AD5253BRU10-RL7
AD5253BRUZ10
AD5253BRUZ10-RL7
AD5253BRU50
AD5253BRU50-RL7
AD5253BRUZ50
AD5253BRUZ50-RL7
AD5253BRU100
AD5253BRU100-RL7
AD5253BRUZ100
AD5253BRUZ100-RL7
AD5254BRU1
AD5254BRU1-RL7
AD5254BRUZ1
AD5254BRUZ1-RL7
AD5254BRU10
AD5254BRU10-RL7
AD5254BRUZ10
AD5254BRUZ10-RL7
AD5254BRU50
AD5254BRU50-RL7
AD5254BRUZ50
AD5254BRUZ50-RL7
AD5254BRU100
AD5254BRU100-RL7
AD5254BRUZ100
AD5254BRUZ100-RL7
EVAL-AD5254SDZ
Step
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
RAB (k)
1
1
1
1
10
10
10
10
50
50
50
50
100
100
100
100
1
1
1
1
10
10
10
10
50
50
50
50
100
100
100
100
Temperature Range
40C to +105C
40C to +105C
40C to +105C
40C to +105C
40C to +105C
40C to +105C
40C to +105C
40C to +105C
40C to +105C
40C to +105C
40C to +105C
40C to +105C
40C to +105C
40C to +105C
40C to +105C
40C to +105C
40C to +105C
40C to +105C
40C to +105C
40C to +105C
40C to +105C
40C to +105C
40C to +105C
40C to +105C
40C to +105C
40C to +105C
40C to +105C
40C to +105C
40C to +105C
40C to +105C
40C to +105C
40C to +105C
Package Description
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
Evaluation Board
Package
Option
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
Ordering
Quantity
75
1,000
75
1,000
75
1,000
75
1,000
75
1,000
75
1,000
75
1,000
75
1,000
75
1,000
75
1,000
75
1,000
75
1,000
75
1,000
75
1,000
75
1,000
75
1,000
1
In the package marking, Line 1 shows the part number. Line 2 shows the branding information, such that B1 = 1 k, B10 = 10 k, and so on. There is also a # marking
for the Pb-free part. Line 3 shows the date code in YYWW.
Z = RoHS Compliant Part.
3
The evaluation board is shipped with the 10 k RAB resistor option; however, the board is compatible with all available resistor value options.
2
Rev. C | Page 29 of 32
AD5253/AD5254
Data Sheet
NOTES
Rev. C | Page 30 of 32
Data Sheet
AD5253/AD5254
NOTES
Rev. C | Page 31 of 32
AD5253/AD5254
Data Sheet
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
Rev. C | Page 32 of 32