Microprocessor and Interfaces

MicroprocessorandInterfaces
MaximumMode

Maximum Mode Interface

MaximumModeInterface
When the8086isset forthe maximummode
configuration,itprovidessignalsforimplementinga
multiprocessor/coprocessorsystem environment
By multiprocessor environmentwemeanthatmorethan
onemicroprocessorexistsinthesystemandthateach
processorisexecutingitsownprogram
Usuallyinthistypeofsystemenvironment,there aresome
systemresourcesthatare commontoallprocessors
They are called asglobalresources.Therearealsoother
resourcesthatareassignedto
g
specificprocessors.These
p
p
areknownaslocalorprivateresources

Maximum Mode Interface

MaximumModeInterface
Coprocessor
Cop ocesso aalsomeansthat
so ea s t at tthere
e e iss aa
second processor inthesystem.Inthistwo
processordoesnotaccessthebusatthesame
time
Onepassesthecontrolofthesystembustothe
otherandthenmaysuspenditsoperation
th
d th
d it
ti
In the maximummode 8086 system,facilities
are providedforimplementingallocationof
provided for implementing allocation of
globalresourcesandpassingbuscontrolto other
microprocessororcoprocessor
p
p

8086 Maximum mode Block Diagram

8086MaximummodeBlockDiagram

8288 Bus Controller

8288BusController
8086doesnotdirectlyprovideallthesignalsthatare
requiredtocontrolthememory,I/Oandinterrupt
interfaces
the WR bar, M/IO_bar,DT/R_bar,DEN_bar,
M/IO bar, DT/R bar, DEN bar,
Specially theWR_bar,
ALEand INTA_bar signalsarenolongerproducedby
the8086.InsteaditoutputsthreestatussignalsS0_bar,
S1 bar, S2 bar prior to the initiation of each bus cycle.
S1_bar,S2_barpriortotheinitiationofeachbuscycle.
This3bitbusstatuscodeidentifieswhichtypeofbus
cycleisto follow
S2_barS1_barS0_barareinputtotheexternalbus
S2 bar S1 bar S0 bar are input to the external bus
controllerdevice,thebuscontrollergenerates
the appropriatelytimedcommandandcontrolsignals

Bus Status Codes

BusStatusCodes

8288 Bus Controller

8288BusController
The8288 produces oneortwooftheseeight
commandsignals foreachbuscycles.Forinstance,when
the8086outputsthecodeS2_barS1_barS0_barequals
001,itindicatesthatan I/O readcycleistobeperformed
In the code 111 isoutputbythe8086,it issignalingthatno
busactivityistotakeplace
Thecontroloutputsproducedbythe8288areDEN,
DT/RandALE.These3signalsprovidethesamefunctionsas
thosedescribedfortheminimumsystemmode.Thisset
of buscommandsandcontrolsignalsiscompatiblewiththe
M ltib andindustrystandardfor
Multibus
d i d t t d d f interfacing
i t f i
microprocessorsystems

8289 Bus Arbiter

8289BusArbiter
Thisdevicepermitsprocessorstoresideonthe
p
p
systembus.Itdoesthisbyimplementingthe
Multibus arbitrationprotocolinan8086based
system
Additionofthe8288buscontrollerand8289bus
arbiterfreesanumberofthe8086pinsfor useto
producecontrolsignalsthatare neededto
supportmultipleprocessors
Buspriority
Bus priority lock (LOCK_bar)is
( LOCK bar) is oneofthese
one of these
signals.Itisinputtothebusarbitertogether
with statussignalsS0_barthroughS2_bar

8289 Bus Arbiter

8289BusArbiter
Theoutputof8289arebusarbitrationsignals:
p
f
g
busbusy(BUSY),commonbusrequest(CBRQ),bus
priorityout(BPRO),buspriorityin(BPRN),bus
request(BREQ) and bus clock(BCLK)
request(BREQ)andbusclock(BCLK)
They correspond to thebus exchange signalsof
theMultibus andareusedtolockother
processoroffthesystembusduringtheexecution
ofaninstructionbythe8086
In thisway
this way the processor can be assuredof
assured of
uninterruptedaccesstocommonsystem
resourcessuchas global memory

Queue Status Signals

QueueStatusSignals
Two
Twonewsignalsthatare
new signals that are producedbythe
produced by the
8086inthemaximummodesystemarequeue
status outputs QS0 and QS1
statusoutputsQS0andQS1

Local Bus Control Signal

LocalBusControlSignal
Request
Request/GrantSignals:Inamaximummode
/ Grant Signals: In a maximum mode
configuration, theminimummodeHOLD,
HLDA interface is also changed These two are
HLDAinterfaceisalsochanged.Thesetwo
are
replacedbyrequest/grantlines
RQ0 bar/GT0 bar and RQ1 bar/GT1 bar
RQ0_bar/GT0_barandRQ1_bar/GT1_bar,
respectively.Theyprovideaprioritizedbus
access mechanism for accessing the local bus
accessmechanismforaccessingthelocalbus

MAXIMUM MODE OPERATION

MAXIMUMMODEOPERATION

Maximum Mode 8086 System

MaximumMode8086System
Inthemaximummode,the8086isoperated
t e a u
ode, t e 8086 s ope ated
by strappingtheMN/MX_bar pintoground
p
Inthismode,theprocessorderivesthestatus
signalS2,S1,S0.Anotherchipcalled
bus controllerderivesthecontrolsignalusingthis
statusinformation
t t i f
ti
In themaximum mode,theremaybemorethan
one microprocessor in the system configuration
onemicroprocessorinthesystemconfiguration
Thecomponentsinthesystemaresameas inthe
minimum mode system
minimummodesystem

Maximum Mode 8086 System

MaximumMode8086System
The basic function of the bus controllerchip IC8288,
is toderivecontrolsignalslikeRDandWR( for
memoryandI/Odevices),DEN_bar,DT/R_bar,ALE etc.
usingtheinformationbytheprocessoronthestatus
g
y
p
lines
Thebus controller chip hasinput linesS2_bar,S1_bar,
S0 bar and CLK. These inputs to 8288 are driven by
S0_barandCLK.Theseinputsto8288aredrivenby
CPU
It derivesthe outputsALE,DEN_bar,DT/R_bar,
MRDC bar MWTC bar AMWC bar IORC bar
MRDC_bar,MWTC_bar,AMWC_bar,IORC_bar,
IOWC_bar andAIOWC_bar.TheAEN_bar,IOBandCEN
pinsarespeciallyusefulformultiprocessorsystems

Maximum Mode 8086 System

MaximumMode8086System
AENandIOB_bar aregenerallygrounded.CEN
g
yg
pinis usuallytiedto+5V.Thesignificanceof
the MCE/PDEN_bar outputdependsuponthe
status of the IOB pin
statusoftheIOBpin
IfIOBisgrounded,itactsasmastercascade
enabletocontrolcascade8259A,elseitactsas
peripheraldataenableusedinthe multiplebus
configurations
INTA_bar
INTA bar pinusedtoissuetwointerrupt
pin used to issue two interrupt
acknowledgepulsestotheinterruptcontrolleror
toaninterruptingdevice

Maximum Mode 8086 System

MaximumMode8086System
IORC_bar,IOWC_bar are I/O read command andI/Owrite
commandsignalsrespectively.Thesesignalsenablean IO
interfacetoreadorwritethe datafromortotheaddress
port
TheMRDC_bar,MWTC_bar arememoryreadcommand
andmemory writecommand signals respectively andmay
beusedasmemoryreadorwritesignals
Allthesecommandsignalsinstructsthememoryto
acceptorsenddatafromortothebus
Forbothofthesewritecommandsignals,theadvanced
g
signalsnamelyAIOWC_bar andAMWTC_bar areavailable

Maximum Mode 8086 System

MaximumMode8086System
Theyy alsoserve thesamepurpose,butareactivated
p p ,
oneclockcycleearlierthantheIOWC_bar and
MWTC_bar signalsrespectively
Themaximummodesystemtiming
Th
i
d
t
ti i diagramsare
di
dividedintwoportionsasread(input)andwrite
( p )
(output)timingdiagrams
g g
The address/data andaddress/statustimingsare
similartotheminimummode
ALE is asserted in T1,justlikeminimummode.Theonly
differenceliesinthestatussignalusedandthe
available control and advanced command signals
availablecontrolandadvancedcommandsignals

MemoryReadTiminginMaximum
Mode
d

MemoryWriteTiminginMaximum
mode
d

Timing Diagram
TimingDiagram
The only differencein
difference in timing diagram
diagram
betweenminimummodeandmaximummode
is the statussignalsusedandthe
isthe
status signals used and the available
available
controlandadvancedcommandsignals
S0_bar,S1_bar,S2_bararesetatthe
S0 bar S1 bar S2 bar are set at the
beginningofbuscycle.8288buscontroller
will output a pulse as on the ALEandapplya
willoutputapulseasonthe
ALE and apply a
requiredsignaltoitsDT/RpinduringT1

Timing Diagram
TimingDiagram
In T2,8288willsetDEN=1
, 8 88
set
tthusenabling
us e ab g
transceivers,andforaninputitwillactivate
MRDCorIORC.Thesesignalsareactivateduntil
T4.Foranoutput,theAMWCorAIOWCis
h
activatedfromT2toT4andMWTCorIOWCis
activated from T3 to T4
activatedfromT3toT4
The status bit S0toS2remainsactiveuntilT3and
become passive during T3 and T4
becomepassiveduringT3andT4
If reader inputisnot activatedbeforeT3,wait
statewillbeinsertedbetweenT3andT4

Timings for RQ bar/GT bar Signals

TimingsforRQ_bar/GT_bar
Therequest/grantresponsesequencecontainsa
q
/g
p
q
seriesofthreepulses.Therequest/grantpinsare
checkedateachrisingpulseofclock input
Whena
When a requestisdetectedandifthecondition
request is detected and if the condition
forHOLDrequestaresatisfied,theprocessor
issuesagrantpulseovertheRQ_bar/GT_bar pin
immediatelyduringT4(current)orT1(next)state
Whenthe requestingmaster receives this
pulse itacceptsthecontrolofthebus,it
pulse,
it accepts the control of the bus it sendsa
sends a
releasepulsetotheprocessorusing
RQ_bar/GT_bar pin

RQ_bar/GT_bar TimingsinMaximum
Mode
d