Daisy Henderson

Mechatronics Lab 6:
Logic Gates and Digital Circuits

Introduction:
The purpose of the lab was to become familiar with basic positive/negative
logic and threshold voltage. Also, it was discovered how to test the behavior of
these gates and connect them together to create a simple circuit.
A logic gate is a building block of a digital circuit, and the majority of logic
gates contain two inputs and one output. Depending on voltage level, the gate is
either in a low condition or a high condition. There are multiple types of logic
gates, and the ones being used in this lab are inverters, AND, OR, XOR, NAND,
and NOR gates.
The inverter gate is the only gate used in the experiment that only has one
input. If the input of this gate is true, the output is false; and if the input of the
gate is false, the output of the gate is true. An AND gate behaves in such a way,
that when both inputs are true, the output is true; but if either input is false, the
output is false. An OR gate's output is true if either input is true, or if both the
inputs are true. A XOR gate is similar to an OR gate in that if either of the inputs
are true, the output will be true, but if both inputs are true the output will be false.
A NAND gate output is true if neither of the inputs are true, or if one of the inputs
is true. Otherwise, if both inputs are true, the output will be false. A NOR gate's
output is only true if both inputs are false, otherwise the output is false.
Procedures:
In the first section of the lab, an inverter gate was connected to a
breadboard, and the ground and power source pins were identified. A hand held
multi-meter's positive lead was then connected to one of the gate outputs of the
inverter and the black lead was connected to the ground pin of the gate. A power
supply of 5 volts was then connected to the circuit and a wire was attached from
the voltage supply pin to the input. The results were recorded, then the wire was
removed and reconnected to the ground pin to the input of a gate and the results
were recorded.
For the second section, a voltage threshold was created for the above
circuit. Another variable power supply was added to the circuit, and the multimeter was connected between the ground and the input of one of the gates. The
voltage was varied between 0V and 5V, and the results were recorded and
graphed.
The third portion of the lab used a NAND, AND, NOR, OR, and XOR gate. The
circuit from the previous sections was removed from the breadboard and one of
the logic gates was attached in a similar fashion. The gate was then connected to
the power supply and each combination of inputs was tested; low input-low input,
low input-high input, high input-low input, and high input-high input. This was
repeated for each gate and the results were observed and recorded.
The circuit was then disassembled, and a circuit containing 4 logic gates was
created using a breadboard. The resulting circuit was then connected to the
power supply, and the logic behaviors between the three inputs were tested and
recorded.
The final segment of the lab was used to introduce clock signal and delay.
An odd number of inverter gates were connected on a breadboard in series, and
the last gate output was connected to the first gate input. The circuit was then
connected to the oscilloscope and a power supply and the frequency was
measured and the delay of each gate was calculated.
Results:

Input to the Inverter

Output(V)
L
5V
H
0V
Table A: Values for inverter gate.
Input A
Input B
AND (V) AND
(H/L)
L
L
.13V
L
L
H
.130V
L
H
L
.13 V
L
H
H
4.26
H
Input A
Input B
NOR (V)
L
L
4.6 V
L
H
0V
H
L
0V
H
H
0V
Table B: The two above tables show the
5 types of logic gates tested in the lab.
Input A
0
0
0
0
1
1
1
1
Table C: Shows
gates.

Input B
0
0
1
1
0
0
1
1
the values of the

H/L
H
L
OR (V)
.083V
4.5 V
4.5 V
4.5 V

OR (H/L) NAND
(V)
L
4.5 V
H
4.5 V
H
4.5 V
H
.165 V

NOR (H/L)
H
L
L
L
tested inputs

XOR (V)
.764 V
4.5 V
4.5 V
.173 V
and the found

NAND
H/L
H
H
H
L
XOR (H/L)
L
H
H
L
outputs of the

Input C
Output (V)
Output (H/L)
0
.147 V
L
1
.148 V
L
0
4.018 V
H
1
.142 V
L
0
.147 V
L
1
.144 V
L
0
.147 V
L
1
.143 V
L
outputs from the circuit built with multiple logic

Frequency
Period
Delay
16.92 MHz
59.10 ns
5.910 ns
Table D: Values found from the clock signal experiment.
Conclusion:
The first part of the experiment found a truth table for an inverter gate. It
was found that if the input was 0 (false), the output would be 1 (true). In the
second section of the lab the threshold was found to be at from 0 -1 volts, where
the logic value was 1, and at 1.5 volts and above the logic value was zero.
When using the various types of logic gates, it was found that each type
(AND, OR, etc.) had their own specific requirements for what was considered to be
true or false. It was also found that the names of these gates, such as AND, were
chosen logically. In the case of an AND gate, the gate output only reads true when
both input A and input B are true. This was found for all of the gates and can be
seen in table B.
The circuit built with multiple gates was found to have only 1 combination of
inputs that would result in a true output. This was when both the A and C input

were set to 0, and the B input was set to 1. The other combinations resulted in a
false, or 0, reading.
Finally, for the last segment, a clock signal was built. It was found that the
delay was the period divided by 2 microseconds, so the delay was 5.91 ns.