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Floating lossless immittance functions

using DVCCTA
a

R. Nandi , Sagarika Das & P. Venkateswaran

a

Department of Electronics & Tele-Communication Engineering,

Jadavpur University, Kolkata, 700032, India
b

Department of Electronics Engineering, B.P. Poddar Institute of

Management & Technology, Kolkata, 700052, India
Accepted author version posted online: 30 Sep 2014.Published
online: 29 Oct 2014.

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To cite this article: R. Nandi, Sagarika Das & P. Venkateswaran (2014): Floating lossless
immittance functions using DVCCTA, International Journal of Electronics Letters, DOI:
10.1080/21681724.2014.966772
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International Journal of Electronics Letters, 2014

http://dx.doi.org/10.1080/21681724.2014.966772

Floating lossless immittance functions using DVCCTA

Downloaded by [Central Electronics Engineering Research Institute] at 01:35 19 February 2015

R. Nandia*, Sagarika Dasb and P. Venkateswarana

a

Department of Electronics & Tele-Communication Engineering, Jadavpur University, Kolkata,

700032, India; bDepartment of Electronics Engineering, B.P. Poddar Institute of Management
& Technology, Kolkata, 700052, India
(Received 4 October 2013; accepted 31 March 2014)
A new circuit realisation scheme for the simulation of floating lossless immittance
function (FLIF) using differential voltage current conveyor transimmittance amplifier
is proposed; intuitive choice of the device transadmittance (Ym) would yield either a
floating inductor (if Ym gm) or a floating FDNR-type supercapacitor (if Ym sCm) in
the same topology. Analysis indicates that device nonidealities have insignificant
effects on the nominal design. Experimental results for some selective filter
(5 Q 10) design using the FLIFs are presented.
Keywords: floating immittance; FDNR; active filter; synthetic inductor

1. Introduction
Recently, considerable work on the topic of synthetic floating immittance function
simulation had been reported in the literature using various types of active building
blocks, e.g., voltage operational amplifier (Senani, 1989), current conveyor (Nandi,
Jana, & Nandi, 1984; Senani, 1984), current backward transconductance amplifier
(Ayten, Sagbas, Herencsar, & Koton, 2012), differential voltage controlled current source
(Nandi, 1981; Patranabis & Paul, 1979) and current feedback amplifier (CFA) (Liu &
Hwang, 1994). Synthetic floating immittances are useful for the design of active ladder
filters, phase shifters and oscillators (Bruton, 1980; Senani, 1984). The differential voltage
current conveyor transimmittance amplifier (DVCCTA) is a relatively new device that had
been primarily configured as a transconductance element (gm) in its basic architecture for
such applications (Tangsrirat, 2013). Here, we propose that the building block may be
insightfully configured in either transconductance (gm) or as transcapacitive (Cm) mode so
as to yield some new variants of the synthetic immittances. The AD-844 type readily
available CFA device (Analog Devices, 1990; Tammam, Hyatleh, Ben-Esmael,
Terzopoulos, & Sebu, 2013) is considered quite amenable for the implementation of the
DVCCTA building block, since the CFA itself is a differential input current conveyor that
only needs an added output stage wherein the desired transimmittance is to be embedded.
The CFA has superior terminal properties, viz., accurate port transfer ratio (Hyeong-Woo,
Ogawa, & Watanabe, 1998), enhanced bandwidth and slew rate capability (Gift &
Maundy, 2005); hence, we implemented the CFA-based DVCCTA so as to take advantage
of these characteristics in our work, keeping in view that a pair of terminal may be
brought out of the chip suitably for external connection of the desired gm or Cm for
possible microminiaturisation of the complete simulation scheme; we believe such a
*Corresponding author. Email: robsilverju@yahoo.co.in
2014 Taylor & Francis

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R. Nandi et al.

circuit architectural attribute offers versatility to the building block for newer future
applications.
Albeit the terminology DVCCTA had been used in the literature (Jantakun,
Pisutthipong, & Siripruchyanun, 2009) for differential voltage current conveyor transconductance amplifier, it is essentially a special hybrid form of the current conveyor coupled
with a transconductance amplifier (gm) stage. With an extended conceptual idea, we
considered a more generic form of the device that may be configured by a voltagecontrolled current source (VCIS) at the output stage wherein the controlling parameter
could be an immittance (Ym), i.e., not only a conductance (gm), it may also be capacitive
(Cm). The device would then be termed as DVCC-transimmittance amplifier which fits
into the general acronym DVCCTA; following the specific need of a designer, this
building block may then be configured as transcapacitive/transconductive in a flexible
way while the nodal relations would be Vx = (V1 V2), Iz = Ix for the CC stage and Io = Ym
Vz for the VCIS output stage coupled together we get the generalised form of the
DVCCTA as in Figure 1(a). To this end, the AD-844 CFA (Tammam et al., 2013) is an
appropriate choice for its device implementation, preferably with all equal-value internal

Y2

DVCCTA
(Ym)
X

Y1

X
Y1

AD844

_
_

AD844

AD844

Y2

+
AD844

Ym

(a)
I1
Y2

V1

Y1
Cp1

Y2

O
DVCCTA
(Ym1)
X

Y1

gp1

Cp2
Y1

Cz1

gz1

Yo

O
DVCCTA
(Ym2)
X

I2

V2

gp2
Y2

Cz2

gz2

(b)

Figure 1. DVCC-transimmittance amplifier device and FLIF realisation, (a) implementation with
readily available AD-844 CFA elements, (b) floating immittance simulation using DVCCTA.

Downloaded by [Central Electronics Engineering Research Institute] at 01:35 19 February 2015

International Journal of Electronics Letters

resistors (r) while using a single-chip (AD-844) or quad-chip (EL-2460) CFA (Senani,
Bhaskar, Singh, & Singh, 2013) IC modules. It is seen that with this implementation, Ym is
grounded leading to topological convenience in view of its integration point of view since
only one terminal could be brought out of the chip for connecting gm or Cm appropriately
as the circuit application may call for.
Here we present a new generalised active circuit topology for the simulation of a
lossless immittance function (FLIF) which yields synthetic inductor if Ym = gm, and
FDNR-type (D) supercapacitor (Nandi, Sanyal, & Bandyopadhyay, 2006) if Ym = sCm.
Analysis including the effects of the various device nonidealities indicates insignificant
deviations from nominal design with extremely low active sensitivity with respect to the
port errors (). It is seen that the device parasitic capacitors (Cp,z), which appear along
with shunt resistive (rp,z) part, tend to degrade the quality of the floating D and L
elements, while imposing a usable frequency limit . These parasitics, however, are quite
small (3 pF < Cp,z < 7 pF and 2 M < rp,z < 5 ), enabling the designer to select nominal
circuit RC values such that the ratios are insignificant at the desired range of operating
frequencies. The simplified realisability conditions for true bilinear FLIF simulation are
worked out. Performance of the proposed FLIFs was verified with a suitable design of
good-quality selective filters (Q 7.2) working up to about 1 MHz.

2. Analysis
The proposed topology is shown in Figure 1; the device port relations are Vx =
(V1 V2), Iz = Ix, Io = YmVz and Iy1 = 0 = Iy2, where the port transfers may be
postulated by some error coefficients (|| << 1) as (1 v), (1 i) and (1 o).
The two-port floating driving point admittance matrix here is given in Equation (1); the
matrix elements are shown in Table 1 where the effects of device imperfections are shown
in a comprehensive manner.

Y 

Y11  Y12
Y21
Y22


(1)

Thus, if errors are assumed negligible, one gets an ideal floating inductor with identical
amplifiers. For true bilinear FLIF, the realisability designs are Ym1 = Ym2 = gm = 1/R and
Table 1.

Matrix
elements
Y11
Y12
Y21
Y22

Y-matrix elements under nonideal conditions: immittance simulation.

Inductor (L)

Supercapacitor (D)

Ym1,2 = gm1,2

Ym1,2 = sCm1,2

With finite

Y1,2 = 1/R1,2; Yo = sC

Y1,2 = sC1,2; Yo = 1/R

With finite
parasitics

111(Y1Ym1/Yo)
12(Ym1Ym2/Yo)
1122(Y1Y2/Yo)
222(Ym2Y2/Yo)

L11 = (1 + 1)CR1/gm1
L12 = (1 + 2)C/gm1 gm2
L21 = (1 + 3)CR1R2
L22 = (1 + 4)CR2/gm2

D11 = (1 1)C1Cm1 R
D12 = (1 2)Cm1Cm2 R
D21 = (1 3)C1C2 R
D22 = (1 4)Cm2C2 R

Yp1 + (Y1Ym1/Yt)
Ym1Ym2/Yt
Y1Y2/Yt
Yz2 + (Y2Ym2/Yt)

1 = i1 + v1 + o1; 2 = o1 + o2; 3 = v1 + v2 + i1 + i2; 4 = i1 + v2 + o2;

Yp1,2 = sCp1,2 + gp1,2; Yz1,2 = sCz1,2 + gz1,2; Yt = Yo + Yp2 + Yz1.

R. Nandi et al.

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Y1,2 = 1/R1,2, 1/R, Yo = sC; the inductance value is L = CR/gm. For an ideal supercapacitor (D), we select identical transcapacitive amplifier Ym1 = Ym2 = sCm and Y1,2 = sC,
Yo = 1/R which yields floating supercapacitor Y = s2 D; D = C2 R with Cm = C. Here, all
passive components are grounded (Senani, 1989); hence, the topology may be suitable for
microcircuit fabrication. The synthetic-L may be tuned by a single capacitor (C), while D
is tunable by a resistor (R). It may be noted that albeit the nominal values of L and D are
slightly reduced owing to finite port errors, their lossless feature is preserved while the
active sensitivities are quite low. The modified values are
L'11 =L11  1 1 ; L'12 =L12  1 2 ; L'21 =L21  1 3 ; L'22 =L22
 1 4 and D'11 =D11  1  1 ; D'12 =D12  1  2 ; D'21 =D21
 1  3 ; D'22 =D22  1  4
The active sensitivities with respect to the port errors () could be calculated as
S L;D  f=1   g<<1:
The effects of the parasitics of the devices had been examined next by assuming
presence of capacitors (Cp,z), associated with their (Potson, 1991) shunt resistances(rp,z);
as per device databook (Analog Devices, 1990), Cp,z are quite small(3 pF Cp,z 7pF)
and resistors are high (2 M rp,z 5M). It is seen that effects of Cp,z are more
pronounced in degrading the quality of the simulated immittances while imposing a
maximum usable frequency range. However, we note that all the parasitic capacitors are
grounded that enables the designer a scope for their inclusion in the nominal C-values; the
shunt resistive parasitic component yields insignificant effect on the design since their
values are sufficiently large relative to the nominal resistance values used in the circuit
such that their ratios are negligible which enables the designer to obtain good-quality
bilinear FLIF realisation.
The basic equations for the elements of the Y-matrix, involving the parasitics, are also
shown in Table 1.
The design equations, taking into effect these parasitics, are summarised in Tables 2
and 3. Our literature survey indicates some applicabilities of the DVCC-transconductance
(gm) device in filter/oscillator design (Jantakun et al., 2009; Lahiri, Jaikla, &
Siripruchyanun, 2010; Pandey, Pandey, & Paul, 2012; Pandey & Paul, 2011; Verma &
Gautam, 2013). Table 4 shows a brief comparative description of the various design
schemes. It is seen that all these realisations are based on gm mode of operation and some
designs use bias current control of gm. Detailed analysis on the effects of parasitic
capacitors is given only for the AP filter/oscillator design (Pandey et al., 2012). It may
be shown that good-quality inductor and supercapacitor-based active filters could be
designed with the design equations presented here; some satisfactory test results were
obtained as described in the next section.

3. Experimental results
The characteristics of the proposed FLIF topologies had been tested in the design of some
active filters, viz., a third-order maximally flat-gain lowpass (LP) Butterworth filter is
built by cascading a second-order LCR filter with a simple RC first-order structure while a
moderately high selectivity (Q 7.2) band-reject (BR) filter is built by the floating D

12(Ym1Ym2/Yo) (1 )(gm1gm2/sC)
11 2 2 (Y1Y2/Yo) (1 )(1/sCR1R3)
222(Ym2Y2/Y0) (1 )(gm2/sCR3)

Y12
Y21
Y22

[s2Cp1CRm1R1 (1 + ) + sCR1Rm1gp1{1 + + }
+(1 + )]/{sCRm1R1 (1 + ) + (gt/gm1G1)}
1/[sC Rm1Rm2(1 + ) + (gt/gm1gm2)]
1/[sC R1R2(1 + ) + (gtR1R2)]
[s2Cz2CRm2R2 (1 + )+ sCR2Rm2 gz2{1 + + }
+(1 + d)]/{sCR2Rm2(1 + )+(gt/gm2G2)}

(Cp,z 0; = 0)

q12 C/gt >> 1

q21 C/gt >> 1
q22 rz2{Cz2/CRm2R2} >> 1

q11 rp1{Cp1/CRm1R1} >> 1

Quality(q) of immittance pole

location at p gt/C (for > p)

= Ct/C, Ct = Cz1 + Cp2, = gp1gt/G1gm1, = Cp1gt/Cgp1, = Cz2gt/Cgz2, d = gz2gt/G2gm2, gt = gz1 + gp2; , , , , d << 1.
2
Simplified design: Y1,2 = 1/R = gm1,2 and Yo = sC for true bilinear realisability of Y = 1/sL, where L = R C with frequency limit of > gt/C; hence, lower operating frequency is
L gt/C; typical estimate fL 200 Hz assuming C = 320 pF and 1/gt = 2.7 M (measured).
2
With q11,22 >> 1, the immittances Y11,12 may show unstable oscillations at its upper operating frequency U 1/(LCp1,z2); a typical estimate is fU 5.1 MHz assuming L = CR with
C = 320 pF, R = 1 k and Cp1 3.3 pF (measured).

111 (Y1Ym1/Yo) (1 )(gm1/sCR1)

Y11

( 0; Cp,z 0)

Nonideal

Floating L-simulation in Figure 1 under nonideal conditions with Y1,2 = 1/R1,2 Yo = sC,Ym1,2 = gm1,2.

Matrix elements

Table 2.

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International Journal of Electronics Letters

5

s C1C2/{sCt + G(1 + m)}

[s2C2Cm2(1 + n) + sCz2 G(1 + m + ) + gz2 G(1 + m)]/
{sCt + G(1 + m)}

222(Ym2Y2/Yo) (1 )(s D)

Y22

q22 (C/Cz2))(R/rz2) >> 1

Y22 s2D

Y12 = Y21 s2D

q11 (C/Cp1))(R/rp1) >> 1

q11 >> 1: Y11 s2D

Quality (q) of immittance

pole location at p = 1/CtR
(for < p)

a = (Cp1Ct/C1Cm1); b = {(gt/G) + (gp1Ct/gCp1)}; m = (gt/G); n = (CtCz2/C2Cm2); = {(gz2Ct/GCz2), x = rz1/rp2 1; Ct = Cz1 + Cp2; gt = gz1 + gp2; D = C2 R; a, b, m, n << 1.
2
2
Simplified design: Y1,2 = sC, Cm1 = Cm2 = C and Yo = 1/R for true bilinear realisability of Y = s D, where D = RC with frequency limit of < 1/RCt; hence, upper operating
frequency limit is p = u 1/CtR; typical estimate fU = 15.9 MHz assuming R = 1.7 K. and Ct = 6.6 pF.
The lower frequency limit is estimated to be at L 1/(Drp1,z2), e.g., a typical estimate is fL 1.5 KHz if C = Cm = 1 nF, rp,z 5.4 M (measured) and R = 1.7 K.

1122(Y1Y2/Yo) (1 )(s D)
2

Y21

12(Ym1Ym2/Yo) (1 )(s2D)

Y12

[s2C1Cm1(1 + a) + sCp1 G(1 + b)+Ggp1(1 + m)]/

{sCt + G(1 + m)}
s2Cm1Cm2/{sCt + G(1 + m)}

111(Y1Ym1/Yo) (1 )(s2D)

(Cp,z 0; = 0)

Y11

( 0; Cp,z = 0)

Nonideal

Floating supercapacitor (D) simulation in Figure 1 under nonideal conditions with Y1 = sC1, Yo = G = 1/R, Y2 = sC2, Ym1,2 = sCm1,2.

Matrix elements

Table 3.

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6
R. Nandi et al.

1(gm)
1(gm)
1:Filter
2:Oscillator
1(gm)
2(gm/sCm) (transimmittance)

Lahiri et al. (2010)

Pandey and Paul (2011)
Pandey et al. (2012)

Verma and Gautam (2013)

Proposed

2(gm)

DVCCTAs used (mode)

C-1, R-2 (for L)
C-2, R-1 (for D)
C-2, R-2
C-2, R-1
C-1, R-1
C-2, R-2
C-2, R-2
C-1, R-2 (for L)
C-2, R-1 (for D)

Passive components used

Comparative description of proposed simulations with some recent publications.

Jantakun et al. (2009)

Reference

Table 4.

Filters 1 MHz
L and D simulator filter 955 KHz

Quadrature oscillator 348 KHz

Filter 1.59 MHz
AP filter/oscillator 1.59 MHz

L and D simulator filter 200 KHz

Function frequency range

Nonideal effect
Effect of only port mismatch
errors considered
Not reported
Not reported
Effect of parasitic capacitor
considered
Not reported
Effects of both port mismatch
errors and parasitics are
analysed

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International Journal of Electronics Letters

7

R. Nandi et al.
0

L R
0

30

F1
1/(s + 1)

C0

F1
60
90

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100

1000

10,000

KHz

(a)
KHz

10

100

1000

10,000
D
R0

F2 10

F2
C0

20

(b)

Figure 2. Experimental results for the active filters based on the proposed FLIFs: hardware test;
simulation. (a) Third-order LP Butterworth characteristics obtained using the floating L; design
for 3 dB frequencies at 955 KHz with R = 1 K, C = 160 pF and at 500 KHz with R = 1 K,
C = 320 pF; corresponding -values for the cascaded first-order stage are matched for maximally flat
response. (b) Second-order BR filter based on the floating D; design for centre frequency at
900 KHz and Q 7.2 with C = Cm = 100 pF, R = 1.7 K = Ro, Co = 15 pF.

being shunted by a resistor as shown in Figure 2. The experimental results, being

measured with hardwire test, and PSPICE (Macromodel of AD 844 AN, 1992) simulation
are shown graphically.

4. Conclusion
A new active circuit design scheme for the simulation of synthetic FLIFs based on the
DVCCTA element is proposed. The active building block had been intuitively configured
in transconductive (gm) or transcapacitive (sCm) mode, respectively, for the design of a
synthetic inductor (L) as first-order immittance and for a supercapacitor (D)-type FDNR
as second-order immittance. The DVCCTA block is implemented with readily available
AD-844 CFA devices, wherein the gm or Cm had been inserted conveniently in the circuit
architecture according to the specific design need.
The effects of the device nonidealities had been analysed; the port mismatch errors
cause a slight reduction in the nominal values of L and D while their lossless feature
remains unaffected. The effects of the parasitics cause certain variation in the
Y-parameters affecting the bilinear feature; it is also seen that the parasitic capacitors

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International Journal of Electronics Letters

tend to impose an upper limit on the usable frequency range of the proposed synthetic
immittances. However with appropriate design, the lossless bilinear nature of the floating
L and D could be preserved; here, we observed that all three passive components in the
simulating circuit are grounded and if the values of these resistors and capacitors are
chosen such that their ratios with respect to the parasitic components (rp.z 5.4 M and
Cp,z 3.3 pF measured) are kept low, desired results could be obtained that enables the L
and D elements, in the floating form, suitable for applications to high-selectivity filter
design, albeit up to a frequency range as set by the parasitic capacitor. To this end,
improved version of the CFA (Tammam et al., 2013) devices with extremely low Cp,z
values (News Updates, 2004) is expected to yield improved high-frequency response for
such design.
Experimental results were obtained satisfactorily with some active filter design, viz.,
the floating L had been used to obtain a third-order LP Butterworth filter, and the floating
D was used for a BR filter; test responses had been verified with PSPICE simulation and
by hardware test which are presented here.
In summary, with this work, we tried to propose that albeit the DVCCTA building
block had so far been used only as a DVCC-transconductance (gm) amplifier in the
literature, it may be configured more elegantly as the DVCC-transimmittance (Ym)
amplifier if the output VCIS stage is set to have an immittance (e.g., a capacitor) as
load termination instead of simply a resistor. This proposition leads to yield additional
versatility and flexibility to this building block keeping in view the range of its applicabilities to analog circuit design, e.g., the proposed realisation as presented simulates a
first-order immittance (L) with the device in gm-mode while one gets the second-order
immittance (D) when it is in Ym(=sCm) mode in the same circuit structure. This conceptual
extension of the idea on the enhancement of the capabilities of the active building block is
believed to open up further DVCCTA-based research possibilities.
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