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EPE2013 - FPGA Motor Drive Based SRM PDF
EPE2013 - FPGA Motor Drive Based SRM PDF
EPE2013 - FPGA Motor Drive Based SRM PDF
Keywords
Switched-Reluctance Motor, SRM, DC-DC converter, Buck converter, Boost converter, FPGA, Real-time
simulation, HIL simulation.
Abstract
In this paper, we describe an FPGA implementation of a Switched Reluctance Motor Drive (SRM) and an H-bridge
Buck-Boost converter targeted for Hardware-In-the Loop (HIL) testing of modern SRM controllers. These FPGA
models allow the HIL simulation of SRM drive and boost converter with switching frequencies in the 50-100 kHz
range because of the very high sampling rate of the FPGA. The models are also integrated into the RT-LAB realtime environment and directly linked with the simulator I/Os, providing ultra-low HIL gate-in-to-current-out
latency, suitable for testing modern motor controllers.
Introduction
As of 2012, its a very common industrial practice to validate motor drive control with Hardware-In-the-Loop
(HIL) simulation[1][2]. The advantages of this are numerous: for example, the real-time simulated motor drive can
be tested with borderline conditions that would damage a real motor prototype. With ever decreasing time-tomarket, HIL simulation enables engineers to design the motor and power electronic controls in parallel to the motor
drive and power converter themselves. Hybrid electric vehicle (HEV) OEMs and other motor drive manufacturers
use HIL technology to speed up development time by allowing early error detection before conducting tests on
physical prototypes. At the production stage, HIL simulation can also be used to verify code integrity at controller
software releases with automated correlation tests.
In the field of HEV, permanent magnet synchronous motors (PMSM) are the preferred choice of many
manufacturers, mainly for efficiency reasons. Recently, the interest in switched reluctance motor drive has
increased greatly because the high cost of rare-earth metals used in PMSM. SRM drives also benefit from its low
manufacturing costs, rugged construction and simplicity of controller design. Since the rotor has no windings and
no magnets, it is a good candidate for drive operation at high speed and in adverse environments. As with the
PMSM, a real-time simulator is the ideal tool to conduct research on this relatively new application of the SRM.
Sensorless drive designs and control optimisations, for example, pose challenges that can be tackled efficiently
with a real-time simulator.
Advances in power electronics have made possible the design of very high switching frequency motor drive and
power converters. The SRM drive, with its high speed capability, can require switching frequencies reaching 20
kHz. Modern HEV topologies with voltage boosting stage goes further with DC-DC converters with PWM
frequencies up to 100 kHz.
The HIL testing of such devices therefore requires a real-time simulator with a very high sampling rate, preferably
below 500 nanoseconds in stringent applications, to obtain reasonable accuracy at 100 kHz. FPGA-based SRM
drive and DC-DC converters are an excellent solution to this challenge. In this paper, we detail such a model
implemented on a Virtex-6 FPGA chip within the RT-LAB real-time system.
1
Paper presented at the EPE'13 ECCE Europe conference, September 3-5, 2013, Lille, France
Paper presented at the EPE'13 ECCE Europe conference, September 3-5, 2013, Lille, France
Model Latencies
Of special importance are the latencies of the different modules. From the controller point of view, the latency from
the gate sampling at the digital input of the simulator to the output of the current at the analog output (SRM or DCDC drive) must be minimal, under 1 s in some applications. Also, the model sampling frequencies should be at
100 times higher than the PWM frequency in use (i.e. for 1 % precision).
ML605 Virtex-6 FPGA boards are used in the current implementation of these models with a 200 MHz clock. On
the RT-LAB simulator, these FPGA boards are directly connected to 16 fast D/A converters with a simultaneous
conversion rate of 1 s.
Table 1: SRM drive and buck-boost converter sampling rate and latencies
Module
Sampling rate/Latency (ns) (not including D/A)
SRM inverter
30/{25-50} ns (gate-to-Vabc)
30/{60-105} (gate-to-Idc)
SRM motor (6/4)
120/{210-300}ns (Vabc-to-Iabc)
H-bridge Buck-Boost converter
120/{85-200} ns (gate-to-Vcapa/Iind)
Table 1 details the various model subsystems sampling rates and latencies. These two are not equal. The sampling
rate is the rate at which each block samples its inputs. Latency is the delay between the input sampling and the
resulting change of the block outputs. The subsystems latency is also variable in the range {minimum, maximum}
in the table, mainly because of the pipelining methods used in coding coupled with the asynchronicity of the gate
inputs (for the inverter and converter).
As it can be seen, the total latency for the controller firing output signal to the motor current output is 235 ns to
350 ns without taking account of the analog output converter conversion delays and the time response of the current
sensors that could also be simulated in the FPGA. The D/A converters installed on the simulator have a conversion
rate of 1 s.
Models configurability
From the industrial users point of view, its important that the models offer some flexibility, especially in terms of
parameterization. However, todays FPGA technology still suffers from a very long compilation time (i.e. Place
and route, and bitstream generation) that can easily take 1 or 2 hours for a large FPGA like the Virtex-6. This
compilation time would result in very long and often unacceptable iteration times for any test engineer.
The models presented in this paper avoid this problem by allowing all their parameters to be loadable as signals to a
fixed bitstream. This way, changes of SRM motor parameters (Stator resistance, SRM flux and torque tables,
number of poles, etc) and Buck-Boost converter (Resistance, capacitance and inductance), can be done easily onthe-fly, without regenerating new bitstreams.
This is an important feature to increase user interactivity with the simulator. This flexibility is increased even more
with the eHS generic FPGA solver [8] and allows users to modify the circuit topology or even create new
converter topologies without generating a new bitstream. This is a great advantage for projects in which the filter
and converter topology must be optimized.
Paper presented at the EPE'13 ECCE Europe conference, September 3-5, 2013, Lille, France
(V
abc
Rs I abc ) dt abc
(1)
where Iabc is the stator current inside the winding, Rs is the stator resistance and Vabc is the voltage across the
stator windings. The current is then derived from the machine flux characteristics and stored in tables on the FPGA.
Fig. 2. Left: Three-dimensional relationship between excitation current, rotor position and flux linkages
for 12/8 SRM motor Right: FEA analysis on the 12/8 SRM in MotorSolve.
In the SRM, there is a three-dimensional relationship between excitation current, rotor position and flux linkages.
This flux relationship can be found using commercial FEA software like JSOLs JMAG-Studio[9] or Infolyticas
MotorSolve[10]. Fig. 2 shows this flux relationship and the corresponding FEA analysis using MotorSolve for the
12/8 SRM used for example in this paper.
From this ( I , ) flux relationship, the OPAL-RT model derives the inverse characteristic I ( , ) , using spline
methods[6][7]. This inverted characteristic is shown in Fig. 3. Note the electric angle scale from 0 to 90 in the
figures because a 12/8 SRM is electrically equivalent to a 6/4 SRM.
Paper presented at the EPE'13 ECCE Europe conference, September 3-5, 2013, Lille, France
The produced electrical torque is also derived from the flux-current characteristic, pre-computed and stored in
tables prior to the real-time simulation. The torque is computed by integration and derivation of the machine coenergy Wc using Eq. (2). For the same motor again, Fig. 3 shows the torque characteristic obtained.
Te ( I , )
Wc ( I , )
Wc ( I , )dI
(2)
The SRM motor model uses Time-Domain-Multiplexing (TDM) in the solver design using single precision
floating-point arithmetic. TDM pipelines the equations of the motor (integration, addition, etc) into a serial
sequence of arithmetic operators and results in very low sampling times. Pipelining, however, induces a latency
that is greater than the sampling time.
Paper presented at the EPE'13 ECCE Europe conference, September 3-5, 2013, Lille, France
Fig. 4. DC-DC converter load step. FPGA on-chip results (left) vs. SPS offline simulation (right)
Fig. 5. SRM Drive current command step: FPGA results (left) vs. SPS offline simulation (right)
Paper presented at the EPE'13 ECCE Europe conference, September 3-5, 2013, Lille, France
Fig. 6. SRM drive latency: from Digital Input to SRM voltage input ( left) and SRM current (right)
The key aspect of this HIL latency measurement is the non-synchronicity of the Analog Output converter, running
at 1 s rate, and the digital inputs of the drive. This results in a dispersion of the latency of about 1 s, easily
observable on the voltage latency measurement but also present on the current one. The latency of the SRM drive
model on FPGA is consequently equal to 1.75s 0.5 s from Digital Input to Voltage Output and 2s 0.5 s
from Digital Input to motor winding current. The latter measurement is more important because it can influence the
hysteretic current control of the SRM drive. The use of a faster digital to analog converter with a 100 or 200
nanosecond conversion time would decrease the total latency to values closer to the model calculation time of
about 350 ns.
Conclusion
This paper presented an ultra-low latency HIL model and SRM drive and DC-DC boost converter, designed on an
FPGA chip. The paper explained the various feature of the models along with validation tests. The tests confirmed
that the models are accurate in steady-state and dynamic response. The latency of the SRM drive, from the digital
inputs to the motor currents at the analog outputs was measured to be equal to 2s 0.5 s. Such a low latency, the
lowest ever reported for an SRM HIL system, can help to achieve high accuracy simulation with an real hysteretic
controller in the loop.
One key aspect of the presented models is that they do not require the user to regenerate a bitstream if some
parameters change, including the SRM flux-current FEA data or boost converter RLC values for example. This is
important for the industrial usability of the models because bitstream generation of such complex model can take
hours to complete. We are currently waiting to obtain HIL results with the client controllers connected to the realtime simulator.
Paper presented at the EPE'13 ECCE Europe conference, September 3-5, 2013, Lille, France
References
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Motion Control Conference, EPE-PEMC 2012, Novi Sad, Serbia, Sept. 4-6, 2012
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[9] JMAG-Studio and JMAG-RT v.10.5, JSOL Corporation, Tokyo, Japan
[10] MotorSolve v.4.1 Infolytica Corporation, Montral, Canada.