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Comb Logic
Comb Logic
Comb Logic
case excels when many tests are performed on the same expression.
case works well for muxes, decoders, and next state logic.
case Statement
U42
U35
U34
U23
U22
U25
U24
U27
U26
always_comb
case (sel)
2b00
2b01
2b10
2b11
endcase
endmodule
U29
U41
:
:
:
:
d_out
d_out
d_out
d_out
=
=
=
=
U39
a_in;
b_in;
c_in;
d_in;
U28
U31
U30
U33
U32
U40
U37
U38
U36
case Statement
Is the simulation correct?
//"full case" case statement
module case1 (
input
[7:0] a_in, b_in, c_in, d_in,
input
[1:0] sel,
output reg [7:0] d_out);
always_comb
case (sel)
2b00
2b01
2b10
2b11
endcase
endmodule
:
:
:
:
d_out
d_out
d_out
d_out
=
=
=
=
a_in;
b_in;
c_in;
d_in;
/case1/a_in 10
/case1/b_in 20
/case1/c_in 30
/case1/d_in 40
/case1/sel 0
/case1/d_out 10
20
30
40
case Statement
Use default case to propagate x
//"full case" case statement
module case1 (
input
[7:0] a_in, b_in, c_in, d_in,
input
[1:0] sel,
output reg [7:0] d_out);
always_comb
case (sel)
2b00
2b01
2b10
2b11
default
endcase
endmodule
:
:
:
:
:
d_out
d_out
d_out
d_out
d_out
=
=
=
=
=
a_in;
b_in;
c_in;
d_in;
8bx;
/case1/a_in 10
/case1/b_in 20
/case1/c_in 30
/case1/d_in 40
/case1/sel 0
/case1/d_out 10
20
30
40
xx
case Statement
U17
...g[6]
U18
...g[5]
U19
...g[4]
U20
...g[3]
U21
always_comb
case (sel)
2b00
: d_out = a_in;
2b01
: d_out = b_in;
2b10
: d_out = c_in;
endcase
endmodule
U25
...g[2]
U22
...g[1]
U27
U26
U23
...g[0]
U24
U15
...g[7]
U16
case Statement
a_in[6]
b_in[6]
c_in[6]
U11
d_out[7:0]
sel[1]
sel[0]
a_in[5]
U12
b_in[5]
U13
c_in[5]
a_in[4]
b_in[4]
c_in[4]
U14
a_in[3]
b_in[3]
c_in[3]
:
:
:
:
d_out
d_out
d_out
d_out
=
=
=
=
a_in;
b_in;
c_in;
8bx;
a_in[2]
b_in[2]
c_in[2]
a_in[1]
b_in[1]
c_in[1]
sel[1:0]
U18
U15
U16
n3
a_in[0]
b_in[0]
c_in[0]
sel[1:0]
always_comb
case (sel)
2b00
2b01
2b10
default
endcase
endmodule
c_in[7:0]
a_in[7:0]
b_in[7:0]
U17
c_in[7:0]
a_in[7:0]
b_in[7:0]
a_in[7]
b_in[7]
c_in[7]
U10
d_out[7:0]
case Statement
System Verilog priority Modifier
I SystemVerilog introduced two case and if statement modifiers
I
I
priority
unique
Both imply that there is a case item for all the possible legal values
that case expression might assume.
Priority
I
I
I
Priority tells the simulator that if all is well, you will find a match
If a match is not found at run-time, emit an error or warning.
Since all legal combinations are listed, synthesis is free to optimize any
other unlisted case items since they are effectively dont-cares.
Priority does not guarantee removal of unintended latches.
case Statement
a_in[6]
b_in[6]
c_in[6]
U11
d_out[7:0]
sel[1]
sel[0]
a_in[5]
U12
b_in[5]
U13
c_in[5]
a_in[4]
b_in[4]
c_in[4]
U14
a_in[3]
b_in[3]
c_in[3]
a_in[2]
b_in[2]
c_in[2]
a_in[1]
b_in[1]
c_in[1]
sel[1:0]
U18
U15
U16
n3
a_in[0]
b_in[0]
c_in[0]
sel[1:0]
always_comb
priority case (sel)
2b00
: d_out = a_in;
2b01
: d_out = b_in;
2b10
: d_out = c_in;
endcase
endmodule
c_in[7:0]
a_in[7:0]
b_in[7:0]
U17
c_in[7:0]
a_in[7:0]
b_in[7:0]
a_in[7]
b_in[7]
c_in[7]
U10
d_out[7:0]
Warning: case2.sv:7: Case statement marked priority does not cover all possible conditions. (VER-504)
case Statement
Go back, fix the error that caused the unallowed case to occur.
case Statement
//incomplete case statement
//with systemverilog priority modifier
module case2 (
input
[7:0] a_in, b_in, c_in,
input
[1:0] sel,
output reg [7:0] d_out);
always_comb
priority case (sel)
2b00
: d_out = a_in;
2b01
: d_out = b_in;
2b10
: d_out = c_in;
endcase
endmodule
case Statement
casez Statement
I
I
I
I
I
casez Example
module interrupt_ctl1 (
output
reg
int2, int1, int0,
input [2:0]
irq
);
always_comb begin
{int2, int1, int0}
casez (irq)
3b1?? : int2 =
3b?1? : int1 =
3b??1 : int0 =
endcase
end
endmodule
3b0;
1b1;
1b1;
1b1;
//default
casez Statement
casez Example
U7
module interrupt_ctl1 (
output reg int2, int1, int0,
input [2:0] irq );
always_comb begin
{int2, int1, int0} = 3b0; //default
casez (irq)
3b1?? : int2 = 1b1;
3b?1? : int1 = 1b1;
3b??1 : int0 = 1b1;
endcase
end
n3
irq[2:0]
n4
U6
int0
int0
irq[2:0]
irq[0]
U5
irq[1]
U8
int1
int1
irq[2]
int2
casez Statement
If the irq bus has any of the values: 3b011, 3b101, 3b110 or
3b111, more than one case item could match the irq value.
casez Statement
Parallel or Unique Encoding
module interrupt_ctl2a (
output reg
int2, int1, int0,
input
[2:0] irq );
always_comb begin
{int2, int1, int0} = 3b0; //default
unique casez (irq)
3b1?? : int2 = 1b1;
3b01? : int1 = 1b1;
3b001 : int0 = 1b1;
endcase
end
irq[1]
int0
U8
int0
U6
int1
int2,irq[1]
int1
irq[2:1]
U7
n2
int2
int2
irq[0]
casez Statement
Now what?
I
Using unique, I get about 10% decrease in delay and area at best.
At this point, until I can bet a better handle on it, avoid unique.
casex Statement