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74LVT162245 Transceiver
74LVT162245 Transceiver
74LVT162245 74LVTH162245
Low Voltage 16-Bit Transceiver with 3-STATE Outputs
and 25: Series Resistors in A Port Outputs
General Description
Features
The LVT162245 and LVTH162245 contains sixteen noninverting bidirectional buffers with 3-STATE outputs and is
intended for bus oriented applications. The device is byte
controlled. Each byte has separate control inputs which
can be shorted together for full 16-bit operation. The T/R
inputs determine the direction of data flow through the
device. The OE inputs disable both the A and B ports by
placing them in a high impedance state.
The LVT162245 and LVTH162245 are designed with
equivalent 25: series resistance in both the HIGH and
LOW states on the A Port outputs. This design reduces line
noise in applications such as memory address drivers,
clock drivers, and bus transceivers/transmitters.
Bushold data inputs eliminate the need for external pullup resistors to hold unused inputs (74LVTH162245),
also available without bushold feature (74LVT162245).
Live insertion/extraction permitted
Power Up/Down high impedance provides glitch-free
bus loading
A Port outputs include equivalent series resistance of
25: making external termination resistors unnecessary
and reducing overshoot and undershoot
A Port outputs source/sink r12 mA.
B Port outputs source/sink 32 mA/64 mA
Functionally compatible with the 74 series 162245
Latch-up performance exceeds 500 mA
ESD performance:
Ordering Code:
Order Number
74LVT162245G
(Note 1)(Note 2)
Package Number
BGA54A
(Preliminary)
Package Description
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
74LVT162245MEA
(Note 2)
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LVT162245MTD
(Note 2)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
74LVTH162245G
(Note 1)(Note 2)
BGA54A
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
74LVTH162245MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[TUBE]
74LVTH162245MEX
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[TAPE and REEL]
74LVTH162245MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TUBE]
74LVTH162245MTX
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]
DS012446
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74LVT162245 74LVTH162245 Low Voltage 16-Bit Transceiver with 3-STATE Outputs and 25: Series Resistors in
A Port Outputs
January 1999
74LVT162245 74LVTH162245
Logic Symbol
Connection Diagrams
Pin Descriptions
Pin Names
Description
OEn
T/Rn
Transmit/Receive Input
A0A15
B0B15
NC
No Connect
B0
NC
T/R1
OE1
NC
A0
B2
B1
NC
NC
A1
A2
B4
B3
VCC
VCC
A3
A4
B6
B5
GND
GND
A5
A6
B8
B7
GND
GND
A7
A8
B10
B9
GND
GND
A9
A10
B12
B11
VCC
VCC
A11
A12
B14
B13
NC
NC
A13
A14
B15
NC
T/R2
OE2
NC
A15
Truth Tables
Inputs
OE1
Pin Assignment for FBGA
T/R1
Outputs
Inputs
OE2
T/R2
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Outputs
Bus B8B15 Data to Bus A8A15
The LVT162245 and LVTH162245 contain sixteen noninverting bidirectional buffers with 3-STATE outputs. The
device is byte controlled with each byte functioning identi-
Logic Diagrams
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74LVT162245 74LVTH162245
Functional Description
74LVT162245 74LVTH162245
Parameter
VCC
Supply Voltage
VI
DC Input Voltage
VO
Output Voltage
IIK
IOK
IO
DC Output Current
Value
Conditions
0.5 to 4.6
0.5 to 7.0
0.5 to 7.0
0.5 to 7.0
50
50
ICC
IGND
TSTG
Storage Temperature
Units
V
V
Output in 3-STATE
mA
VO GND
mA
64
VO ! VCC
128
VO ! VCC
mA
r64
r128
65 to 150
mA
mA
qC
Parameter
VCC
Supply Voltage
VI
Input Voltage
IOH
Min
Max
Units
2.7
3.6
5.5
32
12
mA
B Port
A Port
IOL
TA
't/'V
0.8V2.0V, VCC
B Port
64
A Port
12
3.0V
mA
40
85
qC
10
ns/V
Note 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 4: IO Absolute Maximum Rating must be observed.
DC Electrical Characteristics
Symbol
VCC
Parameter
VIK
VIH
2.73.6
VIL
2.73.6
VOH
A Port
B Port
II(HOLD)
(Note 5)
II(OD)
(Note 5)
II
Input Current
Data Pins
Power Off Leakage Current
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1.2
0.8
2.0
VCC0.2
2.7
2.4
3.0
2.0
Units
Conditions
18 mA
II
VO d 0.1V or
VO t VCC 0.1V
IOH
12 mA
IOH
100 PA
IOH
8 mA
IOH
32 mA
IOL
12 mA
3.0
0.8
2.7
0.2
IOL
100 PA
2.7
0.5
IOL
24 mA
3.0
0.4
IOL
16 mA
3.0
0.5
IOL
32 mA
3.0
0.55
75
3.0
IOL
PA
75
500
3.0
Control Pins
IOFF
2.73.6
Max
2.0
3.0
A Port
40qC to 85qC
Min
2.7
B Port
VOL
TA
(V)
PA
500
64 mA
VI
0.8V
VI
2.0V
(Note 6)
(Note 7)
3.6
10
VI
5.5V
3.6
r1
VI
0V or VCC
VI
0V
VI
VCC
5
3.6
PA
r100
PA
0V d VI or VO d 5.5V
Symbol
(Continued)
VCC
Parameter
TA
(V)
IPU/PD
Power Up/Down
3-STATE Current
40qC to 85qC
Min
Units
Conditions
Max
01.5V
r100
PA
VO
VI
0.5V to 3.0V
GND to VCC
IOZL
3.6
5
PA
VO
0.5V
IOZL
3.6
5
PA
VO
0.0V
IOZH
3.6
PA
VO
3.0V
IOZH
3.6
PA
VO
3.6V
(Note 5)
(Note 5)
IOZH
3.6
10
PA
VCC V O d 5.5V
ICCH
3.6
0.19
mA
Outputs HIGH
ICCL
3.6
mA
Outputs LOW
ICCZ
3.6
0.19
mA
Outputs Disabled
ICCZ
3.6
0.19
mA
'ICC
3.6
0.2
mA
(Note 8)
VCC d V O d 5.5V,
Outputs Disabled
One Input at VCC 0.6V
Other Inputs at VCC or GND
Parameter
(Note 9)
VCC
(V)
TA
Min
25qC
Typ
Max
Units
Conditions
CL
50 pF, RL
VOLP
3.3
0.8
(Note 10)
VOLV
3.3
0.8
(Note 10)
500:
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74LVT162245 74LVTH162245
DC Electrical Characteristics
74LVT162245 74LVTH162245
AC Electrical Characteristics
40qC to 85qC
TA
Symbol
tPLH
CL
Parameter
tPHL
Propagation Delay Data to B Port Output
tPLH
tPHL
tPZH
tPZL
tPZH
tPZL
Output Disable Time for A Port Output
tPHZ
tPLZ
tPHZ
tPLZ
tOSHL
tOSLH
(Note 11)
tOSHL
tOSLH
(Note 11)
50 pF, RL
500:
Units
VCC
3.3V r 0.3V
Min
Max
Min
Max
1.0
4.0
1.0
4.6
1.0
3.7
1.0
4.1
1.0
3.5
1.0
3.9
1.0
3.5
1.0
3.9
1.0
5.3
1.0
6.3
1.0
5.6
1.0
7.2
1.0
4.6
1.0
5.4
1.0
5.3
1.0
6.9
VCC
2.7V
1.5
5.6
1.5
6.3
1.5
5.5
1.5
5.5
1.5
5.4
1.5
6.1
1.5
5.1
1.5
5.4
ns
ns
ns
ns
ns
ns
1.0
1.0
ns
1.0
1.0
ns
Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Capacitance
Symbol
(Note 12)
Parameter
Conditions
CIN
Input Capacitance
VCC
0V, VI
CI/O
Input/Output Capacitance
VCC
3.0V, VO
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0V or VCC
0V or VCC
Typical
Units
pF
pF
74LVT162245 74LVTH162245
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Package Number BGA54A
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74LVT162245 74LVTH162245
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Package Number MS48A
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48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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74LVT162245 74LVTH162245 Low Voltage 16-Bit Transceiver with 3-STATE Outputs and 25: Series Resistors in
A Port Outputs