VHDL LAB REPORT

08-May-14

Indian Institute of Space Science and Technology

Department of Avionics

Project Report on
FPGA Implementation of a Restoring Algorithm
Pipelined Divider
VHDL LAB
LIJO P JOSE
SC12B091

VHDL LAB REPORT

08-May-14

Acknowledgement
I express my humble thanks and gratitude to our esteemed supervisor, Dr. Sheeba Rani,
for assigning this project and helping us to learn the concepts of VHDL and basics of
FPGA.

VHDL LAB REPORT

08-May-14

Algorithm for Restoring Division:

An n-bit positive divisor is loaded into register M and an n-bit positive dividend is
loaded into register Q at the start of the operation. Register A is set to 0. After the
division is complete, the n-bit quotient is in register Q and the remainder is in register
A. The required subtractions are facilitated by using 2's-complement arithmetic. The
extra bit position at the left end of both A and M accommodates the sign bit during
subtractions. The following algorithm performs restoring division.
The following is done n times:
Shift A and Q left one binary position.
2. Subtract M from A, and place the answer back in A.
3. If the sign of A is 1, set q0 to 0 and add M back to A (that is, restore A); otherwise,
set q0 to 1.
1.

Flow chart:

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08-May-14

Implementation Procedure:
Initial idea of implementation of the divider was to construct a basic module of 1 bit
restoring division and further that it could be extended to a pipelined version.
The VHDL implementation of the pipelined version started off with the creation of the
basic component i.e; 1 bit divider. This was implemented by following the C code
method:

S0 Z
for j 1 to k
if 2 S(j-1) 2 k d 0
q (k - j) 1
S j 2 S(j-1) 2 k d
else q (k - j) 0
S j 2 S(j-1)

After this sequence is totally executed a top level module called divider has been
created .The work of this module is just to create an array of dividers which in turn will
calculate each bit of the impending result.
The divider code has been made in such a way that a generic change in the size of
inputs can be easily made.
The latency in the first output was optimized by trial and error method of adding delay
to bit transfer from one basic divider component to another.
To give sustained inputs as numerator and denominator a ROM was utilized (using
IPcore) and a memory initiation file was later added to it.
The output bits are later converted using appropriate conversion function defined in the
code which can then be fed to LCD.

VHDL LAB REPORT

08-May-14

Simulation Results:
In MODELSIM

Initial Timing Analysis:

IN Quartus II

After this initial analysis the clock was forced to 100MHz.This corresponding change
has been stated in the next picture.

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RTL Schematic:

08-May-14

VHDL LAB REPORT

Internal Structure of one 1 bit restoring divider

State Diagram:

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VHDL LAB REPORT

08-May-14

Conclusion:
A pipelined divider has been implemented using Restoring Division Algorithm and has
been verified for its functionality both in MODELSIM simulations and on FPGA(using
Cyclone II).