Doc-1. Rtos

CHAPTER 1
INTRODUCTION
Reconfigurable System like FPGA platform has the potential to provide the
performance benefits of ASICs and the flexibility of processors. An FPGA is a
collection of programmable gates embedded in a flexible interconnect network that can
contain
hard or
soft
microprocessors. FPGAs combine the programmability of
processors with the performance of custom hardware. As FPGAs can provide a

balance between performance and
useful
flexibility, they becomes the primary source of
computation in many critical embedded systems.

FPGA based embedded system have become a platform for the implementation
of cryptographic algorithms, which needs large number of bit-level operations, and that
can be done efficiently on FPGA. The merit of our paper lies in the implementation of
cryptographic algorithm utilizing threads, run by an RTOS on FPGA systems, which is
quite challenging in this reconfigurable architecture domain. The usage of RTOS is
advantageous in many respects, as RTOS is an efficient tool to optimize the software
runtime as the code complexity grows, by distributing the tasks into multiple threads.
Better and safer synchronization and resource management are also major advantages
of an RTOS. As an RTOS, we have chosen Xilkernel and XTEA as our cryptographic
algorithm to be implemented, which is quite popular.
Our contribution in this paper can be briefed as follows
Establishing reliable communication between multiple FPGA devices is an essential
component for developing complex real time systems used for applications like real time
data acquisition and processing [1].
Our paper proposes the major issue that two threads running separately on each board
can communicate with each other via RS232 communication link.
The algorithm is implemented in hardware by introducing the concept of thread
execution by an RTOS and its hardware utilization proves that our implementation is
efficient.
Cryptography :
Cryptography is the practice and study of techniques for secure communication in the
presence of third parties (called adversaries).More generally, it is about constructing and
analyzing protocols that overcome the influence of adversaries and which are related to
various aspects in information security such as data confidentiality, data integrity,
authentication, and non-repudiation. Modern cryptography intersects the disciplines of
mathematics, computer science, and electrical engineering. Applications of cryptography
include ATM cards, computer passwords, and electronic commerce.
Cryptography prior to the modern age was effectively synonymous with encryption, the
conversion of information from a readable state to apparent nonsense. The originator of
an encrypted message shared the decoding technique needed to recover the original
information only with intended recipients, thereby precluding unwanted persons to do the
same. Since World War I and the advent of the computer, the methods used to carry out
cryptology have become increasingly complex and its application more widespread.
Modern cryptography is heavily based on mathematical theory and computer science
practice; cryptographic algorithms are designed around computational hardness
assumptions, making such algorithms hard to break in practice by any adversary. It is
theoretically possible to break such a system but it is infeasible to do so by any known
practical means. These schemes are therefore termed computationally secure; theoretical
advances, e.g., improvements in integer factorization algorithms, and faster computing
technology require these solutions to be continually adapted. There exist informationtheoretically secure schemes that provably cannot be broken even with unlimited
computing poweran example is the one-time padbut these schemes are more difficult
to implement than the best theoretically breakable but computationally secure
mechanisms.
Terminology :
Until modern times cryptography referred almost exclusively to encryption, which is the
process of converting ordinary information (called plaintext) into unintelligible text
(called ciphertext).Decryption is the reverse, in other words, moving from the
unintelligible ciphertext back to plaintext. A cipher (or cypher) is a pair of algorithms that
create the encryption and the reversing decryption. The detailed operation of a cipher is
controlled both by the algorithm and in each instance by a "key". This is a secret (ideally
known only to the communicants), usually a short string of characters, which is needed to
decrypt the ciphertext. A "cryptosystem" is the ordered list of elements of finite possible
plaintexts, finite possible cyphertexts, finite possible keys, and the encryption and
decryption algorithms which correspond to each key. Keys are important, as ciphers
without variable keys can be trivially broken with only the knowledge of the cipher used
and are therefore useless (or even counter-productive) for most purposes. Historically,
ciphers were often used directly for encryption or decryption without additional
procedures such as authentication or integrity checks.
In colloquial use, the term "code" is often used to mean any method of encryption or
concealment of meaning. However, in cryptography, code has a more specific meaning. It
means the replacement of a unit of plaintext (i.e., a meaningful word or phrase) with a
code word (for example, wallaby replaces attack at dawn). Codes are no longer used in
serious cryptographyexcept incidentally for such things as unit designations (e.g.,
Bronco Flight or Operation Overlord)since properly chosen ciphers are both more
practical and more secure than even the best codes and also are better adapted to
computers.
Cryptanalysis is the term used for the study of methods for obtaining the meaning of
encrypted information without access to the key normally required to do so; i.e., it is the
study of how to crack encryption algorithms or their implementations.
Some use the terms cryptography and cryptology interchangeably in English, while
others (including US military practice generally) use cryptography to refer specifically to
the use and practice of cryptographic techniques and cryptology to refer to the combined
study of cryptography and cryptanalysis.English is more flexible than several other
languages in which cryptology (done by cryptologists) is always used in the second sense
above. In the English Wikipedia the general term used for the entire field is cryptography
(done by cryptographers).
The study of characteristics of languages which have some application in cryptography
(or cryptology), i.e. frequency data, letter combinations, universal patterns, etc., is called
cryptolinguistics.
Modern cryptography:
The modern field of cryptography can be divided into several areas of study.
Symmetric-key cryptography:
Symmetric-key cryptography refers to encryption methods in which both the
sender and receiver share the same key (or, less commonly, in which their keys are
different, but related in an easily computable way). This was the only kind of encryption
publicly known until June 1976.
Symmetric key ciphers are implemented as either block ciphers or stream ciphers. A
block cipher enciphers input in blocks of plaintext as opposed to individual characters,
the input form used by a stream cipher.
The Data Encryption Standard (DES) and the Advanced Encryption Standard (AES) are
block cipher designs which have been designated cryptography standards by the US
government (though DES's designation was finally withdrawn after the AES was
adopted). Despite its deprecation as an official standard, DES (especially its stillapproved and much more secure triple-DES variant) remains quite popular; it is used
across a wide range of applications, from ATM encryption to e-mail privacy and secure
remote access. Many other block ciphers have been designed and released, with
considerable variation in quality. Many have been thoroughly broken, such as FEAL.
Stream ciphers, in contrast to the 'block' type, create an arbitrarily long stream of key
material, which is combined with the plaintext bit-by-bit or character-by-character,
somewhat like the one-time pad. In a stream cipher, the output stream is created based on
a hidden internal state which changes as the cipher operates. That internal state is initially
set up using the secret key material. RC4 is a widely used stream cipher. Block ciphers
can be used as stream ciphers;.
Cryptographic hash functions are a third type of cryptographic algorithm. They take a
message of any length as input, and output a short, fixed length hash which can be used
in (for example) a digital signature. For good hash functions, an attacker cannot find two
messages that produce the same hash. MD4 is a long-used hash function which is now
broken; MD5, a strengthened variant of MD4, is also widely used but broken in practice.
The U.S. National Security Agency developed the Secure Hash Algorithm series of MD5-
like hash functions: SHA-0 was a flawed algorithm that the agency withdrew; SHA-1 is
widely deployed and more secure than MD5, but cryptanalysts have identified attacks
against it; the SHA-2 family improves on SHA-1, but it isn't yet widely deployed, and the
U.S. standards authority thought it "prudent" from a security perspective to develop a
new standard to "significantly improve the robustness of NIST's overall hash algorithm
toolkit." Thus, a hash function design competition was meant to select a new U.S.
national standard, to be called SHA-3, by 2012. The competition ended on October 2,
2012 when the NIST announced that Keccak would be the new SHA-3 hash algorithm.
Message authentication codes (MACs) are much like cryptographic hash functions,
except that a secret key can be used to authenticate the hash value upon receipt.
Public-key cryptography:
Symmetric-key cryptosystems use the same key for encryption and decryption of
a message, though a message or group of messages may have a different key than others.
A significant disadvantage of symmetric ciphers is the key management necessary to use
them securely. Each distinct pair of communicating parties must, ideally, share a different
key, and perhaps each ciphertext exchanged as well. The number of keys required
increases as the square of the number of network members, which very quickly requires
complex key management schemes to keep them all straight and secret. The difficulty of
securely establishing a secret key between two communicating parties, when a secure
channel does not already exist between them, also presents a chicken-and-egg problem
which is a considerable practical obstacle for cryptography users in the real world.
In a groundbreaking 1976 paper, Whitfield Diffie and Martin Hellman proposed
the notion of public-key (also, more generally, called asymmetric key) cryptography in
which two different but mathematically related keys are useda public key and a private
key. A public key system is so constructed that calculation of one key (the 'private key') is
computationally infeasible from the other (the 'public key'), even though they are
necessarily related. Instead, both keys are generated secretly, as an interrelated pair. The
historian David Kahn described public-key cryptography as "the most revolutionary new
concept in the field since polyalphabetic substitution emerged in the Renaissance".
In public-key cryptosystems, the public key may be freely distributed, while its
paired private key must remain secret. In a public-key encryption system, the public key
is used for encryption, while the private or secret key is used for decryption. While Diffie
and Hellman could not find such a system, they showed that public-key cryptography was
indeed possible by presenting the DiffieHellman key exchange protocol, a solution that
is now widely used in secure communications to allow two parties to secretly agree on a
shared encryption key.Diffie and Hellman's publication sparked widespread academic
efforts in finding a practical public-key encryption system. This race was finally won in
1978 by Ronald Rivest, Adi Shamir, and Len Adleman, whose solution has since become
known as the RSA algorithm.The DiffieHellman and RSA algorithms, in addition to
being the first publicly known examples of high quality public-key algorithms, have been
among the most widely used. Others include the CramerShoup cryptosystem, ElGamal
encryption, and various elliptic curve techniques. See Category:Asymmetric-key
cryptosystems.To much surprise, a document published in 1997 by the Government
Communications Headquarters (GCHQ), a British intelligence organization, revealed that
cryptographers at GCHQ had anticipated several academic developments.Reportedly,
around 1970, James H. Ellis had conceived the principles of asymmetric key
cryptography. In 1973, Clifford Cocks invented a solution that essentially resembles the
RSA algorithm. And in 1974, Malcolm J. Williamson is claimed to have developed the
Diffie-Hellman key exchange .
Public-key cryptography can also be used for implementing digital signature
schemes. A digital signature is reminiscent of an ordinary signature; they both have the
characteristic of being easy for a user to produce, but difficult for anyone else to forge.
Digital signatures can also be permanently tied to the content of the message being
signed; they cannot then be 'moved' from one document to another, for any attempt will
be detectable. In digital signature schemes, there are two algorithms: one for signing, in
which a secret key is used to process the message (or a hash of the message, or both), and
one for verification, in which the matching public key is used with the message to check
the validity of the signature. RSA and DSA are two of the most popular digital signature
schemes. Digital signatures are central to the operation of public key infrastructures and
many network security schemes.Public-key algorithms are most often based on the
computational complexity of "hard" problems, often from number theory. For example,
the hardness of RSA is related to the integer factorization problem, while DiffieHellman
and DSA are related to the discrete logarithm problem.
TINY ENCYPTION ALGORITHM:

The Encryption Algorithm is a block cipher notable for its simplicity of description
and implementation, typically a few lines of code. It was designed by David
Wheeler and Roger Needham of the Cambridge; it was first presented at the Fast
Software Encryption workshop in Leuven in 1994.
This Algorithm operates on 64-bit blocks and uses a 128-bit key. It has a Feistel
structure with a suggested 64 rounds, typically implemented in pairs termed

cycles. It has an extremely simple key schedule, mixing all of the key material in
exactly the same way for each cycle. Different multiples of a magic constant are
used to prevent simple attacks based on the symmetry of the rounds. The magic
constant, 2654435769 or 9E3779B916 is chosen to be 232/, where is the golden

ratio.
Encryption Routine:
The inputs to the encryption algorithm are a plaintext block and a key K .The
plaintext is
P = (Left[0], Right[0]) and the cipher text is C = (Left[64],
Right[64]). The plaintext block is split into two halves, Left[0] and Right[0]. Each
half is used to encrypt the other half over 32 rounds of processing and then
combine to produce the cipher text block. Each round i has inputs Left[i-1] and
Right[i-1], derived from the previous round, as well as a sub key K[i] derived from
the 128 bit overall K.
The sub keys K[i] are different from K and from each other. The constant delta =
, is derived from the golden number ratio to ensure that the
sub keys are distinct and its precise value has no cryptographic significance. The
round function differs slightly from a classical Fiestel cipher structure in that
integer addition modulo 2 is used instead of exclusive-or as the combining
operators.
Decryption Routine:
Decryption is essentially the same as the encryption process; in the decode
routine the cipher text is used as input to the algorithm, but the sub keys K[i] are
used in the reverse order.The intermediate value of the decryption process is equal
to the corresponding value of the encryption process with the two halves of the
value swapped.
Flow chart for Decryption routine
SOFT CORE PROCESSOR IMPLEMENTATION :

A soft microprocessor (also called softcore microprocessor or a soft processor) is
a microprocessor core that can be wholly implemented using logic synthesis. It can be
implemented via different semiconductor devices containing programmable logic (e.g.,
ASIC, FPGA, CPLD), including both high-end and commodity variations.
While many people put exactly one soft microprocessor on a FPGA, a sufficiently
large FPGA can hold two or more soft microprocessors, resulting in a multi-core
processor. The number of soft processors on a single FPGA is only limited by the size of
the FPGA.Some people have put dozens or hundreds of soft microprocessors on a single
FPGA.
The MicroBlaze is a soft processor core designed for Xilinx FPGAs from Xilinx.
As a soft-core processor, MicroBlaze is implemented entirely in the general-purpose
memory and logic fabric of Xilinx FPGAs.
MICROBLAZE OVERVIEW:
In terms of its instruction-set architecture, MicroBlaze is very similar to the
RISC-based DLX architecture described in a popular computer architecture book by
Patterson and Hennessy. With few exceptions, the MicroBlaze can issue a new instruction
every cycle, maintaining single-cycle throughput under most circumstances.
The MicroBlaze has a versatile interconnect system to support a variety of
embedded applications. MicroBlaze's primary I/O bus, the CoreConnect PLB bus, is a
traditional system-memory mapped transaction bus with master/slave capability. A newer
version of the MicroBlaze, supported in both Spartan-6 and Virtex-6 implementations, as
well as the 7-Series, supports the AXI specification. The majority of vendor-supplied and
third-party IP interface to PLB directly (or through an PLB to OPB bus bridge.) For
access to local-memory (FPGA BRAM), MicroBlaze uses a dedicated LMB bus, which
reduces loading on the other buses. User-defined coprocessors are supported through a
dedicated FIFO-style connection called FSL (Fast Simplex Link). The coprocessor(s)
interface can accelerate computationally intensive algorithms by offloading parts or the
entirety of the computation to a user-designed hardware module.
Many aspects of the MicroBlaze can be user configured: cache size, pipeline
depth (3-stage or 5-stage), embedded peripherals, memory management unit, and businterfaces can be customized. The area-optimized version of MicroBlaze, which uses a 3stage pipeline, sacrifices clock-frequency for reduced logic-area. The performanceoptimized version expands the execution-pipeline to 5-stages, allowing top speeds of 210
MHz (*on Virtex-5 FPGA family.) Also, key processor instructions which are rarely used
but more expensive to implement in hardware can be selectively added/removed (i.e.
multiply, divide, and floating-point ops.) This customization enables a developer to make
the appropriate design tradeoffs for a specific set of host hardware and application
software requirements.
With the memory management unit, MicroBlaze is capable of hosting operating
systems requiring hardware-based paging and protection, such as the Linux kernel.
Otherwise it is limited to operating systems with a simplified protection and virtual
memory-model: e.g. FreeRTOS or Linux without MMU support. MicroBlaze's overall
throughput is substantially less than a comparable hardened CPU-core (such as the
PowerPC440 in the Virtex-5.)
EDK(Embedded development kit):
Xilinx's EDK (Embedded Development Kit) is the development package for
building MicroBlaze (and PowerPC) embedded processor systems in Xilinx FPGAs.
Hosted in the Eclipse IDE, the project manager consists of two separate environments:
XPS and SDK.
Designers use XPS (Xilinx Platform Studio) to configure and build the hardware
specification of their embedded system (processor core, memory-controller, I/O
peripherals, etc.) The XPS converts the designer's platform specification into a
synthesizeable RTL description (Verilog or VHDL), and writes a set of scripts to
automate the implementation of the embedded system (from RTL to the bitstream-file.)
For the MicroBlaze core, the EDK normally generates an encrypted (non humanreadable) netlist, but the processor description (written in VHDL) can be purchased from
Xilinx.
The SDK handles the software that will execute on the embedded system.
Powered by the GNU toolchain (GNU Compiler Collection, GNU Debugger), the SDK
enables programmers to write, compile, and debug C/C++ applications for their
embedded system. Xilinx includes a cycle-accurate instruction set simulator (ISS), giving
programmers the choice of testing their software in simulation, or using a suitable FPGAboard to download and execute on the actual system.
MicroBlaze
Designer
Xilinx
Bits
32
Version
8.40.b
Design
RISC
Encoding
Fixed
Endianness
Big/Little
Open
No
Registers
32 x 32 bits
Chapter-2
FPGA and TOOL FLOW
2.1 FPGA Design Considerations

FPGA demonstrates good performance and logic capacity by exploiting
parallelism. At present single FPGA platform can play multi-functions, including control,
filter and system.
FPGA design flow is a three-step process consisting of design
entry, implementation, and verification stages, as shown in Fig 3.1.The full design flow is
an iterative process of entering, implementing, and verifying the design until it is correct
and complete. The key advantage of VHDL when used for systems design is that it allows
the behavior of the required system to be described (modeled) and verified (simulated)
before Synthesis tools translate the design into real hardware (gates and wires). HDL
describes hardware behavior. There are main differences between traditional
programming languages and HDL.Traditional languages are a sequential process whereas
HDL is a parallel process.

HDL runs forever whereas traditional programming language will only run if directed.
Fig (2.1): FPGA design flow
2.1.1 VHDL
VHDL (VHSIC hardware description language; VHSIC: very-highspeed integrated circuit) is a hardware description language used in electronic design
automation to describe digital and mixed-signal systems such as field-programmable gate

arrays and integrated circuits. The structural and dataflow descriptions show a concurrent
behavior. That is, all statements are executed concurrently, and the order of the statements
is not relevant. On the other hand, behavioral descriptions are executed sequentially in
processes, procedures and functions in VHDL. The behavioral descriptions resemble
high-level programming languages.
VHDL allows a mixture of various levels of design entry abstraction. Precision RTL
Synthesis Synthesizes will accept all levels of abstraction, and minimize the amount of
logic needed, resulting in a final net list description in the technology of your choice. The
Top-Down Design Flow is shown in Figure 2.3
Fig (2.2): Top-Down Design Flow with Precision RTL Synthesis
2.1.2 VHDL and Synthesis

VHDL is fully simulatable, but not fully synthesizable. There are several
VHDL constructs that do not have valid representation in a digital circuit. Other
constructs do, in theory, have a representation in a digital circuit, but cannot be
reproduced with guaranteed accuracy. Delay time modeling in VHDL is an example.

State-of-the-art synthesis algorithms can optimize Register Transfer Level (RTL) circuit
descriptions and target a specific technology. Scheduling and allocation algorithms,
which perform circuit optimization at a very high and abstract level, are not yet robust
enough for general circuit applications. Therefore, the result of synthesizing a VHDL
description depends on the style of VHDL that is used.
2.1.3 Evolution of Programmable Logic Devices

The first device developed later specifically for implementing logic circuits was
the Field-Programmable Logic Array (FPLA), or simply PLA for short. A PLA consists of
two levels of logic gates: a programmable wired AND-plane followed by a
programmable wired OR-plane. A PLA is structured so that any of its inputs (or their
complements) can be ANDed together in the AND-plane; each AND-plane output can
thus correspond to any product term of the inputs. Similarly, each OR-plane output can be
configured to produce the logical sum of any of the AND-plane outputs. With this
structure, PLAs are well-suited for implementing logic functions in sum-of-products
form.
Fig (2.3) Structure of a PAL
Field-Programmable Gate Arrays (FPGAs). Like MPGAs, FPGAs comprise an

array of uncommitted circuit elements, called logic blocks, and interconnect resources,
but FPGA configuration is performed through programming by the end user. An
illustration of a typical FPGA architecture appears in Figure 2.4. As the only type of FPD
that supports very high logic capacity, FPGAs have been responsible for a major shift in
the way digital circuits are designed.
Fig (2.4): structure of an FPGA
2.1.4 Xilinx SRAM-based FPGAs

The basic structure of Xilinx FPGAs is array-based, meaning that each chip
comprises a two dimensional array of logic blocks that can be interconnected via
horizontal and vertical routing channels. An illustration of this type of architecture was
shown in Figure 5.4.
Fig (2.5):- Xilinx XC4000 Configurable Logic Block (CLB).

The XC4000 features a logic block (called a Configurable Logic Block
(CLB) by Xilinx) that is based on look-up tables (LUTs). A LUT is a small one bit wide
memory array, where the address lines for the memory are inputs of the logic block and
the one bit output from the memory is the LUT output. A LUT with K inputs would then
correspond to a 2K x 1 bit memory, and can realize any logic function of its K inputs by
programming the logic functions truth table directly into the memory. The XC4000 CLB
contains three separate LUTs, in the configuration shown in Figure 2.5 There are two 4input LUTS that are fed by CLB inputs, and the third LUT can be used in combination
with the other two. This arrangement allows the CLB to implement a wide range of logic
functions of up to nine inputs, two separate functions of four inputs or other possibilities.
Each CLB also contains two flip-flops. A new version of this family, the 4000E, has the
additional feature that the RAM can be configured as a dual port RAM with a single write
and two read ports. In the 4000E, RAM blocks can be synchronous RAM. Also, each
XC4000 chip includes very wide AND-planes around the periphery of the logic block
array to facilitate implementing circuit blocks such as wide decoders. Besides logic, the
other key feature that characterizes an FPGA is its interconnecting structure.
An important point worth noting about the Xilinx interconnect is that signals
must pass through switches to reach one CLB from another, and the total number of
switches traversed depends on the particular set of wire segments used. Thus, speedperformance of an implemented circuit depends in part on how the wire segments are
allocated to individual signals by CAD tool.
2.2 Spartan-3E FPGA Family

The five-member family offers densities ranging from 100,000 to 1.6 million
system gates. These Spartan-3E enhancements, combined with advanced 90 nm process
technology, deliver more functionality and bandwidth per dollar than was previously
possible, setting new standards in the programmable logic industry. Because of their
exceptionally low cost, Spartan-3E FPGAs are ideally suited to a wide range of consumer
electronics
applications,
including
broadband
access,
home
networking,
display/projection, and digital television equipment.The Spartan-3E family is a superior

alternative to mask programmed ASICs. FPGAs avoid the high initial cost, the lengthy
development cycles, and the inherent inflexibility of conventional ASICs.
2.2.1 Spartan -3E Architectural Overview

The Spartan-3E family architecture consists of five fundamental programmable
functional elements:
Configurable Logic Blocks (CLBs): contain flexible Look-Up Tables (LUTs) that
implement logic plus storage elements used as flip-flops or latches. CLBs perform a wide
variety of logical functions as well as store data.
Input/output Blocks (IOBs): control the flow of data between the I/O pins and the
internal logic of the device. Each IOB supports bidirectional data flow plus 3-state
operation. It supports a variety of signal standards, including four high-performance
differential standards. Double Data-Rate (DDR) registers are included.
Block RAM: provides data storage in the form of 18-Kbit dual-port blocks.
Digital Clock Manager (DCM): Blocks provide self-calibrating, fully digital solutions
for distributing, delaying, multiplying, dividing, and phase-shifting clock signals.
A ring of IOBs surrounds a regular array of CLBs. Each device has two columns of block
RAM except for the XC3S100E, which has one column. Each RAM column consists of
several 18-Kbit RAM blocks. Each block RAM is associated with a dedicated multiplier.
The DCMs are positioned in the center with two at the top and two at the bottom of the
device. The XC3S100E has only one DCM at the top and bottom, while the XC3S1200E
and XC3S1600E add two DCMs in the middle of the left and right sides.
Fig (2.6): Spartan-3E Family Architecture
2.2.2 Spartan -3E Configuration

Spartan-3E FPGAs are programmed by loading configuration data into robust,
reprogrammable, static CMOS configuration latches (CCLs) that collectively control all
functional elements and routing resources. The FPGAs configuration data is stored
externally in a PROM or some other non-volatile medium, either on or off the board.
After applying power, the configuration data is written to the FPGA using any of seven
different modes
Master Serial from a Xilinx Platform Flash PROM.
Serial Peripheral Interface (SPI) from an industry-standard SPI serial Flash.
Slave Serial, typically downloaded from a processor.
Slave Parallel, typically downloaded from a processor.
Boundary Scan (JTAG), typically downloaded from a processor or system tester.
The Spartan-3E FPGA Select I/O interface supports many popular single-ended
and differential standards.Spartan-3E FPGAs support the following single-ended
standards:
3.3V low-voltage TTL (LVTTL)
Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V, 1.5V, or 1.2V.
3V PCI at 33 MHz, and in some devices, 66 MHz.
Spartan-3E FPGAs support the following differential standards:
LVDS.
Bus LVDS.
2.5V LVPECL inputs.
2.3 FPGA Design and Programming Tool Flow
Fig (2.7): Xilinx Design Flow

The standard design flow comprises the following steps:
Design Entry and Synthesis: In this step of the design flow, design is created using a, a
hardware description language (HDL) for text-based entry. Xilinx Synthesis Technology
(XST) GUI can be used to synthesize the HDL file into an NGC file.
Design Implementation: By implementing to a specific Xilinx architecture, the logical
design file format, such as EDIF, that is created in the design entry and synthesis stage is
converted into a physical file format. The physical information is contained in the native
circuit description (NCD) file for FPGAs Then bit stream file is created from these files
and optionally a PROM or EPROM is programmed for subsequent programming of
Xilinx device.
Design Verification: Using a gate-level simulator or cable, it is ensured that the design
meets timing requirements and functions properly.
Fig
(2.8):
Xilinx
Spartan
3e
FPGA Kit
To define the behavior of the FPGA, the user provides a hardware description
language (HDL) or a schematic design. The HDL form is more suited to work with large
structures because it's possible to just specify them numerically rather than having to
draw every piece by hand. However, schematic entry can allow for easier visualization of
a design. Then, using an electronic design automation tool, a technology-mapped net list
is generated. The net list can then be fitted to the actual FPGA architecture using a
process called place-and-route, usually performed by the FPGA Companys proprietary
place-and-route software. The user will validate the map, place and route results via
timing analysis, simulation, and other verification methodologies. Once the design and
validation process is complete, the binary file generated (also using the FPGA company's
proprietary software) is used to (re)configure the FPGA.Going from schematic/HDL
source files to actual configuration: The source files are fed to a software suite from the
FPGA vendor that through different steps will produce a file. This file is then transferred
to the FPGA via a serial interface (JTAG).Initially the RTL description in VHDL is
simulated by creating test benches to simulate the system and observe results. Then, after
the synthesis engine has mapped the design to a net list, the net list is translated to a gate
level description where simulation is repeated to confirm the synthesis proceeded without
errors. Finally the design is laid out in the FPGA at which point propagation delays can
be added and the simulation run again with these values back-annotated onto the net list.
2.5.3 Design Flow

The tools design flow merges easily with any standard FPGA design flow that
uses a standard HDL synthesis tool and the ISE 9.2i implementation tools.
Fig (2. 19): ChipScope Pro Tools Design Flow

2.6 FPGA DESIGN FLOW
This
is part of chapter deals with the implementation flow specifying the
significance of various properties, reports obtained and simulation waveforms of

architectures developed to implement.
2.6.1 FPGA Design flow:
The various steps involved in the design flow are as follows:
1) The design
2] Processes and properties
3] Synthesize options
4] Write Timing Constraints
5) Timing simulation of the design after post PAR.
6) Static timing analysis.
7) Configuring the device by bit generation.
2.6.1.1 Design entry:
The first step in implementing the design is to create the HDL code based on
design criteria. To support these instantiations we need to include UNISIM library and
compile all design libraries before performing the functional simulation. The constraints
(timing and area constraints) can also be included during the design entry. Xilinx accepts
the constraints in the form of user constraint (UCF) file.
2.6.1.2 Functional Simulation:
This step deals with the verification of the functionality of the written source
code. ISE provides its own ISE simulator and also allows for the integration with other
tools such as Modelsim. This project uses Modelsim for the ce. Functional simulation can
take place at the earliest stages of the design flow. Because timing information for the
implemented design is not available at this stage, the simulator tests the logic in the
design using unit delays.
2.6.1.3 Synthesizing and Optimizing:
In this stage behavioral information in the HDL file is translated into a fed into the
Xilinx software program called NGDBuild, which produces a logical native generic
database (NGD) file.
2.6.1.4 Design implementation
In this stage, The MAP program maps a logical design to a Xilinx FPGA. The
input to MAP is an NGD file, which is generated using the NGDBuild Xilinx primitives.
The NGD file also contains any number of NMC (macro library) files, each of which
contains the definition of a physical macro. MAP first performs a logical DRC (Design
Rule Check) on the design in the NGD file. MAP then maps the design logic to the
components (logic cells, I/O cells, and other components) in the target Xilinx FPGA.
The output from MAP is an NCD (Native Circuit Description) file, and PCF (Physical
constraint file).
NCD (Native Circuit Description) filea physical description of the design in terms of
the components in the target Xilinx device.
PCF (Physical Circuit Description (NCD) file with the MAP program, place and route
that design file using PAR. PAR accepts a mapped NCD file as input, places and
routes the design, and outputs an NCD file to be used by the bit stream generator
(BitGen).
The PAR placer executes multiple phases of the placer. PAR writes the NCD after all the
placer phases are complete. During placement, PAR places components procedure
for a solution that routes the design to completion and meets timing constraints.
Once the design is fully routed, PAR writes an NCD file, which can be analyzed
against timing. PAR writes a new NCD as the routing improves throughout the
router phases.
2.6.1.5 Timing simulation after post PAR:
Timing simulation at this stage verifies that the design runs at the desired speed
for the device under worst-case conditions. This process is performed after the design. It
can also determine whether or not the design contains set-up or hold violations. In most
of the designs the same test bench can be used to simulate at this stage.
2.6.1.6 Static timing analysis:
Static timing analysis is best for quick timing checks of a design after it is placed
and routed. It also allows you to determine path delays in your design. Following are the
two major goals of static timing analysis:
Timing verification:-This is verifying that the design meets your timing constraints.
Reporting:-This is enumerating input constraint violations and placing them into an

accessible TRACE are .ncd file and .pcf from PAR .and the output file is a .twr
file.
2.6.1.7 Configuring the device by BitGen:
After the design is completely routed, it is necessary to configure the device so
that it the configuration information from the NCD file that defines the internal logic and
interconnections of the FPGA, plus device-specific information from other files
associated with the target device. The binary data in the BIT file is then downloaded into
the FPGAs memory cells, or it is used to create a PROM file.
2.6.2 Processes and properties:
Processes and properties enable the interaction of our design with the
functionality available in the ISE suite of tools.
2.6.2.1 Processes
Processes are the functions listed hierarchically in the Processes window. They
perform functions from the start to the end of the design flow.
2.6.2.2 Properties
Process properties are accessible from the right-click menu for select processes.
They enable us to customize the parameters used by the process.
Process properties are set at synthesis and implementation phase.
2.6.3 Synthesize options:
The following properties apply to the Synthesize properties .using the Xilinx
Synthesis Technology (XST) synthesis tool.
the drop-down list.
Speed:-Optimizes the design for speed by reducing the levels of logic.
Area:-property is set to Speed.
2.6.3.1 Optimization Effort
Specifies the synthesis optimization effort level.
Select an option from the drop-down list.
Normal:-Optimizes the design using minimization and algebraic factoring algorithms.
High:-Performs additional optimizations that are tuned to the selected device
Normal.:- This project aims at Timing performance and was selected HIGH effort level.
2.6.3.2 Power Reduction

When set to is set to No (checkbox is blank).
2.6.3.3 Use Synthesis Constraints File
Specifies whether or not to use the constraints file entered in the previous
property. By default, this constraints file is used (property checkbox is checked).
2.6.3.4 Keep Hierarchy
Specifies whether or not the corresponding design unit should be preserved and
not merged with the rest of the design. You can specify Yes, No and Soft
property from no to yes gave me almost double the speed.
2.6.3.5 Global Optimization Goal
Specifies the global timing optimization goal
Select
Optimizes the maximum delay from input pad to clock, either for a specific clock
or for an entire design.
Offset Out After
Optimizes the maximum delay from clock to output pad, either for a specific
is set to AllClockNets.
2.6.3.6 Generate RTL Schematic
Generates a pre-optimization RTL schematic of the design. Values for this
property are Yes, No, and only. Only stops the synthesis process before optimization,
after the RTL schematic has been generated.
The default value is yes.
2.6.3.7 Read Cores
Specifies whether or not black box core are read for timing and area estimation
(checkbox is blank), cores are not read.
By default, this property is set to True (checkbox is checked).
2.6.4 Write Timing Constraints (FPGA only)
Specifies whether or not to place timing constraints in the NGC file. The timing
constraints in the NGC file will be used during place and route, as well as synthesis
optimization.
By default, this property is set to False (checkbox is blank).
2.6.4 .1 Slice Utilization Ratio

Specifies resource management by entering -1 here.
2.6.4.2 LUT-FF Pairs Utilization Ratio
Specifies the area size (in %) that XST will not exceed during timing
optimization. If the resource management by entering -1 here.
2.6.4.3 BRAM Utilization Ratio
Specifies the number of BRAM blocks (in %) that XST will not exceed during
synthesis. The default percentage is 100%. You can disable automatic BRAM resource
management by entering -1 here.
2.6.5 Implementation options:
2.6.5.1 Map Properties:
2.6.5.2 Perform Timing-Driven Packing and Placement
Specifies whether or not to give priority to timing critical paths during packing in
the Map Process. User-generated timing constraints are used to result is a completely
placed design, and the design is ready for routing.
If Timing-Driven Packing and Placement is selected in the absence of user timing
constraints, the tools will automatically generate and dynamically adjust timing
constraints for all internal clocks. This feature is referred to as achieve. Instead it is a
balance of performance between all clocks in the design.
By default, this property is set to False (checkbox is blank).
This project aims at speed and this option is selected.
2.6.5.3 Map Effort Level
Note: Available only when Perform Timing-Driven Packing and Placement is set
to True (checkbox is checked).
Specifies the effort level to apply to the Map process. The effort level controls the
amount of time used for packing and placement by selecting a more or less CPUintensive algorithm for placement.
Select an
Gives the longest run time with the best mapping results. Appropriate for a more complex
design.
By default, this property is set to Medium.
As this project is a complex design the option high is selected.

2.6.5.4 Extra Effort
Map is applied. Normal Runs until timing constraints are met unless they are
found to be impossible to meet. This option focuses on meeting timing constraints.
constraints.
By default, this property is set to none.
This project has a timing constraint of 100 ns; to meet this option Normal is
selected.
2.6.6 Combinatorial Logic Optimization
Specifies whether or not to run a process that revisits the combinatorial design.
This project aims to meet timing constraint and this option is selected.
2.6.7 Optimization Strategy (Cover Mode)
Specifies the criteria used during the "cover" phase of MAP. In the "cover" phase, MAP
assigns the logic to CLB function generators (LUTs). Select an option from the
drop-down list.
Area :Select Area to make reducing the number of LUTs (and therefore the number of
CLBs) the highest priority.
Speed: Select Speed to make reducing the number of levels of LUTS (the number of
LUTs a path passes through) the highest priority. This setting makes it the area
setting), and in some cases the increase may be large.
Balanced:Select Balanced to balance two priorities; reducing the number of LUTs and
reducing the number of levels of LUTs. The Balanced option produces results
optimization.:
By default, this property is set to Area.
To meet timing constraints this project selected the option of speed.
2.6.8 PAR properties
2.6.8.1 Place and Route Effort Level (Overall)
Specifies CPU-intensive algorithm for placement and routing. You can set the
overall level from Standard (fastest run time) to High (best results).
By default, this property is set at Standard.
To meet the timing constraint HIGH is selected for this project.
Chapter-3
BLOCK DIAGRAM
Fig- Communication between two fpgas using RTOS

The main theme of the project is to implement Real time
Communication
between two FPGAs for cryptographic applications. Data from FPGA 1 is not directly
transmitted to the FPGA-2 rather than that we are applying cryptographic mechanism .
According to cryptography ,the input data is being transmitted from the
transmitter to receiver by converting the text into a specific format which cannot be read
by the unauthorized (third person) person. This text is called as cipher text. The process
of transforming the plain text into cipher text is called as encryption. This cipher text is
transmitted to the receiver end where the cipher text is again retransformed back to plain
text. This process is called as Decryption.
In this project we are implementing this cryptography between two configurable
devices(FPGAs) for effective real time communication. Presently FPGAs
are
considered as a major platform for high performance embedded applications as it

provides the opportunity for reconfiguration as well as good clock speed and design
resources. In present day application scenarios most embedded systems have real-time
requirements that demand the use of Real-time operating systems (RTOS), which creates
a suitable environment for real time applications to be designed and expanded easily. In
an RTOS the design process is simplified by splitting the application code into
separate tasks and then the scheduler executes them according to a specific schedule,
meeting the real-time deadline.
The merit of our paper lies in the implementation of cryptographic algorithm
utilizing threads, run by an RTOS on FPGA systems, which is quite challenging in
this reconfigurable architecture domain. The usage ofRTOS is advantageous in many
respects, as RTOS is an efficient tool to optimize the software runtime as the code
complexity grows, by distributing the tasks into multiple threads. Better and safer
synchronization and resource management are also major advantages of an RTOS. As an
RTOS, we have chosen Xilkernel.
This work is implemented using the Xilinx EDK 13.2 (version) and Xilinx
Spartan 3E FPGA prototyping board has been used for the hardware implementation and
testing. A soft core 32-bit RISC processor Micro Blaze has been used as a CPU for this
embedded computing unit and all the required soft core peripherals are UART 1 (used for
RS232 DCE (Data Circuit-Terminal Equipment) port), UART 2(used for RS232 DTE
(Data Terminal Equipment) port). The blocks used to build up the FPGA based embedded
computing unit is shown in Fig. 2.
Release 13.2 - xst O.61xd (nt)

Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.27 secs
--> Parameter xsthdpdir set to xst
--> Reading design: system_top_top.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT
===============================================================
==========
*
Synthesis Options Summary
*
===============================================================
==========
---- Source Parameters
Input File Name
: "system_top_top.prj"
Input Format
: mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name
: "system_top_top"
Output Format
Target Device
: NGC
: xc3s500e-4-fg320
---- Source Options

Top Module Name
: system_top_top
Automatic FSM Extraction
: YES
FSM Encoding Algorithm
: Auto
Safe Implementation
: No
FSM Style
: LUT
RAM Extraction
: Yes
RAM Style
: Auto
ROM Extraction
: Yes
Mux Style
: Auto
Decoder Extraction
: YES
Priority Encoder Extraction
: Yes
Shift Register Extraction
: YES
Logical Shifter Extraction
: YES
XOR Collapsing
: YES
ROM Style
: Auto
Mux Extraction
: Yes
Resource Sharing
: YES
Asynchronous To Synchronous
: NO
Multiplier Style
: Auto
Automatic Register Balancing
: No
---- Target Options
Add IO Buffers
: YES
Global Maximum Fanout
: 500
Add Generic Clock Buffer(BUFG) : 24
Register Duplication
: YES
Slice Packing
: YES
Optimize Instantiated Primitives : NO
Use Clock Enable
: Yes
Use Synchronous Set
: Yes
Use Synchronous Reset
: Yes
Pack IO Registers into IOBs
: Auto
Equivalent register Removal
: YES
---- General Options
Optimization Goal
Optimization Effort
Keep Hierarchy
Netlist Hierarchy
RTL Output
Global Optimization
Read Cores
: Speed
:1
: No
: As_Optimized
: Yes
: AllClockNets
: YES
Write Timing Constraints

: NO
Cross Clock Analysis
: NO
Hierarchy Separator
:/
Bus Delimiter
: <>
Case Specifier
: Maintain
Slice Utilization Ratio
: 100
BRAM Utilization Ratio
: 100
Verilog 2001
: YES
Auto BRAM Packing
: NO
Slice Utilization Ratio Delta
:5
===============================================================
==========
===============================================================
==========
*
HDL Compilation
*
===============================================================
==========
Compiling vhdl file "E:/Fm39_kernel_project/top_module/system_top/hdl/system_top.vhd" in Library work.
Entity <system_top> compiled.
Entity <system_top> (Architecture <STRUCTURE>) compiled.
Compiling vhdl file "E:/Fm39_kernel_project/top_module/system_top/system_top_top.vhd" in Library work.
Entity <system_top_top> compiled.
Entity <system_top_top> (Architecture <STRUCTURE>) compiled.
===============================================================
==========
*
Design Hierarchy Analysis
*
===============================================================
==========
Analyzing hierarchy for entity <system_top_top> in library <work> (architecture
<STRUCTURE>).
===============================================================
==========
*
HDL Analysis
*
===============================================================
==========
Analyzing Entity <system_top_top> in library <work> (Architecture <STRUCTURE>).
Entity <system_top_top> analyzed. Unit <system_top_top> generated.
===============================================================
==========
*
HDL Synthesis
*
===============================================================
==========
Performing bidirectional port resolution...
Synthesizing Unit <system_top_top>.
Related source file is "E:/Fm39_kernel_project/top_module/system_top/system_top_top.vhd".
Unit <system_top_top> synthesized.
===============================================================
==========
HDL Synthesis Report
Found no macro
===============================================================
==========
===============================================================
==========
*
Advanced HDL Synthesis
*
===============================================================
==========
Reading core <system_top.ngc>.
Reading core <microblaze_0_wrapper.ngc>.
Reading core <mb_plb_wrapper.ngc>.
Reading core <ilmb_wrapper.ngc>.
Reading core <dlmb_wrapper.ngc>.
Reading core <dlmb_cntlr_wrapper.ngc>.
Reading core <ilmb_cntlr_wrapper.ngc>.
Reading core <lmb_bram_wrapper.ngc>.
Reading core <rs232_dte_wrapper.ngc>.
Reading core <rs232_dce_wrapper.ngc>.
Reading core <leds_8bit_wrapper.ngc>.
Reading core <flash_wrapper.ngc>.
Reading core <ddr_sdram_wrapper.ngc>.
Reading core <xps_timer_0_wrapper.ngc>.
Reading core <clock_generator_0_wrapper.ngc>.
Reading core <mdm_0_wrapper.ngc>.
Reading core <proc_sys_reset_0_wrapper.ngc>.
Reading core <xps_intc_0_wrapper.ngc>.

Loading core <microblaze_0_wrapper> for timing and area information for instance
<microblaze_0>.
Loading core <mb_plb_wrapper> for timing and area information for instance <mb_plb>.
Loading core <ilmb_wrapper> for timing and area information for instance <ilmb>.
Loading core <dlmb_wrapper> for timing and area information for instance <dlmb>.
Loading core <dlmb_cntlr_wrapper> for timing and area information for instance
<dlmb_cntlr>.
Loading core <ilmb_cntlr_wrapper> for timing and area information for instance
<ilmb_cntlr>.
Loading core <lmb_bram_wrapper> for timing and area information for instance
<lmb_bram>.
Loading core <rs232_dte_wrapper> for timing and area information for instance
<RS232_DTE>.
Loading core <rs232_dce_wrapper> for timing and area information for instance
<RS232_DCE>.
Loading core <leds_8bit_wrapper> for timing and area information for instance
<LEDs_8Bit>.
Loading core <flash_wrapper> for timing and area information for instance <FLASH>.
Loading core <ddr_sdram_wrapper> for timing and area information for instance
<DDR_SDRAM>.
Loading core <xps_timer_0_wrapper> for timing and area information for instance
<xps_timer_0>.
Loading core <clock_generator_0_wrapper> for timing and area information for instance
<clock_generator_0>.
Loading core <mdm_0_wrapper> for timing and area information for instance <mdm_0>.
Loading core <proc_sys_reset_0_wrapper> for timing and area information for instance
<proc_sys_reset_0>.
Loading core <xps_intc_0_wrapper> for timing and area information for instance
<xps_intc_0>.
Loading core <system_top> for timing and area information for instance <system_top_i>.
===============================================================
==========
Advanced HDL Synthesis Report
Found no macro
===============================================================
==========
===============================================================
==========
*
Low Level Synthesis
*
===============================================================
==========
Optimizing unit <system_top_top> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block system_top_top, actual ratio is 89.
INFO:Xst:2260 - The FF/Latch <microblaze_0/MicroBlaze_Core_I/sync_reset> in Unit
<microblaze_0> is equivalent to the following FF/Latch :
<microblaze_0/MicroBlaze_Core_I/sync_reset_1>
INFO:Xst:2260 - The FF/Latch
<microblaze_0/MicroBlaze_Core_I/Area.Decode_I/ex_Valid_0> in Unit <microblaze_0>
is equivalent to the following FF/Latch :
<microblaze_0/MicroBlaze_Core_I/Area.Decode_I/ex_Valid_0_1>
<mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelR
eg_i_1> in Unit <mb_plb> is equivalent to the following 3 FFs/Latches :
eg_i_1_1>
eg_i_1_2>
eg_i_1_3>
eg_i_0_1>
eg_i_0_2>
eg_i_0_3>
<mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/arbctrl_s
m_cs_FSM_FFd2> in Unit <mb_plb> is equivalent to the following FF/Latch :
m_cs_FSM_FFd2_1>
m_cs_FSM_FFd3_1>
INFO:Xst:2260 - The FF/Latch <mb_plb/GEN_MPLB_RST[1].I_MPLB_RST> in Unit
<mb_plb> is equivalent to the following 10 FFs/Latches :
<mb_plb/GEN_MPLB_RST[0].I_MPLB_RST>
<mb_plb/GEN_SPLB_RST[7].I_SPLB_RST>
<mb_plb/GEN_SPLB_RST[0].I_SPLB_RST> <mb_plb/I_PLB_RST>
<FLASH/MCH_PLB_IPIF_I/INCLUDE_PLB_IPIF_GEN.PLBV46_SLAVE_BURST_I/
I_SLAVE_ATTACHMENT/GEN_WRITE_BUFFER.GEN_WRBUF_WREN1> in Unit
<FLASH> is equivalent to the following FF/Latch :
I_SLAVE_ATTACHMENT/GEN_WRITE_BUFFER.GEN_WRBUF_WREN2>
I_SLAVE_ATTACHMENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.GE
N_S_H_SIZE_REG[2].I_SIZE_S_H_REG> in Unit <FLASH> is equivalent to the
following FF/Latch :
I_SLAVE_ATTACHMENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.G
EN_S_H_SIZE_REG[2].I_SIZE_S_H_REG>
I_SLAVE_ATTACHMENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.I_S
NGL_S_H_REG> in Unit <FLASH> is equivalent to the following FF/Latch :
I_SLAVE_ATTACHMENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.I_
SNGL_S_H_REG>
I_SLAVE_ATTACHMENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.I_B
URST_S_H_REG> in Unit <FLASH> is equivalent to the following FF/Latch :
BURST_S_H_REG>
I_SLAVE_ATTACHMENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.I_C
ACHLN_S_H_REG> in Unit <FLASH> is equivalent to the following FF/Latch :
CACHLN_S_H_REG>
<DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_0>
in Unit <DDR_SDRAM> is equivalent to the following 13 FFs/Latches :
<DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_0_
1>
2>
3>
4>
5>
6>
7>
8>
9>
10>
11>
12>
13>
<DDR_SDRAM/mpmc_core_0/Ctrl_PhyIF_Force_DM_d1_0> in Unit
<DDR_SDRAM> is equivalent to the following FF/Latch :
<DDR_SDRAM/mpmc_core_0/Ctrl_PhyIF_Force_DM_d1_1>
<DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_write/dqs_oe_180
_r1> in Unit <DDR_SDRAM> is equivalent to the following FF/Latch :

_r1_1>
<DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLE
S_PLBV46_PIM.PIM_ADDRESS_DECODER/CLOCK_TO_N_SAMPLE_CIRCUIT/pl
b_rst_pipe_1> in Unit <DDR_SDRAM> is equivalent to the following 13 FFs/Latches :
b_rst_pipe_1_1>
b_rst_pipe_1_2>
b_rst_pipe_1_3>
b_rst_pipe_1_4>
b_rst_pipe_1_5>
b_rst_pipe_1_6>
b_rst_pipe_1_7>
b_rst_pipe_1_8>
b_rst_pipe_1_9>
b_rst_pipe_1_10>
b_rst_pipe_1_11>
b_rst_pipe_1_12>
b_rst_pipe_1_13>
1>
2>
3>
4>
5>
6>
7>
8>
9>
10>
11>
1>
2>
3>
4>
5>
6>
7>
8>
9>
10>
INFO:Xst:2260 - The FF/Latch <DDR_SDRAM/Rst_tocore_7> in Unit
<DDR_SDRAM> is equivalent to the following 8 FFs/Latches :
<DDR_SDRAM/Rst_tocore_6> <DDR_SDRAM/Rst_tocore_3>
<DDR_SDRAM/Rst_tocore_2> <DDR_SDRAM/Rst_topim_1>
<DDR_SDRAM/Rst_topim_0> <DDR_SDRAM/Rst_tocore_tmp>
S_PLBV46_PIM.PIM_ADDRESS_DECODER/addr_cs_FSM_FFd1> in Unit
S_PLBV46_PIM.PIM_ADDRESS_DECODER/addr_cs_FSM_FFd1_1>
INFO:Xst:2260 - The FF/Latch <DDR_SDRAM/mpmc_core_0/InitDone_i2_0> in Unit
<DDR_SDRAM/mpmc_core_0/InitDone_i2_1>
<DDR_SDRAM/mpmc_core_0/InitDone>
1>
2>
3>
4>
5>
6>
7>
8>
9>
S_PLBV46_PIM.PIM_ADDRESS_DECODER/CLOCK_TO_N_SAMPLE_CIRCUIT/sc
2wr_sample_cycle_i> in Unit <DDR_SDRAM> is equivalent to the following 2
FFs/Latches :
2rd_sample_cycle_i>
2ad_sample_cycle_i>
<DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_write/dqs_rst_180
_r1_1>
<DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_write/dq_oe_90_r
1> in Unit <DDR_SDRAM> is equivalent to the following 2 FFs/Latches :
1_1>
1_2>
S_PLBV46_PIM.PIM_READ_MODULE/sig_sl_rdack_i> in Unit <DDR_SDRAM> is
equivalent to the following FF/Latch :
S_PLBV46_PIM.PIM_READ_MODULE/sig_sl_rdack>
<xps_timer_0/PLBv46_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_2> in
Unit <xps_timer_0> is equivalent to the following FF/Latch :
<xps_timer_0/PLBv46_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_2_1>
<xps_timer_0/PLBv46_I/I_SLAVE_ATTACHMENT/I_DECODER/wrce_out_i_5> in
<xps_timer_0/PLBv46_I/I_SLAVE_ATTACHMENT/I_DECODER/wrce_out_i_5_1>
<xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[21].TCSR0_F
F_I> in Unit <xps_timer_0> is equivalent to the following FF/Latch :
F_I>
INFO:Xst:2260 - The FF/Latch <microblaze_0/MicroBlaze_Core_I/sync_reset> in Unit
<microblaze_0> is equivalent to the following FF/Latch :
<microblaze_0/MicroBlaze_Core_I/sync_reset_1>

<microblaze_0/MicroBlaze_Core_I/Area.Decode_I/ex_Valid_0> in Unit <microblaze_0>
is equivalent to the following FF/Latch :
<microblaze_0/MicroBlaze_Core_I/Area.Decode_I/ex_Valid_0_1>
eg_i_1_1>
eg_i_1_2>
eg_i_1_3>
eg_i_0_1>
eg_i_0_2>
eg_i_0_3>
m_cs_FSM_FFd2_1>
m_cs_FSM_FFd3_1>
INFO:Xst:2260 - The FF/Latch <mb_plb/GEN_MPLB_RST[1].I_MPLB_RST> in Unit
<mb_plb> is equivalent to the following 10 FFs/Latches :
<mb_plb/GEN_MPLB_RST[0].I_MPLB_RST>
<mb_plb/GEN_SPLB_RST[0].I_SPLB_RST> <mb_plb/I_PLB_RST>
I_SLAVE_ATTACHMENT/GEN_WRITE_BUFFER.GEN_WRBUF_WREN1> in Unit
<FLASH> is equivalent to the following FF/Latch :

I_SLAVE_ATTACHMENT/GEN_WRITE_BUFFER.GEN_WRBUF_WREN2>
I_SLAVE_ATTACHMENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.I_S
NGL_S_H_REG> in Unit <FLASH> is equivalent to the following FF/Latch :
SNGL_S_H_REG>
I_SLAVE_ATTACHMENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.I_B
URST_S_H_REG> in Unit <FLASH> is equivalent to the following FF/Latch :
BURST_S_H_REG>
I_SLAVE_ATTACHMENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.I_C
ACHLN_S_H_REG> in Unit <FLASH> is equivalent to the following FF/Latch :
CACHLN_S_H_REG>
1>
2>
3>
4>
5>
6>
7>
8>
9>
10>
11>
12>
13>
<DDR_SDRAM/mpmc_core_0/Ctrl_PhyIF_Force_DM_d1_0> in Unit
<DDR_SDRAM/mpmc_core_0/Ctrl_PhyIF_Force_DM_d1_1>
_r1_1>
b_rst_pipe_1> in Unit <DDR_SDRAM> is equivalent to the following 13 FFs/Latches :
b_rst_pipe_1_1>
b_rst_pipe_1_2>
b_rst_pipe_1_3>
b_rst_pipe_1_4>
b_rst_pipe_1_5>
b_rst_pipe_1_6>
b_rst_pipe_1_7>
b_rst_pipe_1_8>
b_rst_pipe_1_9>
b_rst_pipe_1_10>
b_rst_pipe_1_11>
b_rst_pipe_1_12>
b_rst_pipe_1_13>
1>
2>
3>
4>
5>
6>
7>
8>
9>
10>
11>
1>
2>
3>
4>
5>
6>
7>
8>
9>
10>
INFO:Xst:2260 - The FF/Latch <DDR_SDRAM/Rst_tocore_7> in Unit
<DDR_SDRAM/Rst_tocore_2> <DDR_SDRAM/Rst_topim_1>
<DDR_SDRAM/Rst_topim_0> <DDR_SDRAM/Rst_tocore_tmp>
INFO:Xst:2260 - The FF/Latch <DDR_SDRAM/mpmc_core_0/InitDone_i2_0> in Unit
<DDR_SDRAM/mpmc_core_0/InitDone_i2_1>
<DDR_SDRAM/mpmc_core_0/InitDone>
1>
2>
3>
4>
5>
6>
7>
8>
9>
2wr_sample_cycle_i> in Unit <DDR_SDRAM> is equivalent to the following 2
FFs/Latches :
2rd_sample_cycle_i>
2ad_sample_cycle_i>

_r1_1>
1> in Unit <DDR_SDRAM> is equivalent to the following 2 FFs/Latches :
1_1>
1_2>
S_PLBV46_PIM.PIM_READ_MODULE/sig_sl_rdack_i> in Unit <DDR_SDRAM> is
equivalent to the following FF/Latch :
S_PLBV46_PIM.PIM_READ_MODULE/sig_sl_rdack>
<xps_timer_0/PLBv46_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_2> in
<xps_timer_0/PLBv46_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_2_1>
<xps_timer_0/PLBv46_I/I_SLAVE_ATTACHMENT/I_DECODER/wrce_out_i_5> in
<xps_timer_0/PLBv46_I/I_SLAVE_ATTACHMENT/I_DECODER/wrce_out_i_5_1>
F_I> in Unit <xps_timer_0> is equivalent to the following FF/Latch :
F_I>
Final Macro Processing ...
===============================================================
==========
Final Register Report
Found no macro
===============================================================
==========
===============================================================
==========
*
Partition Report
*
===============================================================
==========
Partition Implementation Status
------------------------------No Partitions were found in this design.
------------------------------===============================================================
==========
*
Final Report
*
===============================================================
==========
Final Results
RTL Top Level Output File Name : system_top_top.ngr
Top Level Output File Name
: system_top_top
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: No
Design Statistics
# IOs
Cell Usage :
# BELS
#
BUF
#
GND
#
INV
#
LUT1
#
LUT2
#
LUT2_D
#
LUT2_L
#
LUT3
#
LUT3_D
#
LUT3_L
#
LUT4
#
LUT4_D
#
LUT4_L
#
MULT_AND
#
MUXCY
#
MUXCY_L
: 93
: 6672
:8
: 19
: 155
: 81
: 664
: 25
: 24
: 1358
: 71
: 31
: 2400
: 71
: 106
: 79
: 467
: 266
#
MUXF5
: 399
#
MUXF6
:5
#
MUXF7
:2
#
MUXF8
:1
#
OR2
:1
# VCC
: 12
#
XORCY
: 427
# FlipFlops/Latches
: 5443
#
FD
: 759
#
FD_1
: 10
#
FDC
: 21
#
FDC_1
:5
#
FDCE
: 46
#
FDE
: 407
#
FDE_1
:8
#
FDP
: 13
#
FDR
: 2069
#
FDR_1
: 17
#
FDRE
: 1526
#
FDRE_1
:1
#
FDRS
: 89
#
FDRS_1
:2
#
FDRSE
: 140
#
FDS
: 202
#
FDS_1
:4
#
FDSE
: 103
#
ODDR2
: 21
# RAMS
: 208
#
RAM16X1D
: 193
#
RAMB16_S18_S36
:4
#
RAMB16_S36
:1
#
RAMB16_S36_S36
:6
#
RAMB16_S9_S9
:4
# Shift Registers
: 271
#
SRL16
: 26
#
SRL16E
: 204
#
SRLC16E
: 41
# Clock Buffers
:7
#
BUFG
:7
# IO Buffers
: 110
#
IBUF
: 20
#
IBUFG
:1
#
IOBUF
: 10
#
OBUF
: 62
#
OBUFDS
:1
#
OBUFT
: 16
# DCMs
:2
#
DCM_SP
:2
# MULTs
:3
#
MULT18X18SIO
:3
# Others
:1
#
BSCAN_SPARTAN3
:1
===============================================================
==========
Device utilization summary:
--------------------------Selected Device : 3s500efg320-4
Number of Slices:
4180 out of 4656 89%
Number of Slice Flip Flops:
5427 out of 9312 58%
Number of 4 input LUTs:
5643 out of 9312 60%
Number used as logic:
4986
Number used as Shift registers: 271
Number used as RAMs:
386
Number of IOs:
93
Number of bonded IOBs:
93 out of 232 40%
IOB Flip Flops:
16
Number of BRAMs:
15 out of 20 75%
Number of MULT18X18SIOs:
3 out of 20 15%
Number of GCLKs:
7 out of 24 29%
Number of DCMs:
2 out of
4 50%
--------------------------Partition Resource Summary:
--------------------------No Partitions were found in this design.
--------------------------===============================================================
==========
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE
REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------+
Clock Signal
| Clock buffer(FF name)
| Load |
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------+
fpga_0_clk_1_sys_clk_pin
| clock_generator_0/DCM1_INST/Using_Virtex.DCM_INST:CLK0
| 4158 |
system_top_i/mdm_0/mdm_0/drck_i
| BUFG
| 208 |
system_top_i/mdm_0/bscan_update1
| BUFG
| 42 |
|
clock_generator_0/DCM1_INST/Using_Virtex.DCM_INST:CLK2X+clock_generator_0/
DCM0_INST/Using_Virtex.DCM_INST:CLK0
| 1241 |
|
clock_generator_0/DCM1_INST/Using_Virtex.DCM_INST:CLK2X+clock_generator_0/
DCM0_INST/Using_Virtex.DCM_INST:CLK90
| 244 |
system_top_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy
_if_0/data_path/dqs_delayed_col0<0>(system_top_i/DDR_SDRAM/DDR_SDRAM/mp
mc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0].
.u_dqs_delay_col1/gen_delay.one:O)| NONE(*)
(system_top_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_ph
y_if_0/data_path/data_read_controller/gen_wr[0].u_fifo_0_wr_en/delay_ff) | 13 |
y_if_0/data_path/data_read_controller/gen_wr[0].u_fifo_1_wr_en/delay_ff_1)| 13 |
y_if_0/data_path/data_read_controller/gen_wr[1].u_fifo_0_wr_en/delay_ff) | 13 |
y_if_0/data_path/data_read_controller/gen_wr[1].u_fifo_1_wr_en/delay_ff_1)| 13 |
system_top_i/xps_timer_0/Interrupt
| NONE(system_top_i/xps_intc_0/xps_intc_0/INTC_CORE_I/intr_sync_0)
|1 |
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------+
(*) These 4 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by
combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered
by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to
insert these buffers to the clock signals to help prevent skew problems.
Asynchronous Control Signals Information:
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+
Control Signal
| Buffer(FF name)
| Load |
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+
system_top_i/mdm_0/mdm_0/MDM_Core_I1/Config_Reg_Acst_inv(system_top_i/mdm
_0/mdm_0/MDM_Core_I1/Config_Reg_Acst_inv1_INV_0:O)
| NONE(system_top_i/mdm_0/mdm_0/MDM_Core_I1/Config_Reg_0)
| 23 |
_if_0/data_path/data_read/rd_addr_rst_reg(system_top_i/DDR_SDRAM/DDR_SDRAM/
mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read/rd_addr_rst_reg:Q)
|
NONE(system_top_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mp
mc_phy_if_0/data_path/data_read/gen_rd_addr[0].fifo0_rd_addr_inst/gen_addr[0].u_add
r_bit)| 16 |
_if_0/infrastructure/sys_rst_reg(system_top_i/DDR_SDRAM/DDR_SDRAM/mpmc_cor
e_0/gen_s3_ddr_phy.mpmc_phy_if_0/infrastructure/sys_rst_reg:Q)
|
NONE(system_top_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mp
mc_phy_if_0/data_path/data_read/gen_wr_addr[0].u_fifo_0_wr_addr/gen_addr[0].u_add
r_bit) | 16 |
system_top_i/mdm_0/mdm_0/MDM_Core_I1/SEL_inv(system_top_i/mdm_0/mdm_0/M
DM_Core_I1/SEL_inv1_INV_0:O)
| NONE(system_top_i/mdm_0/mdm_0/MDM_Core_I1/PORT_Selector_0)
| 12 |
fpga_0_rst_1_sys_rst_pin
| IBUF
|4 |
system_top_i/clock_generator_0/clock_generator_0/DCM0_INST/reset(system_top_i/clo
ck_generator_0/clock_generator_0/DCM0_INST/reset1_INV_0:O)
| NONE(system_top_i/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_0)
|4 |
system_top_i/microblaze_0/microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_
Logic.Master_Core.Debug_Area/Command_Reg_Rst(system_top_i/microblaze_0/micro
blaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/C
ommand_Reg_Rst:Q) |
NONE(system_top_i/microblaze_0/microblaze_0/MicroBlaze_Core_I/Area.Implement_
Debug_Logic.Master_Core.Debug_Area/command_reg_0)
|2 |
system_top_i/mdm_0/bscan_update1(system_top_i/mdm_0/mdm_0/Use_Spartan3.BSCA
N_SPARTAN3_I:UPDATE)
|
BUFG(system_top_i/microblaze_0/microblaze_0/MicroBlaze_Core_I/Area.Implement_
Debug_Logic.Master_Core.Debug_Area/running_clock)
|1 |
system_top_i/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/data_cmd_inv(syste
m_top_i/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/data_cmd_inv1_INV_0:O
)
|
NONE(system_top_i/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/execute)
|1 |
system_top_i/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/local_sel_n3(system
_top_i/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Insert_Delays[4].LUT_Del
ay:O)
|
NONE(system_top_i/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I)
|1 |
Logic.Master_Core.Debug_Area/continue_from_brk(system_top_i/microblaze_0/microbl
aze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/con
tinue_from_brk:Q)|
Debug_Logic.Master_Core.Debug_Area/continue_from_brk_TClk)
|1 |
Logic.Master_Core.Debug_Area/force_stop_cmd(system_top_i/microblaze_0/microblaze
_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/force_
stop_cmd1:O) |
Debug_Logic.Master_Core.Debug_Area/force_stop_TClk)
|1 |
Logic.Master_Core.Debug_Area/normal_stop_cmd(system_top_i/microblaze_0/microbla
ze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/nor
mal_stop_cmd1:O) |
Debug_Logic.Master_Core.Debug_Area/normal_stop_TClk)
|1 |
Logic.Master_Core.Debug_Area/start_single_step(system_top_i/microblaze_0/microblaz
e_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/start_
single_step:Q)|
Debug_Logic.Master_Core.Debug_Area/single_Step_TClk)
|1 |
system_top_i/xps_intc_0/xps_intc_0/INTC_CORE_I/iar_0_or0000(system_top_i/xps_int
c_0/xps_intc_0/INTC_CORE_I/iar_0_or00001:O)
| NONE(system_top_i/xps_intc_0/xps_intc_0/INTC_CORE_I/intr_sync_0)
|1 |
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+
Timing Summary:
--------------Speed Grade: -4
Minimum period: 15.926ns (Maximum Frequency: 62.790MHz)
Minimum input arrival time before clock: 4.704ns
Maximum output required time after clock: 11.543ns
Maximum combinational path delay: No path found
Timing Detail:
-------------All values displayed in nanoseconds (ns)
===============================================================
==========
Timing constraint: Default period analysis for Clock 'fpga_0_clk_1_sys_clk_pin'
Clock period: 14.576ns (frequency: 68.606MHz)
Total number of paths / destination ports: 278349 / 14736
------------------------------------------------------------------------Delay:
7.288ns (Levels of Logic = 5)
Source:
system_top_i/DDR_SDRAM/DDR_SDRAM/DUALXCL1_INST.dualxcl_1/addrack_hol
d (FF)
Destination:
system_top_i/DDR_SDRAM/DDR_SDRAM/DUALXCL1_INST.dualxcl_1/dualxcl_fsm
_0/pi_wrfifo_push_a (FF)
Source Clock: fpga_0_clk_1_sys_clk_pin rising 2.0X
Destination Clock: fpga_0_clk_1_sys_clk_pin rising
Data Path:
system_top_i/DDR_SDRAM/DDR_SDRAM/DUALXCL1_INST.dualxcl_1/addrack_hol
d to
system_top_i/DDR_SDRAM/DDR_SDRAM/DUALXCL1_INST.dualxcl_1/dualxcl_fsm
_0/pi_wrfifo_push_a
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- -----------FDR:C->Q
2 0.591 0.622
DDR_SDRAM/DUALXCL1_INST.dualxcl_1/addrack_hold
(DDR_SDRAM/DUALXCL1_INST.dualxcl_1/addrack_hold)
LUT4_D:I0->O
6 0.704 0.704
DDR_SDRAM/DUALXCL1_INST.dualxcl_1/PI_AddrReq1
(DDR_SDRAM/NPI_AddrReq<1>)
LUT3:I2->O
5 0.704 0.637
DDR_SDRAM/DUALXCL1_INST.dualxcl_1/pi_addrack_slowclk1
(DDR_SDRAM/DUALXCL1_INST.dualxcl_1/pi_addrack_slowclk)
LUT4:I3->O
1 0.704 0.424
DDR_SDRAM/DUALXCL1_INST.dualxcl_1/dualxcl_fsm_0/state_FSM_FFd2-In94
(DDR_SDRAM/DUALXCL1_INST.dualxcl_1/dualxcl_fsm_0/state_FSM_FFd2-In94)
LUT4:I3->O
2 0.704 0.482
DDR_SDRAM/DUALXCL1_INST.dualxcl_1/dualxcl_fsm_0/state_FSM_FFd2-In128
(DDR_SDRAM/DUALXCL1_INST.dualxcl_1/dualxcl_fsm_0/state_FSM_FFd2-In)
LUT3:I2->O
1 0.704 0.000
DDR_SDRAM/DUALXCL1_INST.dualxcl_1/dualxcl_fsm_0/pi_wrfifo_push_a_or0000
1
(DDR_SDRAM/DUALXCL1_INST.dualxcl_1/dualxcl_fsm_0/pi_wrfifo_push_a_or0000
)
FD:D
0.308
DDR_SDRAM/DUALXCL1_INST.dualxcl_1/dualxcl_fsm_0/pi_wrfifo_push_a
---------------------------------------Total
7.288ns (4.419ns logic, 2.869ns route)
(60.6% logic, 39.4% route)
===============================================================
==========
Timing constraint: Default period analysis for Clock
'system_top_i/mdm_0/mdm_0/drck_i'
------------------------------------------------------------------------Delay:
Source:
system_top_i/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/SYNC_FDRE (FF)
Destination:
Logic.Master_Core.Debug_Area/shift_count_7 (FF)
Source Clock: system_top_i/mdm_0/mdm_0/drck_i falling
Destination Clock: system_top_i/mdm_0/mdm_0/drck_i rising
Data Path:
system_top_i/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/SYNC_FDRE to
Logic.Master_Core.Debug_Area/shift_count_7
Gate Net
---------------------------------------- -----------FDRE_1:C->Q
1 0.591 0.499 JTAG_CONTROL_I/SYNC_FDRE
(JTAG_CONTROL_I/sync)
LUT3:I1->O
1 0.704 0.424 JTAG_CONTROL_I/shifting_Data_SW0 (N34)
LUT4:I3->O
9 0.704 0.820 JTAG_CONTROL_I/shifting_Data
(Dbg_Shift_7)
end scope: 'mdm_0/MDM_Core_I1'
end scope: 'mdm_0'
begin scope: 'microblaze_0'
INV:I->O
8 0.704 0.757
microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_
Area/Shift_inv1_INV_0
(microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_
Area/Shift_inv)
FDR:R
0.911
Area/shift_count_0
----------------------------------------
Total

(59.1% logic, 40.9% route)
===============================================================
==========
'system_top_i/mdm_0/bscan_update1'
------------------------------------------------------------------------Delay:
Source:
system_top_i/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I (FF)
Destination:
Logic.Master_Core.Debug_Area/control_reg_0 (FF)
Source Clock: system_top_i/mdm_0/bscan_update1 falling
Destination Clock: system_top_i/mdm_0/bscan_update1 rising
Data Path: system_top_i/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I
to
Logic.Master_Core.Debug_Area/control_reg_0
Gate Net
---------------------------------------- -----------FDC_1:C->Q
14 0.591 1.175 JTAG_CONTROL_I/FDC_I
(JTAG_CONTROL_I/data_cmd)
LUT2:I0->O
2 0.704 0.622 JTAG_CONTROL_I/Dbg_Reg_En_I<2>1
(Dbg_Reg_En_0<2>)
end scope: 'mdm_0'
LUT4:I0->O
4 0.704 0.762
Area/Command_Reg_En_cmp_eq000011
Area/N6)
LUT3:I0->O
2 0.704 0.622
Area/Control_Reg_En_cmp_eq000011
Area/N25)
LUT3:I0->O
9 0.704 0.820
Area/Control_Reg_En_cmp_eq00001
Area/Control_Reg_En)
FDCE:CE
0.555
Area/force_stop_TClk
---------------------------------------Total
(49.8% logic, 50.2% route)
===============================================================
==========
'system_top_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_ph
y_if_0/data_path/dqs_delayed_col1<1>'
------------------------------------------------------------------------Delay:
Source:
_if_0/data_path/data_read_controller/gen_wr[1].u_fifo_1_wr_en/delay_ff_1 (FF)
Destination:
_if_0/data_path/data_read/gen_wr_addr[1].u_fifo_1_wr_addr/gen_addr[3].u_addr_bit
(FF)
Source Clock:
_if_0/data_path/dqs_delayed_col1<1> rising
Destination Clock:
_if_0/data_path/dqs_delayed_col1<1> falling
Data Path:
_if_0/data_path/data_read_controller/gen_wr[1].u_fifo_1_wr_en/delay_ff_1 to
Gate Net
---------------------------------------- -----------FDR:C->Q
1 0.591 0.499
DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read_co
ntroller/gen_wr[1].u_fifo_1_wr_en/delay_ff_1
(DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read_c
ontroller/gen_wr[1].u_fifo_1_wr_en/din_delay)
LUT2:I1->O
12 0.704 0.961
ntroller/gen_wr[1].u_fifo_1_wr_en/dout1
(DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/fifo_1_wr_e
n<1>)
FDCE:CE
0.555
DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read/gen
_wr_addr[1].u_fifo_1_wr_addr/gen_addr[0].u_addr_bit
---------------------------------------Total
(55.9% logic, 44.1% route)
===============================================================
==========
------------------------------------------------------------------------Delay:
Source:
_if_0/data_path/data_read_controller/gen_wr[1].u_fifo_0_wr_en/delay_ff (FF)
Destination:
(FF)
Source Clock:
Destination Clock:
Data Path:
_if_0/data_path/data_read_controller/gen_wr[1].u_fifo_0_wr_en/delay_ff to
Gate Net
---------------------------------------- -----------FDR:C->Q
3 0.591 0.610
ntroller/gen_wr[1].u_fifo_0_wr_en/delay_ff
LUT2:I1->O
12 0.704 0.961
n<1>)
FDCE:CE
0.555
---------------------------------------Total
(54.1% logic, 45.9% route)
===============================================================
==========
------------------------------------------------------------------------Delay:
Source:
_if_0/data_path/data_read_controller/gen_wr[0].u_fifo_1_wr_en/delay_ff_1 (FF)
Destination:
(FF)
Source Clock:
Destination Clock:
Data Path:
_if_0/data_path/data_read_controller/gen_wr[0].u_fifo_1_wr_en/delay_ff_1 to
Gate Net
---------------------------------------- ------------
FDR:C->Q
1 0.591 0.499
ntroller/gen_wr[0].u_fifo_1_wr_en/delay_ff_1
LUT2:I1->O
12 0.704 0.961
n<0>)
FDCE:CE
0.555
---------------------------------------Total
(55.9% logic, 44.1% route)
===============================================================
==========
------------------------------------------------------------------------Delay:
Source:
_if_0/data_path/data_read_controller/gen_wr[0].u_fifo_0_wr_en/delay_ff (FF)
Destination:
(FF)
Source Clock:
Destination Clock:
Data Path:
_if_0/data_path/data_read_controller/gen_wr[0].u_fifo_0_wr_en/delay_ff to
Gate Net

---------------------------------------- -----------FDR:C->Q
3 0.591 0.610
ntroller/gen_wr[0].u_fifo_0_wr_en/delay_ff
LUT2:I1->O
12 0.704 0.961
n<0>)
FDCE:CE
0.555
---------------------------------------Total
(54.1% logic, 45.9% route)
===============================================================
==========
Timing constraint: Default OFFSET IN BEFORE for Clock
------------------------------------------------------------------------Offset:
Source:
system_top_i/mdm_0/mdm_0/Use_Spartan3.BSCAN_SPARTAN3_I:SHIFT (PAD)
Destination:
Logic.Master_Core.Debug_Area/shift_count_7 (FF)
Destination Clock: system_top_i/mdm_0/mdm_0/drck_i rising
Data Path: system_top_i/mdm_0/mdm_0/Use_Spartan3.BSCAN_SPARTAN3_I:SHIFT
to
Logic.Master_Core.Debug_Area/shift_count_7
Gate Net
---------------------------------------- -----------BSCAN_SPARTAN3:SHIFT 5 0.000 0.000
mdm_0/Use_Spartan3.BSCAN_SPARTAN3_I (bscan_shift)
begin scope: 'mdm_0/MDM_Core_I1'
LUT4:I0->O
9 0.704 0.820 JTAG_CONTROL_I/shifting_Data
(Dbg_Shift_7)
end scope: 'mdm_0'

INV:I->O
8 0.704 0.757
Area/Shift_inv1_INV_0
Area/Shift_inv)
FDR:R
0.911
Area/shift_count_0
---------------------------------------Total
(66.5% logic, 33.5% route)
===============================================================
==========
Timing constraint: Default OFFSET IN BEFORE for Clock 'fpga_0_clk_1_sys_clk_pin'
------------------------------------------------------------------------Offset:
Source:
fpga_0_rst_1_sys_rst_pin (PAD)
Destination:
system_top_i/proc_sys_reset_0/proc_sys_reset_0/EXT_LPF/exr_d1
(FF)
Destination Clock: fpga_0_clk_1_sys_clk_pin rising
Data Path: fpga_0_rst_1_sys_rst_pin to
system_top_i/proc_sys_reset_0/proc_sys_reset_0/EXT_LPF/exr_d1
Gate Net
---------------------------------------- -----------IBUF:I->O
5 1.218 0.633 fpga_0_rst_1_sys_rst_pin_IBUF
(fpga_0_rst_1_sys_rst_pin_IBUF)
begin scope: 'system_top_i'
begin scope: 'proc_sys_reset_0'
FDS:S
0.911
proc_sys_reset_0/EXT_LPF/exr_d1
---------------------------------------Total
(77.1% logic, 22.9% route)
===============================================================
==========
Timing constraint: Default OFFSET IN BEFORE for Clock
------------------------------------------------------------------------Offset:
Source:
system_top_i/mdm_0/mdm_0/Use_Spartan3.BSCAN_SPARTAN3_I:SEL2 (PAD)
Destination:
system_top_i/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/command_0 (FF)
Destination Clock: system_top_i/mdm_0/bscan_update1 falling
Data Path: system_top_i/mdm_0/mdm_0/Use_Spartan3.BSCAN_SPARTAN3_I:SEL2
to system_top_i/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/command_0
Gate Net
---------------------------------------- -----------BSCAN_SPARTAN3:SEL2 2 0.000 0.000
mdm_0/Use_Spartan3.BSCAN_SPARTAN3_I (mdm_0/sel)
LUT3:I0->O
7 0.704 0.743 Ext_JTAG_SEL11 (N2)
LUT3:I2->O
8 0.704 0.757 Old_MDM_SEL1 (Old_MDM_SEL)
FDE_1:CE
0.555
JTAG_CONTROL_I/command_7
---------------------------------------Total
(63.3% logic, 36.7% route)
===============================================================
==========
Timing constraint: Default OFFSET OUT AFTER for Clock 'fpga_0_clk_1_sys_clk_pin'
------------------------------------------------------------------------Offset:
Source:
system_top_i/FLASH/FLASH/EMC_CTRL_I/IO_REGISTERS_I/mem_wen_reg (FF)
Destination:
fpga_0_FLASH_Mem_WEN_pin (PAD)
Source Clock: fpga_0_clk_1_sys_clk_pin rising
Data Path:
system_top_i/FLASH/FLASH/EMC_CTRL_I/IO_REGISTERS_I/mem_wen_reg to
fpga_0_FLASH_Mem_WEN_pin
Gate Net
---------------------------------------- -----------FDS:C->Q
2 0.591 0.447
FLASH/EMC_CTRL_I/IO_REGISTERS_I/mem_wen_reg (Mem_WEN)
end scope: 'FLASH'
end scope: 'system_top_i'
OBUF:I->O
3.272
fpga_0_FLASH_Mem_WEN_pin_OBUF
(fpga_0_FLASH_Mem_WEN_pin)
---------------------------------------Total
(89.6% logic, 10.4% route)

===============================================================
==========
Timing constraint: Default OFFSET OUT AFTER for Clock
------------------------------------------------------------------------Offset:
Source:
Logic.Master_Core.Debug_Area/Use_SRL16.The_Cache_Addresses[3].SRL16E_Cache
_I (FF)
Destination:
system_top_i/mdm_0/mdm_0/Use_Spartan3.BSCAN_SPARTAN3_I:TDO2 (PAD)
Source Clock: system_top_i/mdm_0/mdm_0/drck_i rising
Data Path:
Logic.Master_Core.Debug_Area/Use_SRL16.The_Cache_Addresses[3].SRL16E_Cache
_I to system_top_i/mdm_0/mdm_0/Use_Spartan3.BSCAN_SPARTAN3_I:TDO2
Gate Net
---------------------------------------- -----------SRL16E:CLK->Q
1 3.706 0.499
Area/Use_SRL16.The_Cache_Addresses[3].SRL16E_Cache_I
Area/tdo_config_word1<4>)
LUT3:I1->O
1 0.704 0.455
Area/TDO23
Area/TDO23)
LUT4:I2->O
1 0.704 0.000
Area/TDO73_F (N592)
MUXF5:I0->O
1 0.321 0.499
Area/TDO73
Area/TDO73)
LUT4:I1->O
1 0.704 0.000
Area/TDO324_SW01
Area/TDO324_SW0)
MUXF5:I1->O
1 0.321 0.424
Area/TDO324_SW0_f5 (N450)
LUT4:I3->O
1 0.704 0.499
Area/TDO324 (DBG_TDO)
end scope: 'microblaze_0'
begin scope: 'mdm_0'
LUT4:I1->O
1 0.704 0.595 TDO_i81 (TDO_i81)
LUT4:I0->O
0 0.704 0.000 TDO_i217 (TDO)
BSCAN_SPARTAN3:TDO2
0.000
mdm_0/Use_Spartan3.BSCAN_SPARTAN3_I
---------------------------------------Total
(74.3% logic, 25.7% route)
===============================================================
==========
Timing constraint: Default OFFSET OUT AFTER for Clock
------------------------------------------------------------------------Offset:
Source:
system_top_i/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I (FF)
Destination:
system_top_i/mdm_0/mdm_0/Use_Spartan3.BSCAN_SPARTAN3_I:TDO2 (PAD)
Source Clock: system_top_i/mdm_0/bscan_update1 falling
Data Path: system_top_i/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I
to system_top_i/mdm_0/mdm_0/Use_Spartan3.BSCAN_SPARTAN3_I:TDO2
Gate Net
---------------------------------------- -----------FDC_1:C->Q
14 0.591 1.175 JTAG_CONTROL_I/FDC_I
(JTAG_CONTROL_I/data_cmd)
LUT2:I0->O
8 0.704 0.792 JTAG_CONTROL_I/Dbg_Reg_En_I<7>1
(Dbg_Reg_En_0<7>)
end scope: 'mdm_0'
LUT4:I2->O
1 0.704 0.455
Area/TDO264
Area/TDO264)
LUT4:I2->O
1 0.704 0.000
Area/TDO324_SW01
Area/TDO324_SW0)
MUXF5:I1->O
1 0.321 0.424
Area/TDO324_SW0_f5 (N450)
LUT4:I3->O
1 0.704 0.499
Area/TDO324 (DBG_TDO)
end scope: 'microblaze_0'
begin scope: 'mdm_0'
LUT4:I1->O
1 0.704 0.595 TDO_i81 (TDO_i81)
LUT4:I0->O
0 0.704 0.000 TDO_i217 (TDO)
BSCAN_SPARTAN3:TDO2
0.000
mdm_0/Use_Spartan3.BSCAN_SPARTAN3_I
---------------------------------------Total
(56.6% logic, 43.4% route)
===============================================================
==========
-->
Total memory usage is 210840 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 65 ( 0 filtered)
Chapter-4
EMBEDDED DEVELOPMENT KIT [EDK] 13.1
The Xilinx Embedded Development Kit (EDK) is a suite of tools and Intellectual
Property (IP) that enables you to design a complete embedded processor system for
implementation In a Xilinx Field Programmable Gate Array (FPGA) device.
The Embedded Development Kit (EDK) is a suite of tools and IP that you can
use to design a complete embedded processor system for implementation in a
Xilinx FPGA device.
Xilinx Platform Studio (XPS) is the development environment used for

designing the
hardware portion of your embedded processor system.
The Software Development Kit (SDK) is an integrated development

environment,
complementary to XPS, that is used for C/C++ embedded software application
creation
and verification.
EDK is designed to assist in all phases of the embedded design process

Main EDK components include:
Hardware IP for the Xilinx embedded processors
Drivers and libraries for the embedded software development
GNU compiler and debugger for C/C++ software development targeting the
Micro Blaze and PowerPC processors
Typically, the ISE development software is used to add an Embedded Processor
source,
which is then created in XPS using the Base System Builder.
The steps to develop an embedded processor are :

1) You use XPS primarily for embedded processor hardware system development.
Specification of the microprocessor, peripherals, and the interconnection of these
components, along with their respective detailed configuration, takes place in
XPS.
2) You use SDK for software development. SDK is also available as a standalone
application.
3) After your FPGA is configured with the bitstream containing the embedded
design, you can download and debug the Executable and Linkable Format (ELF)
file from your
software project from within SDK.
CREATING A NEW PROJECT
The Base System Builder:
The Base System Builder (BSB) is a wizard in the Xilinx Platform Studio
(XPS) software that quickly and efficiently establishes a working design. You can
then customize your design.
Xilinx recommends using the BSB wizard to create the foundation for any new
embedded design project. While the wizard might be all you need to create your
design, if you require more customization, the BSB saves you time by automating
common hardware and software platform configuration tasks. After running the
wizard, you have a working project that contains all the basic elements needed to
build more customized or complex systems.
Use the BSB wizard to select and configure a processor and I/O interfaces, add
internal peripherals, and generate a system summary report.
Base System Builder requires the selection of an available development board, or
a custom board.
Selecting an Interconnect Type
You can create an AXI system or a PLB system in the Base System Builder.
Selecting and Configuring a Processor
You can choose a MicroBlaze or PowerPC processor and select:
Reference clock frequency
Processor-bus clock frequency
Reset polarity
Processor configuration for debug
Cache setup
Floating Point Unit (FPU) setting.
Selecting and Configuring Multiple I/O Interfaces.
A Xilinx Microprocessor Project (XMP) file is the top-level file description of the
embedded system. All project information is saved in the XMP file.
The XMP file is created and handled in ISE like any other source, such as HDL
code and
constraints files.
XILINX PLATFORM STUDIO :
XPS includes a graphical user interface that provides a set of tools to aid
in project design. From the XPS software, you can design a complete embedded
processor system for implementation within a Xilinx FPGA device..
1)PROJECT INFORMATION AREA

2)SYSTEM ASSEMBLY VIEW
3)CONSOLE WINDOW
4)CONNECTIVITY PANEL
5)VIEW BUTTONS
6)Filter pane
System Assembly View:
The System Assembly View allows you to view and configure system
block elements. If the System Assembly View is not already maximized in the
main window, click and open the
System Assembly View tab at the bottom of the pane.
Bus Interface, Ports, and Addresses Tabs
The System Assembly View comprises three panes, which you can access
by clicking the
tabs at the top of the view.
The Bus Interface tab displays the connectivity in your design. Use this view
to
modify parameters of peripherals and interconnects.
The Ports tab displays ports in your design. Use this view to modify the
details for
each port.
The Addresses tab displays the address range for each IP instance in your
design.
XPS Tools
XPS includes the underlying tools you need to develop the hardware components
of an
embedded processor system.
Platgen:
XPS includes the Hardware Platform Genera tion tool, Platgen, for
generating the
embedded processor system.
When you implement the FPGA design in Project Navigator, Platgen
automatically runs if
necessary.
To start Platgen, click Hardware > Generate Netlist.
Simgen:
XPS includes the Simulation Model Generation tool, Simgen, for
generating simulation
models of your embedded hardware system based on your original embedded
hardware
design (behavioral) or finished FPGA implementation (timing-accurate).
When you implement the FPGA design in Project Navigator, Project Navigator
automatically invokes Simgen when necessary.
Click Simulation > Generate Simulation HDL Files to start Simgen.
Note: When you begin by creating your design in Project Navigator, simulation is
not available in
XPS. Use Project Navigator for simulation

Directory Hierarcy
Directory View
The BSB automatically creates a project director y with the name of your
embedded system source. This directory contains the subdirectories for your
project in the repository search path, shown in Figure 3-3:
__xps
:Contains intermediate files generated by XPS and other tools

for internal project manage ment. You will not use this
directory.
Blockdiagram : Contains files related to the block diagram.
Data
: Contains the user constraints file (UCF).
Etc
: Contains files that capture the options used to run various
tools.
implementation :Contains the netlist and HDL wrapper files generated when
Platgen runs.
Pcores
:Used for including custom hardware peripherals.
system.xmp
: This is the top-level project design file. XPS reads this file and
graphically displays its contents in the XPS user interface.
Project Navigator uses this file as the main source file for the embedded processor
system.
system.mhs
: The system Microprocessor Hardware Specification, or
MHS file, captures the system elements, their parameters, and connectivity in a
text format. The MHS file is the hardware foundation for your project.
Your entire embedded hardware system is represented by the MHS

file.
Microprocessor Hardware specification :

The embedded hardware platform includes one or more processors, along
with a variety of peripherals and memory blocks. These blocks of IP use
an interconnect network to communicate.

XPS maintains your hardware platform description in a high-level form,
known as the Microprocessor Hardware Specification (MHS) file. The
MHS, which is an editable text file, is the principal source file
representing the hardware component of your embedded system.

XPS synthesizes the MHS source file into netlists ready for the FPGA
place and route process using an executable called Platgen.

The MHS file is integral to your design process. It contains all peripheral
instantiations along with their parameters. The MHS file defines the
configuration of the embedded processor system. It includes information
on the bus architecture, peripherals, processor,
connectivity, and address space.
Converting the Hardware Platform to a Bitstream
For a design to work in an FPGA, it needs to be converted to a
bitstream
This conversion is a three step process.
First, XPS generates a netlist that is representative of your
embedded hardware platform

Next, the design is implemented (mapped into FPGA logic) in the
Xilinx ISE Design Suite tools.

In the final step, the implemented design is converted to the
bitstream that can be then downloaded to the FPGA.
When you generate the netlist, it invokes the platform building tool, Platgen,
which does the following:
Reads the design platform configuration MHS file and runs all necessary design
rule
checks to validate the correctness of the design.
Synthesizes the design using Xilinx Synthesis Technology (XST).
Produces netlist files (with an .ngc extension) for each peripheral, as well as the
overall embedded system.
Generates Hardware Description Language (HDL) wrapper files for each
peripheral
and the overall system. To see the created HDL files, look in the
< project_name>\system\hdl directory..
Exporting Your Hardware Platform :

You created your project in Project Navigator and added an embedded processor
source, then designed your hardware platform in XPS using the Base System
Builder, and finally generated a bitstream for the FPGA. Now, you will export
your hardware platform description to the Software Development Kit (SDK).
The exported .xml file has the information SDK requires for you to do software
development and debug work on the hardware platform that you designed
software Development Kit(sdk):
SDK is a complementary program to XPS. You use SDK to develop the
software that is used on the embedded platform built in XPS. SDK is based on
the Eclipse open source tool suite.
When you open SDK, you create a workspace. A workspace is a directory
location that is used by SDK to store project data and metadata. You must provide
an initial workspace location when SDK is launched. You can create multiple
workspaces to more easily manage multiple software versions.
A software project contains one or more source files, along with the necessary
header files, to allow compilation and generation of a binary output (.elf) file. A
workspace can contain multiple software projects. Each software project must
have a corresponding board support package.
You must have a hardware platform for your design. The hardware platform is
the embedded hardware design that is created in XPS. The hardware platform
includes the XML-based hardware description file, the bitstream file, and the
BMM file. When you import the XML file into SDK, you import the hardware
platform. Multiple hardware platforms can exist in a single workspace.
A board support package (BSP) is a collection of libraries and drivers that form
the lowest layer of your application software stack. Your software applications
must link against or run on top of a given software platform using the provided
Application Program Interfaces (APIs).
You can have SDK create board support packages for two different run-time
environments:
STANDALONE - A simple, semi-hosted and single-threaded environment with
basic
features such as standard input/output an d access to processor hardware features.
XILKERNEL - A simple and lightweight kernel that provides POSIX-style
services such as scheduling, threads, synchronization, message passing, and
timers.
When SDK opens, it prompts you to create a workspace. This is the folder
in which your software projects are stored. For this example, create a new
workspace called SDK_Workspace .

Select File > New > Xilinx C Project.
Create a hardware platform called hw_platform_0 and use the default
location.
In the Target Hardware Specification field, select the system.xml file in
the <project home>\system\SDK\SDK_Export\hw folder of your project.

Click Finish
Select the Xilkernel posix thread demo Sample Project Template. The
Project name fills in automatically with Xilkernel_posix_thread_demo_0.
For the project location, make sure that the Use default location check
box is selected and click Next.

Select the Create a new Board Support Package project option and leave
the default options as they are set. Here our BSP(board support package)
will be selected as xilkernel OS. we can change the setting by going to bsp
settings.
The
Xilkernel_posix_thread_demo_0 sample application builds
automatically, producing an ELF file suitable for downloading onto the

target hardware.
Now modify the c code with the user application c code . In our
implementation we are going for encryption and decryption using
xilkernel. The corresponding code for encryption and decryption is shown
below :
copy the code for transmitter and receiver individually.
--------C CODE FOR IMPLEMENTING ENCRYPTION USING XILKERNEL

--------/* Includes */
#include "xmk.h"
#include "os_config.h"
#include "sys/ksched.h"
#include "sys/init.h"
#include "config/config_param.h"
#include "stdio.h"
#include "xparameters.h"
#include "platform.h"
#include "platform_config.h"
#include <pthread.h>
#include <sys/types.h>
//unsigned
char
mes1[]="\r\nImplementation
of
cryptography
based
Encryption/Decryption algorithm\r\n";
unsigned char mes2[]="\r\nEnter input plaintext(Max 8 characters):";
unsigned char mes3[]="\r\n\r\nEnter Encryption key(Max 16 characters):";
unsigned char mes4[]="\r\nEncrypted data is sent to Receiver \r\n: ";
char readchar(void);
void encipher(const unsigned long *const v,unsigned long *const w,const
unsigned long *const k);
void decipher(const unsigned long *const v,unsigned long *const w, const

void encipher(const unsigned long *const v,unsigned long *w, const unsigned
long *const k)
{
unsigned
long
y=v[0],z=v[1],sum=0x0L,delta=0x9E3779B9L,a=k[0],b=k[1],c=k[2],d=k[3],n=3
2;
while(n-->0)
{
sum += delta;
y += ((z << 4)+a) ^ z+sum ^ ((z >> 5)+b);
z += ((y << 4)+c) ^ y+sum ^ ((y >> 5)+d);
}
w[0]=y; w[1]=z;
//DisplayMesPC(w);
}
// Decryption Function
void decipher(const unsigned long *const v,unsigned long *w, const unsigned
long *const k)
{
unsigned
long
y=v[0],z=v[1],delta=0x9E3779B9L,sum/*=0xc6ef3720L*/,a=k[0],b=k[1],c=k[2],
d=k[3],n=32;
sum=delta<<5;
while(n-->0)
{
z -= ((y << 4)+c) ^ y+sum ^ ((y >> 5)+d);
y -= ((z << 4)+a)^ z+sum ^ ((z >> 5)+b);
sum -= delta;
}
w[0]=y; w[1]=z;
//DisplayMesPC(v);
}
void SendChar(unsigned char x)
{
unsigned char ch;
ch=x;
// transmit function to send character to PC
xil_printf("%c",ch);
}
void DisplayMesPC(unsigned char *mes)
{
int counter;
for (counter=0;mes[counter]!='\0';counter++)
{
SendChar(mes[counter]);
}
}
/* Declarations */
#define DATA_SIZE 400
#define N_THREADS 1
void* master_thread(void *);
void* partial_sum_worker(void *);
/* Data */
int input_data[DATA_SIZE];
/* Functions */
int main()
{
int i;
init_platform();
/* Assign random data to the input array */
for (i = 0; i < DATA_SIZE; i++)
input_data[i] = i + 1;
/* Initialize xilkernel */
xilkernel_init();
/* Create the master thread */
xmk_add_static_thread(master_thread, 0);
/* Start the kernel */
xilkernel_start();
/* Never reached */
cleanup_platform();
return 0;
}
/* The master thread */
void* master_thread(void *arg)
{
pthread_t worker[N_THREADS];
pthread_attr_t attr;
#if SCHED_TYPE == SCHED_PRIO
struct sched_param spar;
#endif
int i, ret, *result;
int args[N_THREADS];
int final_result;
xil_printf("----------------------------------------------------------------------------\r\n")
;
xil_printf("implementation of Xilkernel POSIX Threads \r\n");
xil_printf("----------------------------------------------------------------------------\r\n")
;
xil_printf("Kernel based communication between 2 FPGA's.\r\n");
xil_printf("----------------------------------------------------------------------------\r\n\r
\n");
xil_printf("Xilkernel : Master Thread Starting.\r\n");
pthread_attr_init (&attr);
spar.sched_priority = PRIO_HIGHEST;
pthread_attr_setschedparam(&attr, &spar);
#endif
/* This is how we can join with a thread and reclaim its return value */
pthread_attr_setdetachstate(&attr, PTHREAD_CREATE_JOINABLE);
for (i = 0; i < N_THREADS; i++) {
args[i] = i;
ret = pthread_create (&worker[i], &attr, (void*)partial_sum_worker,

&args[i]);
if (ret != 0) {
xil_printf ("Xilkernel Demo: ERROR (%d) launching worker thread" \
"%d.\r\n", ret, i);
break;
}
}
if (ret) {
xil_printf("Xilkernel Demo: Master Thread Terminating.\r\n");
return (void*)-1;
}

ret = pthread_join(worker[i], (void*)&result);
}
xil_printf("Xilkernel : Master Thread Completing.\r\n");
return (void*)0;
}
/* The worker thread */
void* partial_sum_worker(void *arg)
{
int i, psum;
unsigned char j=0;
unsigned char key1[16],key2[16];
unsigned char input[8],*output; /* key1 for encryption and key2 for
decryption and input is 8 byte data*/
unsigned char *mes; /* buffer to hold the message before printing */
unsigned long *v;
unsigned long *k1,*k2;
unsigned long w[2],x[2];
unsigned char *k3;
//unsigned char output1[8];
unsigned char key4[8];
while(1)
{
print("\r\nImplementation of Scalable encryption algorithm.\r\n");

//serialInit();
//DisplayMesPC(mes1);
DisplayMesPC(mes2);
for(j=0;j<8;j++)
{
input[j]=XUartLite_RecvByte(STDIN_BASEADDRESS);
//input[i]=data;
//xil_printf("%c", input[i]);
SendChar(input[j]);
}
v=(unsigned long *)&input[0];
DisplayMesPC(mes3);
for(j=0;j<16;j++)
{
key1[j]=XUartLite_RecvByte(STDIN_BASEADDRESS);
//xil_printf("%c", key1[i]);
SendChar(key1[j]);
}
k1=(unsigned long *)&key1[0];
encipher(v,w,k1); // encryption
DisplayMesPC(mes4);
mes=w;
for(i=0;i<8;i++)
{
key4[i]=*mes;
mes++;
XUartLite_SendByte(XPAR_UARTLITE_2_BASEADDR,key4[i]);
// xil_printf("%c", key2[i]);
//SendChar(key4[i]);
}
psum = 0;
/* This is how return a value to the parent */
pthread_exit((void*)psum);
return NULL;
}
}
--------C CODE FOR IMPLEMENTING DECRYPTION USING XILKERNEL
--------#include "xmk.h"
#include "os_config.h"
#include "sys/ksched.h"
#include "sys/init.h"
#include "config/config_param.h"
#include "stdio.h"
#include "xparameters.h"
#include "platform.h"
#include "platform_config.h"
#include <pthread.h>
#include <sys/types.h>
unsigned char mes1[]="\r\nEncryted data from transmitter through uart \r\n";
unsigned char mes2[]="\r\nEnter input plaintext(Max 8 characters):";
unsigned char mes3[]="\r\n\r\nEnter Encryption key(Max 16 characters):";
unsigned char mes4[]="\r\nDecrypted data is : ";
char readchar(void);
void encipher(const unsigned long *const v,unsigned long *const w,const
void decipher(const unsigned long *const v,unsigned long *const w, const
void encipher(const unsigned long *const v,unsigned long *w, const unsigned
long *const k)
{
unsigned
long
y=v[0],z=v[1],sum=0x0L,delta=0x9E3779B9L,a=k[0],b=k[1],c=k[2],d=k[3],n=3
2;
while(n-->0)
{
sum += delta;
y += ((z << 4)+a) ^ z+sum ^ ((z >> 5)+b);
z += ((y << 4)+c) ^ y+sum ^ ((y >> 5)+d);
}
w[0]=y; w[1]=z;
//DisplayMesPC(w);
}
// Decryption Function
void decipher(const unsigned long *const v,unsigned long *w, const unsigned
long *const k)
{
unsigned
long
y=v[0],z=v[1],delta=0x9E3779B9L,sum/*=0xc6ef3720L*/,a=k[0],b=k[1],c=k[2],
d=k[3],n=32;
sum=delta<<5;
while(n-->0)
{
z -= ((y << 4)+c) ^ y+sum ^ ((y >> 5)+d);
y -= ((z << 4)+a)^ z+sum ^ ((z >> 5)+b);
sum -= delta;
}
w[0]=y; w[1]=z;
//DisplayMesPC(v);
}
void SendChar(unsigned char x)
{
unsigned char ch;
ch=x;
xil_printf("%c",ch);
// transmit function to send character to PC
}
void DisplayMesPC(unsigned char *mes)
{
int counter;
for (counter=0;mes[counter]!='\0';counter++)
{
SendChar(mes[counter]);
}
}
/* Declarations */
#define DATA_SIZE 400
#define N_THREADS 1
void* master_thread(void *);
void* partial_sum_worker(void *);
/* Data */
int input_data[DATA_SIZE];
/* Functions */
int main()
{
int i;
init_platform();
/* Assign random data to the input array */
for (i = 0; i < DATA_SIZE; i++)
input_data[i] = i + 1;
/* Initialize xilkernel */
xilkernel_init();
/* Create the master thread */
xmk_add_static_thread(master_thread, 0);
/* Start the kernel */
xilkernel_start();
/* Never reached */
cleanup_platform();
return 0;
}
/* The master thread */
void* master_thread(void *arg)
{
pthread_t worker[N_THREADS];
pthread_attr_t attr;
struct sched_param spar;
#endif
int i, ret, *result;
int args[N_THREADS];
int final_result;
xil_printf("----------------------------------------------------------------------------\r\n")
;
xil_printf(" Implementation of Xilkernel POSIX Threads \r\n");
xil_printf("----------------------------------------------------------------------------\r\n")
;
xil_printf(" Kernel Based communication between 2 FPGA's. \r\n");
xil_printf("----------------------------------------------------------------------------\r\n\r
\n");
xil_printf("Xilkernel : Child Thread Starting.\r\n");
pthread_attr_init (&attr);
spar.sched_priority = PRIO_HIGHEST;
pthread_attr_setschedparam(&attr, &spar);
#endif
/* This is how we can join with a thread and reclaim its return value */
pthread_attr_setdetachstate(&attr, PTHREAD_CREATE_JOINABLE);
args[i] = i;
ret = pthread_create (&worker[i], &attr, (void*)partial_sum_worker,
&args[i]);
if (ret != 0) {
xil_printf ("Xilkernel : ERROR (%d) launching worker thread" \
"%d.\r\n", ret, i);
break;
}
}
if (ret) {
xil_printf("Xilkernel : child Thread Terminating.\r\n");
return (void*)-1;
}
ret = pthread_join(worker[i], (void*)&result);
}
xil_printf("Xilkernel : child Thread Completing.\r\n");

return (void*)0;
}
/* The worker thread */
void* partial_sum_worker(void *arg)
{
int i, psum;
unsigned char j=0;
unsigned char key1[16],key2[16];
unsigned char input[8],*output; /* key1 for encryption and key2 for
decryption and input is 8 byte data*/
unsigned char *mes; /* buffer to hold the message before printing */
unsigned long *v;
unsigned long *k1,*k2;
unsigned long w[2],x[2];
unsigned char *k3;
unsigned char key4[8];
while(1)
{
print("\r\nImplementation of Scalable encryption algorithm.\r\n");
//serialInit();
//DisplayMesPC(mes1);
// DisplayMesPC(mes2);
DisplayMesPC(mes1);
for(i=0;i<8;i++)
{
input[i]=XUartLite_RecvByte(XPAR_UARTLITE_2_BASEADDR);
SendChar(input[i]);
}
v=(unsigned long *)&input[0];
DisplayMesPC(mes3);
for(j=0;j<16;j++)
{
key1[j]=XUartLite_RecvByte(STDIN_BASEADDRESS);
SendChar(key1[j]);
}
k1=(unsigned long *)&key1[0];
decipher(v,w,k1); // encryption
DisplayMesPC(mes4);
mes=w;
for(i=0;i<8;i++)
{
key4[i]=*mes;
mes++;
// xil_printf("%c", key2[i]);
SendChar(key4[i]);
}
print("\r\nCompletion of of Scalable encryption algorithm.\r\n");
psum = 0;
/* This is how return a value to the parent */
pthread_exit((void*)psum);
return NULL;
}
}
Key words to be known when using EDK :
BMM Block memory map.
MHS microprocessor Hardware specification file
MSS microprocessor software specification file.
ELF Executable and linkable Format.
XMP Xilinx microprocessor project
MPD Microprocessor peripheral description.
Block RAM Memory Map(BMM) Features:

A BlockRAMMemoryMap(BMM) file is designed for human readability. It is
similar to high-level computer programming languages in using the following
features:
Block structures by keywords or directives BMM maintains similar structures in
groups or blocks of data. BMM creates blocks to delineate address space , bus
access groupings ,and comments.
Symbolic name usage BMM uses names and keywords to refer to groups or
entities(improving readability), and uses names to refer to address space
groupings and BlockRAMs.
In-file documentation BMM files allow comment blocks anywhere within the
content of the file.
Implied algorithms
BMM allows you to specify data transposition in semi-graphical terms, while
alleviating the need to specify the exact details of the address-to-block RAM
algorithm. The software then infers the algorithm details for the desired mapping.
SOFT CORE PROCESSOR IMPLEMENTATION :

A soft microprocessor (also called softcore microprocessor or a soft processor) is
a microprocessor core that can be wholly implemented using logic synthesis. It can be
implemented via different semiconductor devices containing programmable logic (e.g.,
ASIC, FPGA, CPLD), including both high-end and commodity variations.
While many people put exactly one soft microprocessor on a FPGA, a sufficiently
large FPGA can hold two or more soft microprocessors, resulting in a multi-core
processor. The number of soft processors on a single FPGA is only limited by the size of
the FPGA.Some people have put dozens or hundreds of soft microprocessors on a single
FPGA.
The MicroBlaze is a soft processor core designed for Xilinx FPGAs from Xilinx.
As a soft-core processor, MicroBlaze is implemented entirely in the general-purpose
memory and logic fabric of Xilinx FPGAs.
MICROBLAZE OVERVIEW:
In terms of its instruction-set architecture, MicroBlaze is very similar to the
RISC-based DLX architecture described in a popular computer architecture book by
Patterson and Hennessy. With few exceptions, the MicroBlaze can issue a new instruction
every cycle, maintaining single-cycle throughput under most circumstances.
The MicroBlaze has a versatile interconnect system to support a variety of
embedded applications. MicroBlaze's primary I/O bus, the CoreConnect PLB bus, is a
traditional system-memory mapped transaction bus with master/slave capability. A newer
version of the MicroBlaze, supported in both Spartan-6 and Virtex-6 implementations, as
well as the 7-Series, supports the AXI specification. The majority of vendor-supplied and
third-party IP interface to PLB directly (or through an PLB to OPB bus bridge.) For
access to local-memory (FPGA BRAM), MicroBlaze uses a dedicated LMB bus, which
reduces loading on the other buses. User-defined coprocessors are supported through a
dedicated FIFO-style connection called FSL (Fast Simplex Link). The coprocessor(s)
interface can accelerate computationally intensive algorithms by offloading parts or the
entirety of the computation to a user-designed hardware module.
Many aspects of the MicroBlaze can be user configured: cache size, pipeline
depth (3-stage or 5-stage), embedded peripherals, memory management unit, and businterfaces can be customized. The area-optimized version of MicroBlaze, which uses a 3stage pipeline, sacrifices clock-frequency for reduced logic-area. The performanceoptimized version expands the execution-pipeline to 5-stages, allowing top speeds of 210
MHz (*on Virtex-5 FPGA family.) Also, key processor instructions which are rarely used
but more expensive to implement in hardware can be selectively added/removed (i.e.
multiply, divide, and floating-point ops.) This customization enables a developer to make
the appropriate design tradeoffs for a specific set of host hardware and application
software requirements.
With the memory management unit, MicroBlaze is capable of hosting operating
systems requiring hardware-based paging and protection, such as the Linux kernel.
Otherwise it is limited to operating systems with a simplified protection and virtual
memory-model: e.g. FreeRTOS or Linux without MMU support. MicroBlaze's overall
throughput is substantially less than a comparable hardened CPU-core (such as the
PowerPC440 in the Virtex-5.)
EDK(Embedded development kit):
Xilinx's EDK (Embedded Development Kit) is the development package for
building MicroBlaze (and PowerPC) embedded processor systems in Xilinx FPGAs.
Hosted in the Eclipse IDE, the project manager consists of two separate environments:
XPS and SDK.
Designers use XPS (Xilinx Platform Studio) to configure and build the hardware
specification of their embedded system (processor core, memory-controller, I/O
peripherals, etc.) The XPS converts the designer's platform specification into a
synthesizeable RTL description (Verilog or VHDL), and writes a set of scripts to

automate the implementation of the embedded system (from RTL to the bitstream-file.)
For the MicroBlaze core, the EDK normally generates an encrypted (non humanreadable) netlist, but the processor description (written in VHDL) can be purchased from
Xilinx.
The SDK handles the software that will execute on the embedded system.
Powered by the GNU toolchain (GNU Compiler Collection, GNU Debugger), the SDK
enables programmers to write, compile, and debug C/C++ applications for their
embedded system. Xilinx includes a cycle-accurate instruction set simulator (ISS), giving
programmers the choice of testing their software in simulation, or using a suitable FPGAboard to download and execute on the actual system.
MicroBlaze
Designer
Xilinx
Bits
32
Version
8.40.b
Design
RISC
Encoding
Fixed
Endianness
Big/Little
Open
No
Registers
32 x 32 bits
REAL TIME OPERATING SYSTEM

INTRODUCTION:
A system is said to be Real Time if it is required to complete its work & deliver its
services on time.
Example Flight Control System
All tasks in that system must execute on time.
There are two types of RTOS :
HARD AND SOFT REAL TIME SYSTEMS(QUALITATIVE DEFINITION ):
Hard Real Time System:
Failure to meet deadlines is fatal
example : Flight Control System
Soft Real Time System:
Late completion of jobs is undesirable but not fatal.
System performance degrades as more & more jobs miss deadlines

Online Databases
HARD AND SOFT REAL TIME SYSTEMS(OPERATIONAL DEFINITION ):
Hard Real Time System:
Validation by provably correct procedures or extensive simulation that the system always
meets the timings constraints
Soft Real Time System:
Demonstration of jobs meeting some statistical constraints suffices.
Standalone Applications
Often no OS involved
Micro controller based Embedded Systems
Some Real Time Applications are huge & complex
Multiple threads
Complicated Synchronization Requirements
File system / Network / Windowing support
OS primitives reduce the software design time
Features of RTOS :
Scheduling.
Resource Allocation.
Interrupt Handling.
Other issues like kernel size.
Scheduling Algorithms:
Clock Driven Scheduling
Weighted Round Robin Scheduling
Priority Scheduling
(Greedy / List / Event Driven).
Clock Driven:
All parameters about jobs (release time/ execution time/deadline) known in advance.
Schedule can be computed offline or at some regular time instances.
Minimal runtime overhead.
Not suitable for many applications
Weighted Round Robin:
Jobs scheduled in FIFO manner
Time quantum given to jobs is proportional to its weight
Example use : High speed switching network
QOS guarantee.
Not suitable for precedence constrained jobs.
Job A can run only after Job B. No point in giving time quantum to Job B before Job A.
Priority Scheduling :
(Greedy/List/Event Driven)
Processor never left idle when there are ready tasks
Processor allocated to processes according to priorities
Priorities
static
- at design time
Dynamic - at runtime.
Resource allocation :
Resource Allocation
1. The issues with scheduling applicable here.
2. Resources can be allocated in
I.
Weighted Round Robin
II.
Priority Based
Some resources are non preemptible

1. Example : semaphores
Priority Inversion if priority scheduling is used
XILKERNEL
OVERVIEW :
Xilkernel is a small, robust, and modular kernel. It is highly integrated with the Platform
Studio framework and is a free software library that you get with the Xilinx Embedded
Development Kit (EDK). It allows a very high degree of customization, letting users
tailor the kernel to an optimal level both in terms of size and functionality. It supports the
core features required in a lightweight embedded kernel, with a POSIX API. Xilkernel
works on both the MicroBlaze and PowerPC 405 processors. Xilkernel IPC services
can be used to implement higher level services (such as networking, video, and audio)
and subsequently run applications using these services.
Typical embedded control applications are comprised of various tasks that need
to be
performed in a particular sequence or schedule. As the number of control tasks involved

grows, it gets very hard to manually organize the sub-tasks and time-share the work that
needs to be done. The responsiveness and the capability of such an application decreases
dramatically when the complexity is increased.
Breaking down tasks as individual applications and implementing them on an
operating system (OS) is much more intuitive.
It enables the you to write code at an abstract level, instead of at a small, microcontroller
level standalone code.
Many common and legacy applications rely on OS services such as file systems, time
management, etc. Xilkernel is a thin library that provides these essential services. Porting
or using common/open source libraries (such as graphics or network protocols) may also
require some form of these OS services.
XILKERNEL FEAUTURES:
Xilkernel includes the following key features:
A POSIX API targeting embedded kernels.
Core kernel features such as:
POSIX threads with round-robin or strict priority scheduling
POSIX synchronization services - semaphores and mutex locks
POSIX IPC services - message queues and shared memory
Dynamic buffer pool memory allocation
Software timers
User level interrupt handling API
Highly robust kernel, with all system calls protected by parameter validity checks and
proper return of POSIX error codes.
Highly scalable kernel that can be accommodated into a given system through the
inclusion or exclusion of functionality as required.
Complete kernel configuration, deployment within minutes from inside of Platform
Studio
Statically creating threads that startup with the kernel.
System call interface to the kernel.
Support for creating processes out of separate executable Executable Link Files (ELF).
XILKERNEL ORGANISATION :
BUILDING XILKERNEL APPLICATIONS :

This section describes how to compile your applications on Xilkernel. Xilkernel is
organized in the form of a library of kernel functions. This leads to a simple model of
kernel linkage. To build Xilkernel, you must include Xilkernel in your software platform,
configure it appropriately, and run Libgen to generate the Xilkernel library. Your
application sources can be edited and developed separately, or as a software application
project from inside of XPS. Once you are done developing your application, to build the
final kernel image, you must link with the Xilkernel library, thus pulling in all the kernel
functionality. The Xilkernel library is generated as libxilkernel.a . Figure 2 shows this
development flow.
Internally, Xilkernel also supports the much more powerful, traditional OS like method of
linkage - separate executables. Conventional operating systems have the kernel image as
a separate file and each application that executes on the kernel as a separate file.
However, we recommend that you use the simpler, more elegant library linkage mode.
This mode is fully supported within Platform Studio and provides maximum ease of use.
It is also the best mode for debugging, downloading and bootloading. The separate
executable mode is required only by those who have advanced requirements in the form
of separate executables. The separate executable mode and its caveats are documented in
the Advanced Features section.
The following are the steps for the kernel linkage mode of application development:
Application source C files should include the file xmk.h as the first file among others.
For
example,
#include xmk.h
Defining this flag makes available certain definitions and declarations from the GNU
include files that are required by Xilkernel and applications.
Your application software project links with the library libxil.a . This library contains
the
actual kernel functions generated. Your application links with this and forms the final
kernel and application image.
Xilkernel is responsible for all first level interrupt and exception handling on both the
MicroBlaze and PowerPC processors. Therefore, you should not directly attempt to use
any of the methods of handling interrupts documented for standalone programs. Instead
refer to the section on interrupt handling for how to handle user level interrupts and
exceptions.
You can control the memory map of the kernel by using the linker script feature of the
final
software application project that links with the kernel. Automatic linker script generation
helps you here.
Your application must provide a main() which is the starting point of execution for your
kernel image. Inside your main() , you can do any initialization and setup that you need to
do. The kernel remains unstarted and dormant. At the point where your application setup
is complete and you want the kernel to start, you must invoke, xilkernel_main() which
starts off the kernel, enables interrupts and transfers control to your application processes,
as configured. Some system-level features may need to be enabled before invoking

xilkernel_main(). These are typically machine-state features such as cache enablement,
hardware exception enablement which must be "always ON" even when context
switching from application to application. Make sure that you setup such system state
before invoking xilkernel_main(). Also, you must not arbitrarily modify such systemstate in your application threads. If a context switch occurs when the system state is
modified, it may lead to subsequent threads executing without that state being enabled.
Hence, you must lock out context switches and interrupts before you modify such a state.
XILKERNEL SCHEDULING MODEL :
Xilkernel supports either priority-driven, preemptive scheduling with time slicing
(SCHED_PRIO) or simple round-robin scheduling (SCHED_RR). This is a global
scheduling policy and cannot be changed on a per-thread basis. This must be configured
statically at
kernel generation time. In SCHED_RR, there is a single ready queue and each process
context executes for a configured time slice before yielding execution to the next process
context in the queue. In SCHED_PRIO there are as many ready queues as there are
priority levels. Priority 0 is the highest priority in the system and higher values mean
lower priority.
BUILDING APPLICATIONS FOR XILKERNEL :
SUMMARY OF XILKERNEL FUNCTIONS :

int pthread_create (pthread_t thread , pthread_attr_t* attr, void* (* start_func)(void*),
void* param)
void pthread_exit (void *value_ptr)
int pthread_join (pthread_t thread , void ** value_ptr)
pthread_t pthread_self (void)
int pthread_detach (pthread_t target )
int pthread_equal (pthread_t t1, pthread_t t2)
int pthread_getschedparam (pthread_t thread, int *policy, struct sched_param *param).
int pthread_setschedparam (pthread_t thread , int policy, const struct

sched_param * param).
int pthread_attr_init (pthread_attr_t* attr)
int pthread_attr_destroy (pthread_attr_t* attr)
int pthread_attr_setdetachstate (pthread_attr_t* attr, int dstate )
int pthread_attr_getdetachstate (pthread_attr_t* attr, int * dstate )
int pthread_attr_setschedparam (pthread_attr_t* attr, struct sched_param
*schedpar )
int pthread_attr_getschedparam (pthread_attr_t* attr, struct sched_param*

schedpar )
int pthread_attr_setstack (const pthread_attr_t *attr, void *stackaddr, size_t stacksize)
int
pthread_attr_getstack
(const pthread_attr_t
*attr, void
**stackaddr, size_t
*stacksize)
pid_t get_currentPID (void)
int kill (pid_t pid )
int process_status (pid_t pid , p_stat * ps)
int yield (void)
int sem_init (sem_t * sem , int pshared, unsigned value)
int sem_destroy (sem_t* sem )
int sem_getvalue (sem_t* sem , int* value)
int sem_wait (sem_t* sem )
int sem_trywait (sem_t* sem )
int sem_timedwait (sem_t* sem , unsigned ms)
int sem_post (sem_t* sem )
sem_t* sem_open (const char* name, int oflag,...)
int pthread_setschedparam (pthread_t thread , int policy, const struct sched_param
*param).
int pthread_attr_init (pthread_attr_t* attr)
int pthread_attr_destroy (pthread_attr_t* attr)
int pthread_attr_setdetachstate (pthread_attr_t* attr, int dstate )
int pthread_attr_getdetachstate (pthread_attr_t* attr, int * dstate )
int pthread_attr_setschedparam (pthread_attr_t* attr, struct sched_param *schedpar )
THREAD MANAGEMENT:
Xilkernel supports the basic POSIX threads API. Thread creation and
manipulation is done in the exact same way as defined in POSIX. Threads are identified
by a unique thread identifier. The thread identifier is of type pthread_t. This thread
identifier is to used to uniquely identify a thread for an operation. Threads created in the
system have a kernel wrapper to which they return control to when they terminate.
Therefore a specific exit function is not required at the end of the threads code. Thread
stack is allocated automatically on behalf of the thread from a pool of Block Starting
Symbol (BSS) memory that is statically allocated depending on the maximum number of
threads in the system. You can also assign a custom piece of memory as the stack for each
thread that they create dynamically. The entire thread module is optional and can be
configured in or out as a part of the software specification.
HARDWARE RESULTS :
The below figures show the hardware configuration for communication between
two fpgas. In this communication we require two pcs two fpgas and three rs-232 cables.
RS232 (DTE to DCE cable) is used for communication between fpga and pc. RS232
(DTE to DTE cable) is used for communication between two fpgas. It is used to transfer
data from one fpga to another fpga.
The two different cables and its connections with fpga are shown in the below figures.
I)
WITHOUT RTOS :
II)
WITH RTOS :
Open Xilinx 13.2 version project navigator and create a new project like micro_fm.
Add new source select embedded processor and give a name like system.
And then next we get the Xilinx platform studio window and we get a message like do
you want to create a base system builder,click yes.
Do the next process which is showed as in print screens format.
Do the next process.
And then click next button(only for single processor).
Then click next.
Here we should remove the components which we dont want in our Microblaze part.only keep
ddr ram,flash memory,leds,rs232 components and controllers.click next.
Here select 2kb memory in both the sides,and one side flash and another side ddr_sdram.and
dont select both sides same memory we may get error.and then click next.
Click next.
Here we can get the ucf file of fpga board which we are using.
Ucf filecopy this ucf file and add in our project ucf file.when we want to add.
After that we should create a net list so go to hardware and generate net list.
We get the message like done.(net list generated).
Next close the xps.

Next close the xps.
We get the error like continue to xps and then click ok and close.
Next generate top level hdl source to our project.(its tool generated core).
Process will goes on.
And then we get the core like system_top(vhdl file).
FUTURE SCOPE:
We can implement the same algorithm in high end FPGA boards which is having high
speed as well as for more speed applications we can implement this application by using
power pc type of processor.
For more security for communication we can go for other encryption algorithms. or
If we increased the key bit length then it would be critical to decode the information for
the third party member other than transmitter and receiver.
CONCLUSION:
Implementing a microblaze soft core processor on the FPGA.
The verification of l communication between two FPGAs(chip to chip communication).
And here the communication is done in secured manner by applying tiny encryption
algorithm .
This is all done on RTOS(real time operating system) environment.
Verifying the input and output data.
APPLICATIONS:
The Xilinx Microblaze soft processor and PowerPC hard processor are widely
used in FPGA based CSOC (configurable system on chip) applications.
Mainly in communication systems our proposed solution can be very usefull in
terms of speed as well as in real time environment.
We can use this type applications in processor based solutions.

And we can use at aviation, navigation and other equipment
Software defined radios for military applications
ADVANATGES:
High speed devices such as serial ADC/DACs can be interfaced to Microblaze
Full digital techniques can give room for full reconfigurability of the MODEM for
different specifications
FPGA based implantation will result in extremely high speed and also can provide
room for adding additional hardware blocks.
Low power solution
High reliability
DISADVANATGES:
If we Compared to the hard core processor speed is some what less.

Cost is some what high because we require two fpga kits for to provide end-toend communication.
REFERENCES
[I] S. Sau , C. Pal and A Chakrabarti "Design and Implementation of Real Time Secured
RS232 Link for Multiple FPGA Communication, Proc. Of International Conference on
Communication, Computing & Security,201 I, ISBN - 978-1-4503-0464-1.
[2] C. D. Walter. August 1999. Montgomery's Multiplication Technique: How to Make It

Smaller and Faster. Cryptographic Hardware and Embedded Systems, Lecture Notes in
Computer Science, Springer. No. 1717. pp. 80-93.
[3] A Mazzeo, L. Romano, G. P. Saggese and N. Mazzocca. 2003. FPGABased
Implementation ofa Serial RSA Processor. Design. Proceedings of the conference on
Design, Automation and Test in Europe - Volume I. ISBN:O-7695-1870-2.
[4] xilkernel_v3.00.pdf on www.xilinx.com.
[5] R. L. Rivest et al. 1978. A Method for Obtaining Digital Signatures and Public-Key
Cryptosystems. Communications of the ACM. Vol. 21. pp. 120-126.
[6] Cryptography & Network Security By Behrouz AForouzan.
[7] Montgomery Algorithm for Modular Multiplication Professor Dr. D. J. Guan ,August
25, 2003.
[8]RSA & Public Key Cryptography in FPGAs, John Fry, Martin Langhammer Altera
Corporation -Europe
[9] A. Tenca, C. Koc. 1999. A Scalable Architecture for Montgomery Multiplication.
Cryptographic Hardware and Embedded Systems, Lecture Notes in Computer Science,
No. 1717, pp. 94-108.
[10]. A. Tenca, G. Todorov, C. Koc. May 2001. High-radix design of a scalable modular
multiplier. Cryptographic Hardware and Embedded Systems, Lecture Notes in
Computer Science, Springer. No. 2162. pp. 185-201.
[II] High-Speed RSA Implementation, Cetin Kaya Koc, November 1994, Version 2.0,
ftp://ftp.rsa.comlpub/pdfs/tr20I.pdf.
[12]] http://csrc.nist.gov/publications/fips/fipsI97Ifips-197.pdf.
[13] http://www.design-reuse.comlarticlesIl3981 /fpga-implementation-of-aes-encryptio
n-and-decryptio n. html.
[14] B. Schneier. 1996. Applied Cryptography, Protocols, Algorithms, and
Source Code in C, John Wiley and Sons Inc. 2nd Edition. New York, U.S.A.
[15] G.B. Arfken, D.F. Griffing, D.C. Kelly and J priest. University Physics
San Diego, CA Harcourt Brace, Jovanovich Publishers, 1989.
[16] http://www.techmaish.comlmaximum-internet-speed-available-in-theworld/.
[17] 4.6.3 of D. E. knuth , The Art of Computer Programming Seminumeritical

Algorithm, Volume 2, Reading M.A. : Addison Wasley, Second Edition, 1981.
[18] Qing Li, Caroline Yao "Real-Time Conceptsfor Embedded Systems".
[19] Tran Nguyen Bao Anh*t, Su-Lim TantSurvey and performance evaluation of realtime operating systems (RTOS) for small microcontrollers", *Renesas Technology
Singapore, Singapore Engineering Centre, Singapore 098632, t School of Computer
Engineering, Nanyang Technological University, Singapore 639708.
[20] Awais M. Kamboh, Adithya H. Krishnamurthy and Jaya Krishna K. Vallabhaneni
"Demonstration of Multitasking using ThreadX RTOS on Microblaze and PowerPC"
[21] Operating system for Xilinx embedded processor" at http://www.em.avnet.com.
[22] Sarat Yoowattana, Chinnapat Nantajiwakornchai, Manas Sangworasil "A Design of
Embedded DMX512 Controller using FPGA and XILKernel" ,2009 IEEE Symposium on
Industrial Electronics and Applications (lSIEA 2009), October 4-6,2009, Kuala Lumpur,
Malaysia.
[23] http://www.xilinx.com
[24]] M. Ibrahimy, M.B.Reaz, K.Asaduzzaman and S.Hussain. 2007. FPGA
Implementation of RSA Encryption Engine with Flexible Key Size. International
Journal of Communications. Issue 3. Volume I.
Open Xilinx 13.2 version project navigator and create a new project like micro_fm.
Add new source select embedded processor and give a name like system.
And then next we get the Xilinx platform studio window and we get a message like do
you want to create a base system builder,click yes.
Do the next process which is showed as in print screens format.
Do the next process.
And then click next button(only for single processor).
Then click next.
Here we should remove the components which we dont want in our Microblaze part.only keep
ddr ram,flash memory,leds,rs232 components and controllers.click next.
Here select 2kb memory in both the sides,and one side flash and another side ddr_sdram.and
dont select both sides same memory we may get error.and then click next.
Click next.
Here we can get the ucf file of fpga board which we are using.
Ucf filecopy this ucf file and add in our project ucf file.when we want to add.
Next close the xps.
We get the error like continue to xps and then click ok and close.
Next generate top level hdl source to our project.(its tool generated core).
Process will goes on.
And then we get the core like system_top(vhdl file).
System_top vhdl file.
Add new source like microblaze.
Select vhdl module and create with the name microblaze.
We will get the vhdl file like above.
Copy the line from the system_top core like which we showed in the print screen.
And paste it into the main module.
Call the system_top module as a component in our main module(microblaze).
We will get like this.(component calling).
Next port mapping process in our main module.copy the instance of the system from the
system_top module and paste into the main module(microblaze).
Paste the instance into the main module(microblaze).
And remove the parts which we are showing in the print screen.
We will get like this.
Change the name there.
Write the name which we want to replace.
Call a signal with the name led_port_data.
Replace that signal which we want in order
Transfer led_port_data into the inv_serial_port_data.
Save the mail module.
In the left side we observe the modules format.
Add new source(ucf file).
Select the ucf file with the name micro.
Copy the ucf file which we get in the Xilinx platform studio and paste here.
In this ucf file we should change the name or replace the fpga_0_LEDs_8Bit_GPIO_IO_O_pin
with the inv_seril_port_data.of 8 pins.
Save the ucf file.
Next start the synthesis format means run the main module.
It takes some more time to complete.
We will get the window like this.
Next export the hardware with bitstream(click on the embedded processor,we will get the down
options).
Process is going on.
We should select our path where we are creating the project and in that we should select the
folder name SDK which is in the system folder in our project.
Like this we are selecting the path
Process is going on.
We will get the warning just click ok.
Like this the window will be opend.
Now got to file and open Xilinx c project.
Select the above option.
Now got to file and open Xilinx c project.
Next click finish.
Process will goes on..
Open that one.
And open another c file
Do the modifications in the program.
And also in the programe.And save those c files.
Open terminal software on the desktop.
This window will be opend.
Select the com port which your serial cabel is connected to your pc.
And then connect that port.
Dump the program into the fpga.
Program fpga.
The program will be dumped into the fpga.
Click run in the Xilinx sdk c/c++ editor.
After that in terminal window we will get like this.
If we enter the characters we will get the corresponding frequencies.
Like this the microblaze softcore processor will gives the commands from the pc to the fpga.

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CHAPTER 1

microprocessors. FPGAs combine the programmability of

processors with the performance of custom hardware. As FPGAs can provide a

flexibility, they becomes the primary source of

computation in many critical embedded systems.

TINY ENCYPTION ALGORITHM:

structure with a suggested 64 rounds, typically implemented in pairs termed

constant, 2654435769 or 9E3779B916 is chosen to be 232/, where is the golden

P = (Left[0], Right[0]) and the cipher text is C = (Left[64],

Flow chart for Decryption routine

SOFT CORE PROCESSOR IMPLEMENTATION :

2.1 FPGA Design Considerations

FPGA design flow is a three-step process consisting of design

HDL is a parallel process.

Fig (2.1): FPGA design flow

automation to describe digital and mixed-signal systems such as field-programmable gate

Fig (2.2): Top-Down Design Flow with Precision RTL Synthesis

2.1.2 VHDL and Synthesis

reproduced with guaranteed accuracy. Delay time modeling in VHDL is an example.

2.1.3 Evolution of Programmable Logic Devices

Fig (2.3) Structure of a PAL

Field-Programmable Gate Arrays (FPGAs). Like MPGAs, FPGAs comprise an

Fig (2.4): structure of an FPGA

2.1.4 Xilinx SRAM-based FPGAs

Fig (2.5):- Xilinx XC4000 Configurable Logic Block (CLB).

2.2 Spartan-3E FPGA Family

display/projection, and digital television equipment.The Spartan-3E family is a superior

2.2.1 Spartan -3E Architectural Overview

Fig (2.6): Spartan-3E Family Architecture

2.2.2 Spartan -3E Configuration

2.3 FPGA Design and Programming Tool Flow

Fig (2.7): Xilinx Design Flow

2.5.3 Design Flow

Fig (2. 19): ChipScope Pro Tools Design Flow

is part of chapter deals with the implementation flow specifying the

significance of various properties, reports obtained and simulation waveforms of

Reporting:-This is enumerating input constraint violations and placing them into an

2.6.3.2 Power Reduction

2.6.4 .1 Slice Utilization Ratio

As this project is a complex design the option high is selected.

Fig- Communication between two fpgas using RTOS

considered as a major platform for high performance embedded applications as it

Release 13.2 - xst O.61xd (nt)

---- Source Options

Write Timing Constraints

Reading core <xps_intc_0_wrapper.ngc>.

Optimizing unit <system_top_top> ...

_r1> in Unit <DDR_SDRAM> is equivalent to the following FF/Latch :

INFO:Xst:2260 - The FF/Latch

<FLASH> is equivalent to the following FF/Latch :

_r1> in Unit <DDR_SDRAM> is equivalent to the following FF/Latch :

6.114ns (3.614ns logic, 2.500ns route)

Cell:in->out fanout Delay Delay Logical Name (Net Name)

end scope: 'mdm_0'

(89.6% logic, 10.4% route)

Xilinx Platform Studio (XPS) is the development environment used for

The Software Development Kit (SDK) is an integrated development

EDK is designed to assist in all phases of the embedded design process

The steps to develop an embedded processor are :

1)PROJECT INFORMATION AREA

XPS. Use Project Navigator for simulation

:Contains intermediate files generated by XPS and other tools

void decipher(const unsigned long const v,unsigned long const w, const