ECE 5/410 Digital IC Design

Digital Design using Logical Effort

Vishal Saxena
(vishalsaxena@boisetstate.edu)

Jan 20, 2014

Vishal Saxena

Outline

Logical Effort
Delay in a Logic Gate
Multistage Logic Networks
Choosing the Best Number of Stages
Example
Summary

Jan 20, 2014

Vishal Saxena

Introduction

Chip designers face a bewildering array of choices

What is the best circuit topology for a function?
How many stages of logic give least delay?
How wide should the transistors be?

???

Logical effort is a method to make these decisions

Uses a simple model of delay
Allows back-of-the-envelope calculations
Helps make rapid comparisons between alternatives
Emphasizes remarkable symmetries

Jan 20, 2014

Vishal Saxena

Example

Ben Bitdiddle is the memory designer for the Motoroil 68W86, an embedded
automotive processor. Help Ben design the decoder for a register file.

Decoder specifications:
16 word register file
Each word is 32 bits wide
Each bit presents load of 3 unit-sized transistors
True and complementary address inputs A[3:0]
Each input may drive 10 unit-sized transistors
Ben needs to decide:
How many stages to use?
How large should each gate be?
How fast can decoder operate?

A[3:0] A[3:0]

Vishal Saxena

16

Register File

16 words

4:16 Decoder

Jan 20, 2014

32 bits

Delay in a Logic Gate

Express delays in process-independent unit

Delay has two components: d = f + p
d
f: effort delay = gh (a.k.a. stage effort)
d = abs

Again has two components

= 3RC
g: logical effort
3 ps in 65 nm process
Measures relative ability of gate to deliver current
60 ps in 0.6 m process
g 1 for inverter
h: electrical effort = Cout / Cin
Ratio of output to input capacitance
Sometimes called fanout
p: parasitic delay
Represents delay of gate driving no load
Set by internal parasitic capacitance

Jan 20, 2014

Vishal Saxena

Delay Plots

=f+p
= gh + p

What about
NOR2?

2-input
NAND

Normalized Delay: d

Inverter

g=1
p=1
d=h+1

4
3

g = 4/3
p=2
d = (4/3)h + 2

Effort Delay: f

2
1

Parasitic Delay: p
0
0

Electrical Effort:
h = Cout / Cin

Jan 20, 2014

Vishal Saxena

Computing Logical Effort

DEF: Logical effort is the ratio of the input
capacitance of a gate to the input capacitance of
an inverter delivering the same output current.
Measure from delay vs. fanout plots
Or estimate by counting transistor widths
2

2
A

Y
1
Cin = 3
g = 3/3

Jan 20, 2014

2
Cin = 4
g = 4/3
Vishal Saxena

4
Y
1

Cin = 5
g = 5/3

Catalog of Gates
Logical effort of common gates

Gate type

Number of inputs
1

NAND

4/3

5/3

6/3

(n+2)/3

NOR

5/3

7/3

9/3

(2n+1)/3

4, 4

6, 12, 6

8, 16, 16, 8

Inverter

Tristate / mux
XOR, XNOR

Jan 20, 2014

Vishal Saxena

Catalog of Gates
Parasitic delay of common gates
In multiples of pinv (1)
Gate type

Number of inputs
1

NAND

NOR

2n

Inverter

Tristate / mux
XOR, XNOR

Jan 20, 2014

Vishal Saxena

Example: Ring Oscillator

Estimate the frequency of an N-stage ring
oscillator

Logical Effort: g =
Electrical Effort: h =
Parasitic Delay: p =
Stage Delay:
d=
Frequency:
fosc=

Jan 20, 2014

Vishal Saxena

10

Example: Ring Oscillator

Estimate the frequency of an N-stage ring
oscillator

Logical Effort: g = 1
Electrical Effort: h = 1
Parasitic Delay: p = 1
Stage Delay:
d=2
Frequency:
fosc = 1/(2*N*d) = 1/4N

Jan 20, 2014

Vishal Saxena

31 stage ring oscillator in

0.6 m process has
frequency of ~ 200 MHz

11

Example: FO4 Inverter

Estimate the delay of a fanout-of-4 (FO4) inverter
d

Logical Effort:

g=

Electrical Effort:
Parasitic Delay:
Stage Delay:

h=
p=
d=

Jan 20, 2014

The FO4 delay is about

300 ps in 0.6 m process
15 ps in a 65 nm process

Vishal Saxena

12

Example: FO4 Inverter

Estimate the delay of a fanout-of-4 (FO4) inverter
d

Logical Effort:

g=1

Electrical Effort:
Parasitic Delay:
Stage Delay:

h=4
p=1
d=5

Jan 20, 2014

The FO4 delay is about

300 ps in 0.6 m process
15 ps in a 65 nm process

Vishal Saxena

13

Multistage Logic Networks

Logical effort generalizes to multistage networks
Path Logical Effort
G = gi

Path Electrical Effort H = Cout-path

Cin-path

=
F

Path Effort
10
g1 = 1
h1 = x/10

Jan 20, 2014

x
g2 = 5/3
h2 = y/x

=
f g h

y
g3 = 4/3
h3 = z/y

Vishal Saxena

i i

z
g4 = 1
h4 = 20/z

20

14

Multistage Logic Networks

Logical effort generalizes to multistage networks
Path Logical Effort
G = gi

Path Electrical Effort H = Cout path

Cin path

Path Effort

=
F

=
f g h

i i

Can we write F = GH?

Jan 20, 2014

Vishal Saxena

15

Paths that Branch

No! Consider paths that branch:
G

H
GH
h1
h2
F

=
=
=
=
=

Jan 20, 2014

15

90

5
15

Vishal Saxena

90

16

Paths that Branch

No! Consider paths that branch:
G

=1

H
GH
h1
h2
F

= 90 / 5 = 18
= 18
= (15 +15) / 5 = 6
= 90 / 15 = 6
= g1g2h1h2 = 36 = 2GH

Jan 20, 2014

15

90

Vishal Saxena

15

90

17

Branching Effort
Introduce branching effort
Accounts for branching between stages in path

b=

Con path + Coff path

Con path

B = bi

Note:

= BH

Now we compute the path effort

F = GBH
Jan 20, 2014

Vishal Saxena

18

Multistage Delays
Path Effort Delay

DF = f i

Path Parasitic Delay

P = pi

Path Delay

=
D

Jan 20, 2014

d
=

Vishal Saxena

DF + P

19

Designing Fast Circuits

=
D

d
=
i

DF + P

Delay is smallest when each stage bears same effort

=
f g=
F
i hi

1
N

Thus minimum delay of N stage path is

This is a key result of logical effort

Find fastest possible delay
Doesnt require calculating gate sizes

Jan 20, 2014

Vishal Saxena

20

Designing Fast Circuits

=
D

d
=
i

DF + P

Delay is smallest when each stage bears same effort

=
f g=
F
i hi

1
N

Thus minimum delay of N stage path is

1
N

=
D NF + P
This is a key result of logical effort
Find fastest possible delay
Doesnt require calculating gate sizes

Jan 20, 2014

Vishal Saxena

21

Gate Sizes
How wide should the gates be for least delay?
Cout

=
f gh
= g Cin

gi Couti
Cini =
f
Working backward, apply capacitance transformation to
find input capacitance of each gate given load it drives.
Check work by verifying input cap spec is met.

Jan 20, 2014

Vishal Saxena

22

Example: 3-stage path

Select gate sizes x and y for least delay from A to B

x
y

x
A

Jan 20, 2014

45

Vishal Saxena

45

23

Example: 3-stage path

x
x
A

Logical Effort
Electrical Effort
Branching Effort
Path Effort
Best Stage Effort
Parasitic Delay
Delay
Jan 20, 2014

y
45
y

45

G = (4/3)*(5/3)*(5/3) = 100/27
H = 45/8
B=3*2=6
F = GBH = 125
=
f

=
F 5

P=2+3+2=7
D = 3*5 + 7 = 22 = 4.4 FO4
Vishal Saxena

24

Example: 3-stage path

Work backward for sizes

y = 45 * (5/3) / 5 = 15
x = (15*2) * (5/3) / 5 = 10

x
y

x
A P:
84
N: 4

Jan 20, 2014

45
45

P:
x 4
N: 6

Vishal Saxena

P:
y 12
N: 3

45
45

25

Best Number of Stages

How many stages should a path use?
Minimizing number of stages is not always fastest

Example: drive 64-bit datapath with unit inverter

Initial Driver

2.8

16

D = NF1/N + P
= N(64)1/N + N

23

64

Datapath Load
N:
f:
D:

Jan 20, 2014

Vishal Saxena

1
64
65

64
2
8
18

64
3
4
15
Fastest

64
4
2.8
15.3

26

Derivation
Consider adding inverters to end of path
How many give least delay?
n1

D= NF + pi + ( N n1 ) pinv
1
N

Logic Block:
n1Stages
Path Effort F

N - n1 ExtraInverters

i =1

1
1
1
D
=
F N ln F N + F N + pinv =
0
N

Define best stage effort = F

1
N

pinv + (1 ln ) =
0
Jan 20, 2014

Vishal Saxena

27

Best Stage Effort

pinv + (1 ln ) =
0 has no closed-form solution
Neglecting parasitics (pinv = 0), we find = 2.718 (e)
For pinv = 1, solve numerically for = 3.59

Jan 20, 2014

Vishal Saxena

28

Sensitivity Analysis
How sensitive is delay to using exactly the best number
of stages?
D(N) /D(N)

1.6

1.51

1.4

1.26

1.2

1.15

1.0
( =2.4)

(=6)

0.0
0.5

0.7

1.0

1.4

2.0

N/ N

2.4 < < 6 gives delay within 15% of optimal

We can be sloppy!
I like = 4
Jan 20, 2014

Vishal Saxena

29

Example, Revisited

Ben Bitdiddle is the memory designer for the Motoroil 68W86, an embedded
automotive processor. Help Ben design the decoder for a register file.

Decoder specifications:
16 word register file
Each word is 32 bits wide
Each bit presents load of 3 unit-sized transistors
True and complementary address inputs A[3:0]
Each input may drive 10 unit-sized transistors
Ben needs to decide:
How many stages to use?
How large should each gate be?
How fast can decoder operate?

A[3:0] A[3:0]

Vishal Saxena

16

Register File

16 words

4:16 Decoder

Jan 20, 2014

32 bits

30

Number of Stages
Decoder effort is mainly electrical and branching
Electrical Effort:
H = (32*3) / 10 = 9.6
Branching Effort:
B=8
If we neglect logical effort (assume G = 1)
Path Effort:
F = GBH = 76.8
Number of Stages:

N = log4F = 3.1

Try a 3-stage design

Jan 20, 2014

Vishal Saxena

31

Gate Sizes & Delay

Logical Effort: G = 1 * 6/3 * 1 = 2
Path Effort:
F = GBH = 154
1/ 3
Stage Effort: =
f F=
5.36
Path Delay:
D= 3 f + 1 + 4 + 1= 22.1
Gate sizes:
z = 96*1/5.36 = 18 y = 18*2/5.36 = 6.7
A[3] A[3]
10

10

A[2] A[2]
10

10

A[1] A[1]
10

10

A[0] A[0]
10

10

word[0]
96 units of wordline capacitance

Jan 20, 2014

word[15]

Vishal Saxena

32

Comparison
Compare many alternatives with a spreadsheet
D = N(76.8 G)1/N + P

Jan 20, 2014

Design
NOR4

N
1

G
3

P
4

D
234

NAND4-INV

29.8

NAND2-NOR2

20/9

30.1

INV-NAND4-INV
NAND4-INV-INV-INV

3
4

2
2

6
7

22.1
21.1

NAND2-NOR2-INV-INV

20/9

20.5

NAND2-INV-NAND2-INV

16/9

19.7

INV-NAND2-INV-NAND2-INV

16/9

20.4

NAND2-INV-NAND2-INV-INV-INV

16/9

21.6

Vishal Saxena

33

Review of Definitions
Term

Stage

Path

number of stages

logical effort

G = gi

electrical effort

h=

Cout
Cin

H=

branching effort

b=

Con-path +Coff-path
Con-path

B = bi

effort

f = gh

F = GBH

effort delay

DF = f i

parasitic delay

P = pi

delay

d= f + p

D
=

Jan 20, 2014

Vishal Saxena

Cout-path
Cin-path

d
=
i

DF + P

34

Method of Logical Effort

1)
2)
3)
4)
5)

Compute path effort

Estimate best number of stages
Sketch path with N stages
Estimate least delay
Determine best stage effort

N = log 4 F
1
N

=
D NF + P
f = F N1
gi Couti
Cini =
f

6) Find gate sizes

Jan 20, 2014

F = GBH

Vishal Saxena

35

Limits of Logical Effort

Chicken and egg problem
Need path to compute G
But dont know number of stages without G

Simplistic delay model

Neglects input rise time effects

Interconnect
Iteration required in designs with wire

Maximum speed only

Not minimum area/power for constrained delay
Jan 20, 2014

Vishal Saxena

36

Summary
Logical effort is useful for thinking of delay in circuits

Numeric logical effort characterizes gates

NANDs are faster than NORs in CMOS
Paths are fastest when effort delays are ~4
Path delay is weakly sensitive to stages, sizes
But using fewer stages doesnt mean faster paths
Delay of path is about log4F FO4 inverter delays
Inverters and NAND2 best for driving large caps

Provides language for discussing fast circuits

But requires practice to master

Jan 20, 2014

Vishal Saxena

37