Computer Instructions P: CSE 410 Spring 2009 CSE 410, Spring 2009 Computer Systems

Computer
p
Instructions
CSE 410,
410 Spring 2009
Computer Systems
http://www.cs.washington.edu/410
3/31/2009
cse410-02-instructions 2006-09 Perkins, DWJohnson & University of Washington
Readingg and References

Readings
Computer
C
O
Organization
i i andd Design
D i
Section 2.1, Introduction

Section 2.2,
2 2 Operations of the Computer Hardware
Section 2.3, Operands of the Computer Hardware
Section 2.5,
2 5 Representing Instructions
Other References
See MIPS Run,
Run D Sweetman
section 8.6, Instruction encoding
section 10.2,
10 2 Endianness
3/31/2009
Todays
y Agenda
g
//pick
p a language
g g
A = B + C;
//say, c
Lets convert this to a much more primitive
programming
i language
l
Assume A,B,C are associated with $t0,$t1,$t2
add $t0,, $t1,, $t2

3/31/2009
#say,
y, MIPS
A veryy simple
p organization
g
program counter
main
memoryy
registers
functional units
3/31/2009
Instructions in main memoryy

Instructions are stored in main memory
y
each byte in memory has a number (an address)
Program counter (PC) points to the next

instruction
All MIPS instructions are 4 bytes long,
long and so
instruction addresses are always multiples of 4
Program addresses are 32 bits long

232 = 4,294,967,296 = 4 GigaBytes (GB)
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Instructions in memoryy
...
...
...
3/31/2009
...
...
instruction
addresses
20
16
12
8
4
0
instruction value
instruction value
Fetch/Execute Cycle
y
Operation of a computer:
while (processor not halted) {
fetch instruction at memory location (PC)
PC = PC + 4 (increment to point to next instruction)
execute fetched instruction
}
Instructions execute sequentially unless a jump or

branch changes the PC to cause the next instruction to
be fetched from somewhere else
3/31/2009
Some common storage

g units
Note that a byte is 8 bits on almost all machines.
The definition of word is less uniform (4 and 8 bytes are common today).
A nibble is 4 bits (half a byte!)
3/31/2009
unit
it
# bits
bit
byte
half-word
16
word
32
double word
64
Alignment
g
An object
j in memoryy is aligned
g
when its
address is a multiple of its size
Byte: always aligned
Halfword: address is multiple of 2
Word:
W d address
dd
iis multiple
lti l off 4
Double word: address is multiple of 8
Alignment simplifies load/store hardware
And is required
q
by
y MIPS,, but not x86
3/31/2009
System
y
organization
g
so far
instructions
i
t
ti
and
d
data
program counter
increments by 4
main
memory
32-bit
instructions
registers
functional units
3/31/2009
10
MIPS Registers
g
32 bits wide
32 bits is 4 bytes
same as a word in memoryy
signed values from -231 to +231-1
unsigned values from 0 to 232-11
easy to access and manipulate

32 registers (not related to being 32 bits wide)
on chip, so very fast to access
3/31/2009
11
Register
g
addresses
32 ggeneral purpose
p p
registers
g
how many bits does it take to identify a
register?
5 bits, because 25 = 32
32 registers is a compromise selection

more would require more bits to identify & cost
more to save/restore when switching processes
fewer would be harder to use efficiently
3/31/2009
12
Register
g
numbers and names
number
name
usage
zero
always
l
returns 0
at
2-3
v0, v1
values returned by procedures
4-7
a0-a3
first few procedure arguments
8-15, 24, 25
t0-t9
temps - can use without saving
16-23
s0-s7
temps - must save before using
26,27
k0, k1
28
gp
global pointer
29
sp
stack pointer
30
fp or s8
frame pointer
31
ra
3/31/2009
reserved for use as assembler temporary
reserved for kernel use - may change at any time
return address from procedure
13
How are registers

g
used?
Many
y instructions use 3 registers
g
2 source registers
g
1 destination register
For example
add $t1, $a0, $t0
add a0 and t0 and put result in t1
add $t1,$zero,$a0
move contents of a0 to t1 (t1 = 0 + a0)
3/31/2009
14
R-format instructions: 3 registers

g
32 bits available in the instruction
15 bits for the three 5-bit register numbers
The remaining 17 bits are available for
specifying the instruction
66-bit
bit op code - basic instruction identifier
5-bit shift amount (25 = 32)
6-bit
6 bit function
f ti code
d
3/31/2009
15
R-format fields
op code
d
6 bits
source 1 source 2
5 bits
5 bits
d t
dest
shamt
h t
f
function
ti
5 bits
5 bits
6 bits
some common R-format

R format instructions
3/31/2009
arithmetic: add, sub, mult, div

l i l and,
logical:
d or, sll,
ll srll
comparison: slt (set on less than)
jump through register: jr
16
Bits are jjust bits

The bits mean whatever the designer
g
says
y they
y
mean when the ISA is defined
How many possible 33-register
register instructions are
there?
217 = 131,072
131 072
includes all values of op code, shamt, function
As the ISA develops over the years

years, the
encoding tends to become less logical
3/31/2009
17
System
y
organization
g
again
g
instructions
i
t
ti
and
d
data
program counter
increments by 4
main
memory
32-bit
instructions
registers 32
32
bits wide
in number
functional units
implement
p
instructions
3/31/2009
18
Transfer from memoryy to register

g
Load instructions
word:
lw
half word: lh
lh
lhu
byte:
lb
lbu
rt,
rt,
rt,
rt,
rt,
address
address
address
dd
address
address
signed load => sign bit is extended into the

upper bits of destination register
unsigned load => 0 in upper bits of register
3/31/2009
19
Transfer from register

g
to memory
y
Store instructions
word:
3/31/2009
sw
rt, address
half word: sh
rt, address
byte:
rt, address
sb
20
The address term

There is one basic addressing
g mode:
offset + base register value
Offset is 16 bits ( 32 KB)

Load word pointed to by s0, add t1, store
lw
add
sw
3/31/2009
$t0,0($s0)
$t0
0($s0)
$t0,$t0,$t1
$ , ($ )
$t0,0($s0)
21
I-format fields
op
p code
6 bits
base reg
g src/dest
5 bits
5 bits
offset or immediate value

16 bits
Th
The contents off the
h base
b
register
i
andd the
h
offset value are added together to generate
th address
the
dd
for
f the
th memory reference
f
Can also use the 16 bits to specify an
immediate value, rather than an address
3/31/2009
22
Instructions and Data flow

instructions and
data
program counter
increments by 4
main
memoryy
instructions
and data
registers 32
32
bits wide
in number
functional units
implement instructions
3/31/2009
23
The eye
y of the beholder
Bit p
patterns have no inherent meaning
g
A 32-bit word can be seen as
3/31/2009
a signed integer ( 2 Billion)

an unsigned integer or address pointer (0 to 4GB)
a single precision floating point number
four 1-byte characters
an instruction
24
Big-endian,
g
, little-endian
A 32-bit word in memory
y is 4 bytes
y longg
But which byte is which address?
Consider the 32-bit
32 bit number 0x01234567
four bytes: 01, 23, 45, 67
mostt significant
i ifi t bits
bit are 0x01
0 01
least significant bits are 0x67
3/31/2009
25
Data in memoryy bigg endian

Big endian - most significant bits are in byte 0 of the word
...
...
...
3/31/2009
...
...
12
8
4
0
01
23
45
67
byte # contents
7
6
5
4
67
45
23
01
b t offsets
byte
ff t
26
Data in memoryy little endian

Little endian - least significant bits are in byte 0 of the word
...
...
...
3/31/2009
...
...
12
8
4
0
01
23
45
67
byte # contents
7
6
5
4
01
23
45
67
b t offsets
byte
ff t
27

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Computer

cse410-02-instructions 2006-09 Perkins, DWJohnson & University of Washington

Readingg and References

Section 2.1, Introduction

cse410-02-instructions 2006-09 Perkins, DWJohnson & University of Washington

add $t0,, $t1,, $t2

cse410-02-instructions 2006-09 Perkins, DWJohnson & University of Washington

cse410-02-instructions 2006-09 Perkins, DWJohnson & University of Washington

Instructions in main memoryy

Program counter (PC) points to the next

Program addresses are 32 bits long

cse410-02-instructions 2006-09 Perkins, DWJohnson & University of Washington

cse410-02-instructions 2006-09 Perkins, DWJohnson & University of Washington

Instructions execute sequentially unless a jump or

cse410-02-instructions 2006-09 Perkins, DWJohnson & University of Washington

Some common storage

A nibble is 4 bits (half a byte!)

cse410-02-instructions 2006-09 Perkins, DWJohnson & University of Washington

cse410-02-instructions 2006-09 Perkins, DWJohnson & University of Washington

cse410-02-instructions 2006-09 Perkins, DWJohnson & University of Washington

easy to access and manipulate

cse410-02-instructions 2006-09 Perkins, DWJohnson & University of Washington

32 registers is a compromise selection

cse410-02-instructions 2006-09 Perkins, DWJohnson & University of Washington

values returned by procedures

first few procedure arguments

temps - can use without saving

temps - must save before using

reserved for use as assembler temporary

reserved for kernel use - may change at any time

return address from procedure

cse410-02-instructions 2006-09 Perkins, DWJohnson & University of Washington

How are registers

cse410-02-instructions 2006-09 Perkins, DWJohnson & University of Washington

R-format instructions: 3 registers

cse410-02-instructions 2006-09 Perkins, DWJohnson & University of Washington

some common R-format

arithmetic: add, sub, mult, div

cse410-02-instructions 2006-09 Perkins, DWJohnson & University of Washington

Bits are jjust bits

As the ISA develops over the years

cse410-02-instructions 2006-09 Perkins, DWJohnson & University of Washington

cse410-02-instructions 2006-09 Perkins, DWJohnson & University of Washington

Transfer from memoryy to register

signed load => sign bit is extended into the

cse410-02-instructions 2006-09 Perkins, DWJohnson & University of Washington

Transfer from register

cse410-02-instructions 2006-09 Perkins, DWJohnson & University of Washington

The address term

Offset is 16 bits ( 32 KB)

cse410-02-instructions 2006-09 Perkins, DWJohnson & University of Washington

offset or immediate value

cse410-02-instructions 2006-09 Perkins, DWJohnson & University of Washington

Instructions and Data flow

cse410-02-instructions 2006-09 Perkins, DWJohnson & University of Washington

a signed integer ( 2 Billion)

cse410-02-instructions 2006-09 Perkins, DWJohnson & University of Washington

cse410-02-instructions 2006-09 Perkins, DWJohnson & University of Washington