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Fault Simulation
Fault Simulation
y RandomFaultSampling
Wh t iis ffault
What
lt simulation?
i l ti ?
Circuit
Ci
i
Testpatterns
Faultmodel
FFault
lt
Simulator
Faultyoutputs
Faulty
outputs
Undetectedfaults
Faultcoverage
Time Complexity
Proportional to
n: Circuit size, number of logic gates
p: Number of test patterns
f : Number of modeled faults
Complexity=P*F*G~O(G3)withsinglesafaults
Complexityishigherthanlogicsimulation,O(G2),butismuchlower
thantestpatterngeneration.
h
Inreality,thecomplexityismuchlowerduetofaultdroppingand
advancedtechniques.
Definitions
y FaultSpecification
y FaultDropping
y FaultInsertion
Definingasetofmodeledfaultsand
performing fault collapsing
performingfaultcollapsing
The removal of detected, hyperactive and
hypertrophic faults during the run (Inverseof
fault insertion)
faultinsertion)
Selectingasubsetoffaultstobesimulated
andcreatinganetlistwiththesefaults
Propagationoffaulteffects
Afaultcanbetermeddetectediff:
y Itisactivatedbythetestvector
y Itsfaultyvalueistransferredfromtheeffectednet(internal)ontothe
p
primaryoutputpins
y
p p
F lt Dropping
Fault
D
i g
y Numberoffaultsrequiringsimulationdecreasesastherunproceeds
becausethemaingoalistodeterminethefaultcoverageofagiven
because
the main goal is to determine the fault coverage of a given
testpattern
y Detectedfaultscanbeimmediatelyremoved,drasticallyreducingthe
averagelistlengthandthusthecomputingload
average
list length and thus the computing load
y Some faults must be removed in any case for the sake of efficiency. These belong
to two main classes: hyperactive and hypertrophic faults
y Hypertrophic
H
t
hi ffault
lt causes the
h networkk to remain
i iin an unknown
k
status on almost
l
Referred from S.Gai, P.L.Montessoro, Fabio Somenzi, MOZART, a Concurrent Multilevel Simulator, IEEE Transactions on Computer-Aided Design,
vol. 7, no. 9, September 1988, pp. 1005-1016
Fault Injection
Fault-free circuit
Comparator
f1 detected?
Comparator
f2 detected?
Comparator
fn detected?
Example
words
S
Storage:onewordperlinefortwostatesimulation
d
li f
i l i
Multipasssimulation:Eachpasssimulatesw1 newfaults,wherew is
themachinewordlength
S
Speedupoverserialmethod~w1
d
i l
h d
1
NotsuitableforcircuitswithtimingcriticalandnonBooleanlogic
1 1
1
a
b
1 1 1
1 0 1
c s-a-0 detected
ss-a-0
a0
g
0
0
s-a-1
AND
OR
Input
output
{La Lb }UZ1
{ La' Lb }UZ
{L
} U Z1
{La ULb } Z0
{LaULb } Z1
{La' Lb }UZ0
{ La Lb' }UZ
{L
} U Z0
{La Lb }UZ0
a
b
1
1
{b0}
{ 0}
{a
{b0 , c0}
c
d
{b0 , d0}
{b0 , d0 , f1}
Lg = (Le Lf ) U {g0}
= {a0 , c0 , e0 , g0}
Faults detected by
the input vector
y
y
y
faultycircuitthatdifferinsignalstatesfromthefault
faulty
circuit that differ in signal states from the faultfree
freecircuit.
circuit.
Alistpergatecontainingcopiesofthegatefromallfaultycircuitsin
whichthisgatediffers.ListelementcontainsfaultID,gateinputand
outputvaluesandinternalstates,ifany.
Alleventsoffaultfreeandallfaultycircuitsareimplicitlysimulated.
Faultscanbesimulatedinanymodelingstyleordetailsupportedin
truevaluesimulation(offersmostflexibility.)
Fasterthanothermethods,butusesmostmemory.
y Badevent
Eventsthatoccurinthefaultycircuitofcorrespondingfault
Affectonlybadgates
y Diverge
Additionofnewbadgates
g
y Converge
RemovalofbadgateswhoseI/Osignalsarethesameascorresponding
Removal of bad gates whose I/O signals are the same as corresponding
goodgates
0
1
a
b
c0
b0
e0
1
0
1
1
1
c
d
1
0
1 0
0
0
a0
1
1
b0
0 1
d0
0 1
f1
1 1
g0
b0
0
1
1
f1
c0
0
1
1
d0
e0
0