Experiment 5

Sampling & Delta Modulation

5.1 Objective
1- To evaluate and analyze an implementation of a sample and hold (S/H) circuit.
2- To introduce Delta Modulation and test its main characteristics in a simple
circuit implementation.

5.2 Basic Information

Introduction to sampling
A/D circuits require the input signal to remain constant during the conversion
process; however, real world signals may fluctuate rapidly. The Sample and Hold
(S/H) is a device that makes its output follow the input until it is told to hold this
value. It then maintains the output as steady as possible, regardless of fluctuations of
the input, until released to follow the input again. This assures that the A/D is not
trying to hit a moving target.

(a)
(b)
Figure 5.1. (a) A simple S/H circuit. (b) A practical S/H circuit.
In its simplest form, the S/H circuit consists of a switch (S) and a capacitor (C)
as in figure 5.1(a). When the switch S is closed, the capacitor C is charged to the
value of the input voltage, the sample stage. Afterwards the switch is opened and the
capacitor retains its charge, the hold stage. The resulting output is shown in figure
5.2-b. This alternation between sample and hold modes is repeated as long as the
switch keeps toggling. The switching rate is controlled by a clock signal whose
frequency should satisfy the Nyquist sampling criterion.
A practical implementation of the S/H circuit is shown in figure 5.1(b). The
switch is a FET whose gate is controlled by the clock pulse. Buffers are placed at the
input and output to isolate the circuit.
.

Figure 5.2 (a) Original signal. (b) Sample and hold cycles. (c) Capacitor
droop.
The S/H has three sources of error:
1- Finite Aperture Time: The S/H takes a period of time to capture a sample of
the signal. This is called the aperture time. Since the signal will vary during
this time, the sampled signal can be slightly off.
2- Signal Feedthrough: When the S/H is not connected to the i/p signal, the value
being held should remain constant. Unfortunately, some signal does bleed
through the switch to the capacitor, causing the voltage being held to change
slightly.
3- Signal Droop: The voltage being held on the capacitor starts to slowly
decrease over time if the signal is not sampled often enough, see figure 5.2(c).
To reduce the first and second sources of error, the sampling rate is increased. The
third source of error is reduced by selecting a special kind of capacitor. Much depends
on the quality of the charging capacitor. It is responsible for regulating the hold step,
the acquisition time and the droop rate. The absorption of the dielectric used in the
hold capacitor is extremely important. Lossy standard capacitors are slow which
reduces the sampling rate. Polystyrene and polypropylene capacitors are best suited
for S/H circuits.
Aliasing
If the Nyquist rate for sampling is not satisfied. I.e. if a signal was sampled at
a rate less than double its maximum frequency aliasing will occur. This will appear as
a new signal at a different frequency. This new frequency looks like it is folded back
around the original signal. For example if the signal to be sampled has a frequency of
2kHz. It must be sampled at a minimum of 4kHz. If by mistake this signal is sampled
at 3kHz, a new signal will appear instead of the original signal. The frequency of the
new signal will be at 1kHz. It appears that since we know what has happened we can
recover the original signal. In reality this is not possible since we do not know the
frequency of the original signal and we do not know if aliasing has occurred in the
first place. Things are complicated further if the original signal is composed of many
frequencies, some below the Nyquist rate and some above. Therefore we must make
sure aliasing does not occur in the first place. This is accomplished by two things;

sampling at a rate higher than the Nyquist (over-sampling), and by limiting the upper
frequency of the original signal through a low pass filter (anti-aliasing filter).
The LF398 S/H Integrated Circuit
The LF398 is a basic and common S/H monolithic IC, figure 5.3. It consists of
an input and output buffer amplifiers, and a digital switch. The hold capacitor is
connected externally. During the sample mode, the capacitor is connected to the
output of the input amplifier A, and during the hold mode, to the input of the output
amplifier B. Amplifier B is a unity gain follower, of FET type for high input and low
output resistances. Amplifier A is bipolar with low output offset voltage and wide
bandwidth. The external capacitor is charged from a current source through the logic
controlled switch. Amplifier C is a digital switch, which is turned on when the logic
input drops below the reference voltage. The output of amplifier B is fed back to
amplifier A.
During the sample mode, the charge on the capacitor follows the analog input
signal. In the hold mode, the input amplifier is disconnected and the capacitor holds
the charge. The capacitor is discharged by the follower amplifier.

Figure 5.3 LF398 block diagram and S/H experiment circuit connections.
The Sample & Hold Experiment Circuit
The experiment circuit in figure 5.3 is built around the LF398 IC. The analog
input is selected to be DC (+5 to -5V) through a pot, or AC through Vin. Selection of
input is through switches c7 and c8.
The sample and hold modes are chosen as continuous sample mode by switch
c6 and a reset switch, or clocked S/H through switches c4 or c5. The hold capacitor
with different values is selected through switches c1 and c2. A resistor is connected in

parallel to the hold capacitor through switch c3 to clarify the effect of capacitor
droop.
Introduction to Delta Modulation
Various techniques exist for converting analog message signals into a digital
stream of bits. PCM is one of these techniques. In PCM, the amplitude of each sample
in the message signal is converted into an 8-bit word. This offers high resolution of
the signal amplitude. However, audio signals do not have a large amplitude variation
from one sample to the next, i.e. there is a strong similarity between consecutive
samples. This implies that we can decrease the number of bits per sample if we utilize
the information we have about the previous sample. In the simplest method, the
information sent indicates whether the sample is merely larger or smaller than the
previous one. This is called delta modulation.

Figure 5.4 The message signal m(t), the staircase approximation of the message signal
mq(t) , and the binary sequence output eq(t).
To generate delta modulation the amplitude of each sample of the message
signal m(t) is compared with the amplitude of the previous sample, a 1 is sent to
indicate that the new sample is larger than its predecessor, while a zero is sent
otherwise. The resulting stream of bits is transmitted to the receiver. The output mq(t)
is a staircase approximation of the original message. See figure 5.4. The step size is
fixed to a certain value while the sample period is denoted by TS. To increase the
correlation between consecutive samples, the sampling rate is increased to a value
much higher than the Nyquist rate. This results in a close approximation to the
original message.
The staircase approximation of the message signal mq(t) is given by the relation
mq ( n T S ) = mq ( n T S T S ) + eq ( n T S ) 5-1

where

eq ( n T S ) = sign[m( n T S ) mq ( n T S T S )] 5-2

The main advantage of modulation over other methods is its simplicity. The simple
logic behind it, and the small amount of hardware required to implement it, make it
the most attractive for new systems.
There are two sources of error in modulation. The first is Slope Overload
Distortion, this distortion occurs when the input signal rises or drops (increases or
decreases in amplitude) at a rate higher than the slope of the staircase approximation
of the signal. Figure 5.5 shows this distortion. To avoid this case, the slope of the

input signal must be less than the staircase approximation; this is satisfied under the
condition:

max

TS

dm( t )
dt

5-3

In the case of a sinusoidal signal this condition simplifies to

2A f m 5-4
TS
where A is the amplitude of the sinusoid and fm is its frequency.

Figure 5.5 Slope overload distortion and granular noise in delta modulation.
The second source of error is Granular Noise, which occurs when the change
in the amplitude of the input signal is smaller than the step size . This causes the
staircase approximation to hunt up and down around the signal. See figure 5.5. The
solution to this case seems to be in reducing the step size. However this contradicts
the condition for avoiding slope overload.
Advanced modulation techniques use a variable step size that adapts to the
signal at hand. When the signal increases rapidly (large slope), the step size is
increased until the error is reduced. Inversely, when the change in signal amplitude is
small, the step size is reduced to decrease granular noise. Such systems use
sophisticated circuits and are mainly utilized in areas where signal reproduction
quality vastly outweighs cost.
Delta Modulation Block Diagram
The transmitter consists of a hard limiter (comparator), whose output is high
or low depending on the difference between the input signal and its approximation.
See figure 5.6. The output of the limiter is multiplied with the sampling clock. This
product is transmitted through the channel to the receiver. The product is also fedback
through an integrator (LPF) to the summing junction of the limiter.

Figure 5.6 Block diagram of a Delta modulation system.

In this system, the parameters of step size, sample rate and integrator (LPF) cutoff
frequency are related by the formula:

= V clock (1 e T S f cutoff ) 5-5

Experimental circuit
The circuit is quite simple, shown in figure 5.7. It is composed of a
comparator (LM339), which acts as a summer and hard limiter. The D-type flip-flop
(74LS74) performs multiplication with the clock. The integrator in the feedback path
is a simple RC low pass filter circuit. The output of the modulator is a stream of high
and low digital bits (Tx o/p). The receiver is a LPF, the same as the LPF in the
feedback loop. So the output of the receiver is identical to the output of the feedback
loop (Rx o/p).

Figure 5.7. Delta Modulator circuit diagram.

5.3 Prelab
Use parts C and D of the procedure to do a complete simulation of circuit 5.7.

5.4 Equipment
Digital Communications Panel (SIP397-1)
Power Supply Base (S300PSB)
Function Generator
Oscilloscope
Frequency Counter
Digital Multimeter

5.5 Procedure
Part A- Clocked sampling for a continuous signal
1- Set the supply voltages on the power supply base to +10V.
2- Close switches b4 & c5 to feed a sampling clock to the LF398 IC. Adjust
R1 potentiometer (in section A- Universal Clock section of the test board)
to get a sampling frequency 4.8kHz at TP6 (in section BSAMPLE/HOLD). Record this clock.
Clock Amplitude (V)
Frequency (kHz)
3- Connect 30nF hold capacitor to pin 6 of the IC by closing switch c1.
4- Set the function generator to 3VPkPk sine wave at 200Hz. And connect it to
the input of the IC at TP5. Also connect ch1 of the oscilloscope to TP5,
and use it as the trigger for the oscilloscope.
5- Record the sampling output at TP7 through ch2 of the oscilloscope. Adjust
the Hold-Off on the oscilloscope for best display.

6- Count the number of samples/cycle.

Measured

Theoretical

No. of samples/cycle
7- Increase the input frequency to 800Hz. Repeat step 6.
Measured
No. of samples/cycle

Theoretical

8- Increase the input frequency to 5kHz. Describe the display and explain
what has happened.

....
9- Set the oscilloscope to 0.5ms/div and find the alias frequency.
Measured

Theoretical

Alias Frequency
Part B- Capacitor droop observation
1- Change the input signal to a triangular wave at 400Hz. Record the sampled
output.

2- To simulate a lossy capacitor, add 220k resistor in parallel with the 0.003F
capacitor, open sw. c1 and close sw c2 and c3.
3- Record the o/p at TP7. Record the output.

4- Compare and describe what happens to the shape of segments between steps 1
& 4.

5- Open all c switches (c1 to c8).

Part C- Delta Modulator

1. Build the circuit in figure 5.7.
2. Use the Universal Clock from the test board to obtain a 100kHz clock for your
circuit. Open sw. b4 and close sw. a3. Adjust R1 to get 100kHz at TP3. Use
jumper wires to connect TP3 to the clock input in your circuit. And connect
the circuit ground to the ground on the board
3. Set the function generator to 1.8VPP sine wave at 1kHz with 2V dc offset, and
connect it to the input marked Vin.
4. Compare and draw the input at Vin with the staircase approximation at Rx
(Receive) o/p.

5. Record the error between both signals by subtracting the Rx o/p signal from
Vin on the oscilloscope. Draw the error and note the areas of slope overload,
granular noise, and the error amplitude.

6. Increase the clock rate to 300kHz. Open sw. a3 and close sw. a2. Adjust R1 to
get 300kHz at TP3. Note the effect on the output and the error.

7. Return the clock to 100kHz. Open a2 and close a3. Adjust R1 to get 100kHz at
TP3. Increase the signal frequency to 1.3kHz. Note the effect on the output
and the error.
..
..
..

8. In your report, relate your results in steps 4, 6 and 7 to the equation 5-4.
9. Calculate the cutoff frequency of the LPF and relate it to the previous results.
10. Calculate the step size.
Filter Cutoff (kHz)

Step Size (V)

11. Restore the signal to 1kHz. Observe the digital Tx (Transmit) output. Draw
the digital signal in relation to the analog input.