MATH CO-PROCESSOR

The Intel 8087 is a high performance math co processor that

extends the architecture of the 8086 with floating point,
extendedinteger and BCD data type:

• .The 8087 adds over sixty eight mnemonics to the

instruction set of the 8086, including support for
arithmetic,logarithmic,exponential,and trigonometric
mathematical operations.

• .The 8087 is implemented with 1.5 micron, high speed

CHMOS III technology andpackaged in both a 40 pin
CERDIP and a 44 pin PLCC package.

• The instruction set of the math chip is different from of the

primary CPU.

Features of 8087 :

• . High performance 80 bit internal architecture

• . Implements ANSI/IEEE standard 754 1985 for binary floating point

arithmetic

• . Directly interfaces with 8086 CPU

• . seven built in exception handling

• . Eight 80 bit numeric registers, usable as individually

addressable general registers or as a register stack.

• . Multi bus system compatible interface

Pin Diagram and Description :

 1 40 VCC
GND
2 39 AD15
AD14
3 38 A16/S3
AD13
4 37 A17/S5
AD12
5 36 A18/S5
AD11
6 35 A19/S6
AD10
7 34 BHE/GT
AD9 1
8 33 RQ/GT1
AD8
9 32 INT
AD7
10 31 RQ/GTT
AD6 0
NC
AD5 11 8087 30
NC
AD4 12 MATH 29
S2
AD3 13 COPROCESSOR 28
S1
AD2 14 27
S0
AD1 15 26
QS0
AD0 16 25
QS1
NC 17 24
Busy
NC 18 23
Ready
CLK 19 22
Reset
GND 20 21

AD0-AD15 [multiplexed Address/ Data Lines]:

• These are time multiplexed address/ data lines. These lines carry
address during T1 state and data during T2, T3, Tw and T4 states.
• A0 address signal is used to generate chip select signal while
transferring data on lower order data bus D0- D7.
• These lines act as input lines CPU driven bus cycles and become
input/output lines for NDP initiated cycles.
A16/S3-A19/S6 [Multiplexed Address /Status Lines]:
• These lines are also time multiplexed address /status lines .These lines
carry address during T1 state and status during T2, T3, Tw and T4
states.
• For 8087 controlled bus cycle, S0, S4, S3 are reserved and
permanently high ,while S6 is permanently low.
• These lines are input, which 8087 monitors when the CPU is in control
of bus.
BHE/S7;
 • During T1 the BHE/S7 pin is used to enable data on the higher bytes
of the 8086 data bus i.e. D0-D7.
• During T2, T3, Tw and T4, thid line carry status which does not carry
any significance in 8088 bases system.

QS1, QS2:
• These are queue status input signal enable 8087 to keep to keep track
of the instruction pre-fetch queue of the CPU ,to maintain synchronism
with it .
• The status of these lines can be decoded as given in table.

QS1 QS0 Queue Status

0 0 No Operation
0 1 First byte of op-code from queue
1 0 Empty Queue
1 1 Subsequent byte from queue

INT:

• This line is used to indicate that an unmasked exception has occurs

during numeric instruction execution when 8087 interrupt is enable.
• This signal is routed to programmable interrupt controller 8259.
BUSY:

•
This is an output signal to indicate 8087 is executing an instruction.
•
This pin is normally connected to TEST pin of 8086 CPU.
READY:
• This input signal may be used to in form the coprocessor that the
addressed device will complete the data transfer from its side and
the bus is likely to be free for the next bus cycle
• Normally this signal is synchronized by the clock generator.
RESET:
• This is an input signal used to reset coprocessor which will
terminate all coprocessor operation.
• This signal must be active high for at least 4 clock pluses.
CLK:
• The clock input provides basic timing for the coprocessor
operation.
S0, S1, S2:
These status lines can be either 8087 driven or externally driven by the CPU.
If these lines are driven by 8087, they can be decoded as given in table.
These lines become active during T4 of previous bud cycle and become active
till T1 or T2 of current bus cycles.
They are suspended during t3 for the next bus cycle.
These signals are used by the bus controllers to derive the read and write
signals.
This signal act as input signals if CPU is executing a task.
S2 S1 S0 Status
0 X X Unused
1 0 0 Unused
1 0 1 Memory read
1 1 0 Memory write
1 1 1 Passive
RQ/GT0:
• The request/grant pin is used by the 8087 to gain control of the bus
from the bus master 8086/8088 for operand transfer.
• It must be connected to one of the request/grant pin of the
8086/8088.
• The 8087 waits for the grant pulse from the 8086.
• An active low pulse of one clock duration is generated by 8087 for
the 8086 to inform that 8087 needs control of local buses either for
him or for the other coprocessor connected to RQ/GT1 pin of
8087.
• When it received, it either initiates a bus cycle if the request for
itself or it passes the grant pulse to RQ/GT1,if the request is for the
other coprocessor.
RQ/GT1:
• The bidirectional pin is used by the other bus master to request for the
use of local buses access to 8087.
• This request further transfer to the 8086 CPU.
• At the time of request, if the 8087 does not have the control of the bus,
the request is passes to the 8086 using RQ/GT pin.
• If the 8087 has the control over the bus,whenit receives a valid request
on RQ/GT1 pin,the 8087 sends a grant pulse during the following T4
or T1 clock cycle, to requesting master indicating that it has floated the
bus.
• The requesting master gains the control of the bus till it needs.
• At the end, the requesting master issues an active low for one clock
cycle for 8087, to indicate that the task is over and 8087 may gain the
control of bus.
• The request/Grant pin may be used by the other bus master such as
DMA controller.