Robust asynchronous-reset architecture for

scan coverage
Sandeep JainNikila Krishna, - April 15, 2015

Digital integrated circuits typically use asynchronous set/resets to set the value of memory elements
(flip-flops) without depending on any clock pulses. This logic, however, requires special handling
during scan based testing of the device. Also, the logic associated with asynchronous set/reset may
constitute 2-4% of the total faults in a design. With growing focus on high test-coverage and zero
DPPM, especially for critical applications like automotive and medical devices, it is important to
thoroughly test such faults to ensure overall system robustness.
This article presents various scenarios, and the test architecture to robustly detect scan coverage
including potential race conditions on asynchronous paths.
The salient features of this architecture are:

Targets coverage on internally generated set and reset logic

Avoids glitches due to reconvergence on scan-enable and async-SE signals
Reuses scan-in pin during capture to delay the async-SE trigger

1. Coverage Loss with Test-mode Gating

A design can have reset logic generated from combinational decoding of other sequential cells, in
addition to a top-level reset control. During scan-mode, if this logic gets random scan-data, the sink
flop can get reset thus corrupting the scan shift data. To avoid this situation, the combinational logic
is gated-off with a static signal (testmode/scanmode) to feed a constant data during shift as well as
capture.

Figure 11 Static Gating of Internally Generated Reset

However, using a static signal blocks the observe cone of the combinational logic, leading to
coverage loss, as seen in Figure 11.

Figure 12 Bypassing Internally Generated Reset with External Pin

To recover this loss of coverage, we typically bypass the internal reset with external pin-reset. The
bypassing signal is toggled in one of the scan-modes to allow functional path to propagate to scanflops as shown in Figure 12.

2. Coverage Recovery with Scan-Enable Logic

Figure 21 Async_SE Generated with a Static Bit and an External Pin SE

The coverage loss on functional reset can be recovered, if the gating logic is enabled only during
shift. During capture, the functional values take control of the flop-reset pin.
The scan-enable signal (denoting the shift or capture phase) is gated with a static Test Data
Register(TDR) bit, so that this functionality is enabled only in a specific ATPG mode (when reset
coverage is targeted). The TDR bits needs to be kept out of scan with clock/reset gated, so that the
bit retains its value during entire scan operation.

Mode
Mode-1
Mode-2

Details
ATPG without targetting reset faults
ATPG targetting reset faults

Mode-3

ATPG targetting functional reset cone

coverage

Table 21 Modes of Operation with Async-SE

Configuration
TDR_bit=1, RESET=1
TDR_bit=1,
RESET=0(capture)
TDR_bit=0, RESET=X

Figure 22 Waveforms for Async_SE Operation

The waveforms in 2-2 shows a window after the clock pulses and before asserting SE, where all
glitches in the combinations logic has settled before the logic is made transparent for flop reset pin.

3. Glitches Due to Reconvergence on Scan-enable Cone

Figure 31 Async-SE updated for SE Reconvergence

The async-SE logic discussed earlier can still create glitches during capture, if there is any
reconvergence on SE pin, as shown in Figure 2-4(a). SE is typically used to control various pinmuxing and other muxing logic which can get triggered simultaneously, the moment SE is asserted.
To avoid this issue, another qualifying signal is added which allows any transition excited by SEassertion to settle down, before making the functional-reset cone transparent. In order to avoid
another top-level pin for this functionality, we have reused 1 of the scan-in pins which are unused
during the capture phase.

Figure 32 Waveforms for Async_SE after adding Another Qualifier Pin

The waveforms in Figure 32 shows a 2-stage approach that allows any glitch arising from clockpulsing or SE-assertion to settle down before the logic is made transparent for flop reset pin.

4. Glitches Due to Reconvergence on Async-SE Cone

Figure 41 Reset-Ripples Created due to Same Async-SE controlling Cascaded Resets

In case the output of a flop driven by async_SE feeds the functional reset cone of another flop, there
can be ripple effect when async-SE is asserted. The 1st flop would get a reset, once async-SE is
asserted. This would make the functional-reset logic of 2nd flop to be re-evaluated and update the
output of 2nd flop (this behavior was not expected though, during pattern generation).
As the ATPG tools work on a static view of the design, these issues are not detectable during pattern
generation. This can lead to simulation failures when actual timing data is applied. Sometimes the
ripple effect is seen to manifest only at silicon, while the glitch was not seen during timing
simulations.

Figure 42 Async-SE Split within TCU Based on 1-cold Decoded Testpoints

In order to avoid the ripple-reset scenario, the async-SE logic is split so that a unique async-SE
signal is generated for cascaded reset cases. The async-SE is gated by testpoints which are 1-cold
decoded, so that only 1 of the flops are at 0, while others are at logic 1.

5. Glitches Due to Reconvergence on Reset Mux

There can be cases where we get a glitch on the reset pin even after taking care of the
reconvergence in the SE and Async_SE pins. These glitches can arise due to reconvergence in the
reset-mux itself, if the logic gets broken in combinational gates during synthesis

Figure 51 Reset Mux broken into Combinational Gates Resulting in Glitches

In order to avoid these glitches, we need to ensure that the reset mux gets preserved as a mux and
is never broken into AND-OR gates.
It is recommended that the reset muxing is always done using a mux-instantiation code in the RTL
rather than a combinational statement. The synthesis team can add-in rules to ensure that these
muxes are further preserved as mux during the entire Synthesis/BE cycle.

assign muxed_rst = (async_se) ? test_rst : func_rst;

dft_reset_mux mux_inst (.a(func_rst), .b(test_rst), .sel(async_se), .x(muxed_rst) );

As the mux is a single library cell, there will not be any glitch inside the mux logic. There should be
no special requirement to use any balanced or glitchless muxes for reset muxing.