EE 134

FINAL PROJECT
Winter Quarter 2004

The Knight Rider Team

Arshdeep Singh
Oscar Servin
Edward Lee
Lutfi Bustami

Introduction:
For our final project we are designing laying out a 4017 CMOS
Counter LED chaser. We used Transmission gates, 2-input NOR gates,
3-input NOR gates, Inverters, and 2-input NAND gates to create our
4017 CMOS Counter.

Components of the Circuit:

For the layout of the circuit we are going to be using
Transmission gates, 2-input NOR gates, 3-input NOR gates, Inverters,
and 2-input NAND gates. In addition to these components, we will be
using a bond pad and pad frame.
In the circuit we will be using CMOS Transmission gates. This
particular transmission gate has two transistors, one n channel
transistor and one p channel pass transistor. These two transistors are
connected in parallel. The reason why we use these two particular
transistors is because they pass logic lows and logic highs.

Below is a picture of our transmission gate layout. This layout was

done in Cadence. I have also provided below a picture of our symbol
for the transmission gate.
Layout of Transmission Gate:

Symbol for Transmission Gate:

Below I have provided a truth table for the basic operation of a

transmission gate. C is the input while the 0 represents a logic low and
1 represents a logic high.

Result

A and B are disconnected

A and B are connected

Next, I will talk a little about the inverter. We use inverters very

often in this layout as does anybody who is building a digital circuit

design. The inverter is known as the basic building block of digital
circuitry design. The inverter just takes an input A and turns it into A
bar. Basically, it takes a logic low (0) and turns it into a logic high (1)
and vice versa. The way it works for our circuit is, that when the input
of the inverter is connected ground, the output gets pulled up to Vdd
through the PMOS (p-channel) transistor. Similarly, when the input of
the inverter is connected to Vdd, the output gets pulled down to
ground through the NMOS (n-channel) transistor. Below I have
provided a picture of the inverter layout we did in Cadence and also
the inverter symbol that we used.

Layout of the Inverter:

Symbol of the Inverter:

Next, I am going to go into talking about our D-flip flop. The way
that we designed our particular D-flip flop is by using transmission
gates and inverters. The D-flip flop has one input line D which is
referred to as data. When we D=1 the flip flop is set and when D=0
the flip flop is reset. Our particular D-flip flop is a rising edge-triggered
D-flip flop. The rising edge-triggered D-flip flop is a D-flip flop whose
state only changes during positive clock transitions. Again, we provide
pictures of the layout, transistor level schematic, and truth table
below.

Layout of the D-flip flop:

Transistor Level Schematic of the D-flip flop:

Truth Table for the D-flip flop:

Q Q(next) D
0

If you look at the transistor level schematic of the D-flip flop

above, you will notice that the transmission gates are labeled T1-T4.
Labeling these transmission gates will help you better understand my
explanation of how exactly the D-flip flop functions. When the CLK
goes to low, the logic value at D sets nodes A and D bar to node B
which means that transmission gates T2 and T3 are turned off. The
value at node C is available at the flip flop output as a result of the
previous leading edge transition of the CLK input pulse. When the
value at the CLK goes high, transmission gates T1 and T4 and turned
off and T2 and T3 are turned on. The value at node C is transferred
with the correct inversion to the output of the D-flip flop.

The two basic components in this circuit are the NAND and NOR gates.
The NAND gate is a NOT and AND gate in one which means that in
order to get the truth table for the NAND gate we take the truth table
for the AND gate and invert it. Below I have provided the symbol and
the truth table for the NAND gate.

A B Y
0 0 1
0 1 1
1 0 1
1 1 0

The NOR gate consists of a NOT and OR gate together in one which
means that logic of the NOR gate is the same as the OR gate except
its inverted. Below I have provided the symbol and truth table of the
NOR gate.

A B Y
0 0 1
0 1 0
1 0 0
1 1 0

In addition to the NOR gate described above, we also added a threeinput NOR gate. Below I have provided the symbol and truth table for
the three-input NOR gate.

A
0
0
0
0
1
1
1
1

B
0
0
1
1
0
0
1
1

C
0
1
0
1
0
1
0
1

Y
1
0
0
0
0
0
0
0

Overall Gate-level Schematic:

Before we actually laid the whole circuit out we created a gate-level
schematic in Cadence. Then we actually went and did a simulation on
Cadence also to make sure that it actually worked properly and did
what we wanted it to do. Below I have provided the gate-level
schematic and simulation results of our counter.

Gate-Level Schematic:

Simulation Results:

Truth Table for the CMOS Counter:

Clock
0
X
X
Rising Edge
Falling Edge
X
1

(Clock
Enable)
X
1
X
0
X
Rising Edge
Falling Edge

Decode
Output = N
N
N
Q0
N+1
N
N
N+1

Overall Layout:
Below I have provided you with a picture of the overall layout.
All of the components are laid out and linked together in one overall
layout.

Bond Pad Layout:

Below I have provided a picture of the layout all connected to the
bondpads. This was the final step in our project. We simply had to set
our outputs, power, and ground pins, in order for next years group to
be able to test our chip.

Pin Assignment Diagram:

Below I have provided a diagram of the pin assignments on our chip.
In order to be able to test our chip, you will have to know what these
assignments are. Also, our project is to design a CMOS counter that
works as an LED chaser. You are going to need 10 LEDs and one
1kohm watt resistor. Below I have also provided you a picture of
exactly how to hook up the LEDs and the resistor. (Pin 1 is the power
pin)

This is the end of our Report.