Chapter 10

BINARY
ARITHMETIC,
DECODING AND
MUX LOGIC UNITS
 Lesson 7

Demultiplexer

Ch10L7-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 2

 Outline

• Demultiplexer
• 1 of 2 and 1 of 4 line demultiplexer
• 1 of 8
• Decoder from demultiplexer

Ch10L7-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 3

 Demultiplexer
• A demultiplexer is a circuit that gives
the binary information from one end to
another as an output at a unique
channel (one-line or multiple line)
according to a unique combination of
the channel selector inputs at an input
at one-line (or at multiple lines).

Ch10L7-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 4

 Demultiplexer
• Assume that we have 2n circuits to
implement different functions. One is
for addition; other is for subtraction;
other for incrementing; and so on. We
have to activate only one by giving
appropriate input 1 or 0.

Ch10L7-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 5

 Demultiplexer
• A 1 of 2n demultiplexer will let us
select only one using n-bit address or
channel-select input. For example, we
want to de-multiplex and get at
selected output 9th pin when the select-
input is 1001 and activate the circuit,
one of 16 circuits connected at output
of demultiplexer.

Ch10L7-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 6

 Demultiplexer
• Assume that we have 10 digit display,
We have to select only one unique
digit by giving a unique digit select
input bits.
• A 7th digit will be selected by inputs
0111.

Ch10L7-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 7

 1 to n Demultiplexer

• A circuit, which takes the n-bit channel or

address select input, activates only one of
the output out of 2n outputs and remaining
remains inactive. That output equals the
input. [Input is multiplexed and has data fro
different channels at different instances.
Inactive output can be taken as tristate or 1
or 0
• Active output be taken as 1 or 0
Ch10L7-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 8
 Outline

• Demultiplexer
• 1 of 2 and 1 of 4 line
demultiplexers
• 1 of 8 line demultiplexer
• Decoder from demultiplexer

Ch10L7-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 9

 1 of 2 Demultiplexer with inactive
tristate output
Input Address-select input Outputs
I A Y0 Y1
F0 0 F0 *
F0 1 * F0

F0 I Y0
A Y1
* means tristate or 1 or 0. F0 is a
Boolean Function or logic circuit output
Ch10L7-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 10
1 of 2 Demultiplexer with inactive 0
output
Input Address-select input Outputs
I A Y0 Y1
F0 = 1 0 1 0
F0 = 1 1 0 1

1 I Y0
A Y1

Ch10L7-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 11

1 of 2 Demultiplexer with inactive 1
output
Input Address-select input Outputs
I A Y0 Y1
F0 = 0 0 0 1
F0 = 0 1 1 0

0 I Y0
A Y1

Ch10L7-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 12

1 of 4 Demultiplexer with inactive
tristate output
Input Address-select input Outputs
I A1A0 Y3 Y2Y1Y0
F0 00 * * * F0
F0 01 * * F0 *
F0 10 * F0 * *
F0 11 F0 * * *

Ch10L7-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 13

1 of 4 Demultiplexer with inactive
tristate output

Y0
F0 I Y1
Y2
Y3
A1
A0
* means tristate or 1 or 0
Ch10L7-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 14
 Outline

• Demultiplexer
• 1 of 2 and 1 of 4 line
demultiplexers
• 1 of 8 line demultiplexer
• Decoder from demultiplexer

Ch10L7-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 15

1 of 8 Demultiplexer with inactive
tristate output
Y0
Y1
Y2
F0 I Y3
Y4
A2 Y5
Y6
A1 Y7
A0
* means tristate or 1 or 0
Ch10L7-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 16
1 of 8 Demultiplexer with inactive
output 1
Y0
Y1
Y2
0 I Y3
Y4
A2 Y5
Y6
A1 Y7
A0

Ch10L7-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 17

 Outline

• Demultiplexer
• 1 of 2 and 1 of 4 line
demultiplexers
• 1 of 8 line demultiplexer
• Decoder from demultiplexer

Ch10L7-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 18

 Decoder from a 1 of 8 Demultiplexer
with one control (enabling/disabling)
pin. Active 0 output

Y0
Address A0 Y1
Select Y2
Input bits
A1
A2 Y3
Y4
0 I
Y5
G Y6
Y7
Ch10L7-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 19
 Summary

Ch10L7-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 20

 Demultiplexer

• Demultiplexer active one output pin

among 2n output pins and has n address
or channel select inputs to enable
circuit to select corresponding output.

Ch10L7-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 21

 Demultiplexer

• A demultiplexer can have inactive

outputs in tristate and active output as
0 or 1
• A demultiplexer can have control gate
pins
• A demultiplexer function as decoder
with active 1 or 0 as per input pin
Ch10L7-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 22
 End of Lesson 7 on

Demultiplexer

Ch10L7-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 23

 THANK YOU

Ch10L7-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 24