The document discusses analyzing signal shapes from a digital-to-analog converter (DAC) simulation to identify the converter's parameters. It provides an example where analyzing the signal periods and slopes allows determining the time base, input and reference signal frequencies, DAC bit number, operational amplifier slew rate, and DAC setting time. The lab exercise has students analyze three simulated DAC circuits to identify the parameters and explain any differences from ideal signal shapes.
The document discusses analyzing signal shapes from a digital-to-analog converter (DAC) simulation to identify the converter's parameters. It provides an example where analyzing the signal periods and slopes allows determining the time base, input and reference signal frequencies, DAC bit number, operational amplifier slew rate, and DAC setting time. The lab exercise has students analyze three simulated DAC circuits to identify the parameters and explain any differences from ideal signal shapes.
The document discusses analyzing signal shapes from a digital-to-analog converter (DAC) simulation to identify the converter's parameters. It provides an example where analyzing the signal periods and slopes allows determining the time base, input and reference signal frequencies, DAC bit number, operational amplifier slew rate, and DAC setting time. The lab exercise has students analyze three simulated DAC circuits to identify the parameters and explain any differences from ideal signal shapes.
PARAMETERS, USING THE SIGNAL SHAPES The signal shape shown on a scope screen encodes a lot of information. Visual quantitative and qualitative analysis allows understanding the under-study circuit behavior, emphasizing, estimating or even measuring of certain behavioral parameters. Comparing those values to normal ones helps in circuit limits estimation or finding design- and manufacturing-mistakes. THE LAB PURPOSE First, the lab intends to learn the students to completely read a scope-diagram, analyzing both the individual signal carried information (amplitude, offset, frequency, shape) and the correlation between more synchronized signals. On the other hand, the students go thoroughly into understanding the behavior basics for a D/A converter family, previously discussed at class. The lab uses the same simulation program as the previous one, Simulation of digital-analog converters. Knowing its behavior and the set of settable parameters, the students use this time the program as a needed tool to solve a required task: identifying the type and the parameters of a digital-toanalog conversion schematic. The simulated scope is a memory one. The signal images are static, corresponding to a single scan cycle, synchronized on the zero-phase of both input signal and code generator. A non-memory scope can be used for iterative time scanning of periodical signals. All the signals shown by different channels should have a whole number of periods in the scope scan period, otherwise the image is unstable. Additional problems are choosing appropriate time base and trigger level. For D/A conversion analysis, using such a scope would be difficult.
Data Conversion and Acquisition Systems - Lab Manual
SIGNAL SHAPE ANALYZING EXAMPLE
Fig. 1 DAC simulated signal shapes example
In Fig. 1, the first step is observing the scope time base (three tact/division). Reading on the diagram that a division represents 0.3s, the clock period results 0.1s at a clock frequency of 10MHz. The first two divisions fit one and a half input signal periods, resulting an input signal period of 0.4s, at a frequency of 2.5MHz. The input signal is rectangular, the two levels being at -2V, respectively +10V. Their mean value is the offset voltage = 4V, and half of their difference is the amplitude = 6V. The code generator is a counter type one (observing on the diagram the succession of the most significant four bits). A whole cycle takes 16 tact, resulting that both the counter and DAC have 4 bits. To confirm that, the hexadecimal representation of input number {A} uses a single digit (max. 4 bits), and the maximum value is E (min. 4 bits). Correspondingly, the output voltage should be trapezoidal, in phase (or anti-phase) to the reference voltage, increasing the amplitude while the input number increases. Against that ideal shape, the observed differences provide additional information regarding the circuit behavior: 2
Identifying the digital-analog converter parameters, using the signal shapes
The output voltage is never negative, despite the fact that the reference voltage has both polarities. One of the polarities is cut out, showing that the converter IC is a bipolar technology one. Further, the only polarity of the output signal is positive, due to a voltage output stage (for a current output stage, the V- signal would be missing). The output voltage is not strictly trapezoidal, even when positive, the deviations being greater as the amplitude is greater (the output voltage goes closer to a triangular shape). The slopes between the ideal (trapezoidal) levels are so slow that, they end (in the fifth division), by reaching the final value when they already have to begin a new (reverse) transition. That means that the operational amplifier Slew Rate limits the variation speed of the output voltage. Estimating the output voltage angle in the fifth division (around 8V swing in around 0,2s.), the slew rate results: SRAO = 40V/s. During the time when Vout is not at its ideal value (SRAO limitation), V- is not zero. The voltage drop across the OA does not equal Vout. If the converter IC would exhibit an ideal (zero) setting time, the voltage drop across the feedback resistor (proportional to Io) would attend the ideal (trapezoidal) shape. For example, on the negative Vref level, at 5th to 6th divisions boundary, Vout and Io should be both zero (negative reference voltage). Vout isnt zero, due to SRAO . Io zero value would result in zero voltage drop across R, i.e. Vout = V-. The graphic shows that the two previous mentioned voltages are not equal immediately after the previous negative slope of Vref, meaning Io is not zero at that time also. That shows the DAC IC doesnt change its output current instantaneously. Its setting time can be estimated as the time needed for the two voltages (Vout and V-) to became equal, respectively for Io to became zero, (approximately 0,1s).
Data Conversion and Acquisition Systems - Lab Manual
THE LAB FLOW Each student receives three printed images, obtained using the DAC simulation program discussed in previous lab. Analyzing the graphical representation, the students identify the signals and estimate the behavioral parameters for the simulated circuits. By reconstituting the initial (unknown) parameter set, each figure is reproduced on the computer screen. For the figure, the student has to determine: the time base; the code generator (type and clock period); the reference signal (shape, amplitude, offset and frequency); the schematic type; the used DAC IC (bit number, reference limitations, dynamic parameters); the output stage (gain, dynamic parameters, supply voltage). The student has also to explain the signal shapes and to identify the approximating mathematical functions. The differences to ideal shapes will be pointed, the disturbing phenomena analyzed and solutions to improve the behavior proposed. A special attention (only for voltage output circuit) will be paid to V- signal (the voltage in the inverting input of the operational amplifier), explaining why it doesnt always equal zero. The quantitative relation between V- and other signals has to be determined. Each figure is analyzed slice by slice, emphasizing the time periods where each phenomenon manifests.