DR AJAY KUMAR SINGH

Position

: Principal Lecturer

Address

: Faculty Of Engineering And Technology (FET)

Multimedia University, Jalan Ayer Keroh Lama
Bukit Beruang 75450
Melaka

Office

: 06-2523425

Fax

: 06-2316552

Email

: ajay1@mmu.edu.my

General
Biography

Dr Ajay Kumar Singh is working as a Principal Lecturer in the Faculty of Engineering and Technology, Multimedia UniversityMelaka Malaysia. He has supervised 4 PhDs and two Master thesis. His areas of interest are modeling of submicron MOS
devices, Low power VLSI circuit design, Memory design and Mixed signal design. He has published more than 50 research
papers in various International Journals and conferences and reviewed many research papers submitted to various
international journals. He is invited in the technical programme committee of various international conferences. He has
authored two books and coauthored one book. He is senior member of IEEE and Fellow of IET-India. He has acted as an
external examiner for master thesis as well as for PhD thesis. He is actively involved as a project leader on his project
Design and implementation of power efficient 32kb 0.2V SRAM memory funded by MOSTI and as a project member in
another project approved by FRGS.

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Education Background

2003
Birla Institute of Technology & Science, Pilani. M.E. (Microelectronics). 1st Class.
1994
Applied Physics, Institute of Technology (BHU) Varanasi- 221 005 UP, India (Now IIT-BHU) Ph.D. Thesis Title: A
study of the propagation characteristics of some Tapered and Chiral Optical waveguides.
1990
Physics Department, Banaras Hindu University. Varanasi 221 005 UP India. MSc(Physics) Specialization in
Electronics. 1st Class.
1988
Banaras Hindu University, Varanasi-221 005 UP India. BSc. (Hons.in Physics) 1st Class.
Award and Recognition

1. Paper, A comprehensive analytical study of an undoped symmetrical double-gate MOSFET after

considering quantum confinement parameter, selected for the presentation in EPS Global
International Forum of Analytical Science, 17-18 January-2012, Bangkok Thailand.
2. Biography is included in Marquis Who's Who in Science and Engineering 2011-2012 (11th Edition).
3. Biography is included in Marquis Who's Who in Asia 2012 (2nd Edition)
Working Experience

1. Sept. 1990-Dec.1991
Research Scholar, Applied Physics, Indian Institute of Technology (BHU)
Varanasi-221 005 UP India
2. Jan. 1992- Dec.1993
Junior Research Fellow, Council of Scientific and Industrial Research (CSIR) New Delhi INDIA
Applied Physics, Indian Institute of Technology (BHU)
Varanasi-221 005 UP India
3. Jan. 1994- March, 1995
Senior Research Fellow, Council of Scientific and Industrial Research (CSIR) New Delhi INDIA
Applied Physics, Indian Institute of Technology (BHU)
Varanasi-221 005 UP India
4. April, 10th 1995- to-November, 2003
Lecturer
Department of Electrical & Electronics Engineering (EEE)
Birla Institute of Technology & Science, (BITS)
Pilani, Rajasthan 333 031 INDIA
5. December, 2003-to-May 2005
Asst. Professor
Department of Electrical & Electronics Engineering (EEE)
Birla Institute of Technology & Science, (BITS)
Pilani, Rajasthan 333 031 INDIA
6. June 24, 2005 to- June 2011
Senior Lecturer
Faculty of Engineering and Technology (FET)
Multimedia University (MMU) Malacca Campus, Malaysia
7. July-2011-to-Continue
Principal Lecturer
Faculty of Engineering and Technology (FET)
Multimedia University (MMU) Malacca Campus, Malaysia
Expertise

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Microelectronics Circuits and their Simulation/MEMS.

MOS modeling (SOI MOSFET and Double gate MOSFET)
Low power VLSI Design, (especially SRAM cell design)
Mixed Signal VLSI design

Publication
Book and Chapter in Book

1. Adaptation of the book Electronic Devices and Circuits authored by JIMMIE J.CATHEY Published by TATA
McGraw-HILL-New Delhi India
2. Electronic Devices and Integrated Circuits, 2008, Published by Prentice-Hall (Pvt.) Company, India
3. Digital VLSI Design, 2010, Prentice-Hall (Pvt.) Company-India
Journal

International Journal with Impact Factor

1. Local field configuration modes in a weakly guiding fibre with a conically annular core: An analytical study. Ajay
Kumar Singh, Prasad Khastgir, Onkar Nath Singh, Sant Prasad Ojha Japanese Journal of Applied Physics Part-2
Letters, Vol.32, No.1A/B, 15 Jan. 1993 (impact Factor 1.058) (ISSN Online: 1347-4065 / Print: 0021-4922)
2. Modal cutoff condition of an optical chiral fibre with different chiralities in the core and the cladding. Ajay Kumar
Singh, Kh.S.Singh, P.Khastgir, S.P.Ojha, O.N.Singh Journal of Optical Society of America-B Vol. 11, No.7,
1283, July 1994 (2011 ISI Impact Factor: 2.185) (ISSN: 0740-3224 | eISSN: 1520-8540)
3. Modal Characteristics of EM wave propagation through a chirofibre with different core and cladding
admittances Ajay Kumar Singh, P.Khastgir, O.N.Singh. Optics Communications (Netherlands) Vol.115, 256, 15Th
March 1995 (Impact Factor: 1.356) (ISSN: 0030-4018)
4. Power distribution in a chirofibre filled with distinct core and cladding chiralities. Ajay Kumar Singh, P.Khastgir,
O.N.Singh. Optical Fibre Technology (Academy Press) Vol.1, 264, 1995 (Impact Factor: 1.232) (ISSN: 1068- 5200)
5. Edge Potential effect on the operation of Short Channel devices A.K.Singh, S.Gurunaraynan, V.Ramachandran and
M.Umashanker. Microelectronics International, (Emerald Publication) Vol.20, No.3, 23-28, 2003 (Impact Factor:
0.600) (ISSN: 1356-5362)
6. AN ANALYTICAL STUDY OF SUBSTRATE CURRENT IN SUBMICRON MOS DEVICES. Gokul Vaidyanaath G.And A.K.
SINGH European Physical Journal B, Vol.42, 113-117 2004 (Impact Factor 1.534) (ISSN Print
Edition:1434-6028, ISSN Electronic Edition: 1434-6036)
7. Study of avalanche breakdown (MI) mode in submicron MOSFET device. A.K.Singh Microelectronics International,
(Emerald Publication) Vol.22, No.1, 16-20, 2005 (Impact Factor 0.600) (ISSN: 1356-5362)
8. A Theoretical Study of the Performance of Sub-micron MOSFET Devices in the presence of edge potential. V. P
Kiran, R.G. Kumar, A.K.Singh and S.Gurunarayanan International Journal of Electronics, Vol.92, No.5,
295-302, May 2005 (Impact Factor 0.440) (ISSN 0020-7217 (Print), 1362-3060 (Online)).
9. An analytical study of hot-carrier degradation effects in sub-micron MOS devices A.K.Singh The European
Physical Journal Applied Physics (EPJAP), Vol. 42, issue 2, 87-94, May 2008 (Impact Factor 0.771) (ISSN:
1286-0042 EISSN: 1286- 0050).
10. Design of Low-power, high performance, 8X8 bit multiplier using a Shannon-Based adder cell. C.Senthilpari, Ajay
Kumar Singh and K.Diwakar.Microelectronics Journal (Elsevier), Vol.39, 812-821, 2008 (Impact Factor
0.904) (ISSN: 0026-2692).
11. Highly stable Delta-Sigma Modulator for industrial applications. K.Diwakar, C.Senthilpari and Ajay Kumar
Singh> IEICE Electronics Express (Japan), Vol. 5, No. 15, 530-536, 2008 (Impact Factor 0.51) (ONLINE
ISSN:1349-2543).
12. A proposed SRAM cell for Low power consumption during write operation C.M.R Prabu and Ajay Kumar
Singh Microelectronics International (Emerald Publication), Vol.26, no.1, 37-42, 2009 (Impact Factor 0.600) (ISSN:
1356-5362)
13. Low Energy, Low latency and high speed array Divider circuit using a Shannon theorem based
adder C.Senthilpari, K.Diwakar, Ajay Kumar Singh Recent Patent of Nanotechnolgy, (Bentham Science
publisher), Vol.3, 61-72, 2009 (Impact Factor 1.275) (ISSN: 1872-2105, Print: ISSN: 2212-4020)
14. Delta-Sigma Modulator based multiplier.K.Diwakar, C.Senthilpari, Lim Way Soong, Ajay Kumar Singh.IEICE
Electronics Express, Vol.6, no.6, 322-328, 2009 (Impact Factor 0.51) (ONLINE ISSN:1349-2543).
15. Low power, Low Latency, High Throughput 16-bit CSA Adder using non-clocked Pass transistor logic. C.Senthilpari,
Ajay Kumar Singh and K.Diwakar. Journal of Circuits, System and Computers (World Scientific
Publishing), Vol.18, no.3, 581-596, 2009 (Impact Factor 0.281) (Print ISSN: 0218-1266, Online ISSN:
1793-6454)
16. Delta-Sigma Modulator Based Analog Multiplier with Digital Output,Krishna M.Diwakar, Chinnaiyan Senthilpari,
Ajay Kumar Singh, Lim Way Soong. Recent Patents on Electrical Engineering, (Bentham Science
Publishers Ltd.), Vol.2, 161-164, 2009 (H index 2) (ISSN: 2213-1116 (Print), ISSN: 2213-1132 (Online)).

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17. Vector quantized signal dependent Delta-Sigma modulator based high performance three-phase switching
converter. K.Diwakar, C.Senthilpari, Ajay Kumar Singh, Lim Way Soong IEICE Electronics Express, Vol.6,
no.17, 1259-1265, 2009 (Impact Factor 0.51) (ONLINE ISSN:1349-2543).
18. A comprehensive analytical study of double-gate MOSFET after considering quantum confinement parameter.Tiw
Pei Wen and Ajay Kumar Singh. Microelectron. J., Vol. 41, no. 2-3, 162-170, 2010 (Impact Factor 0.904)
((ISSN: 0026-2692).
19. Novel Eight-Transistor SRAM cell for Write Power Reduction. C.M.R.Prabhu and Ajay Kumar Singh IEICE
Electronics Express (ELEX), Vol.7, no.16, 1175-1181, 2010 (Impact Factor 0.51) (ONLINE
ISSN:1349-2543)..
20. "An Analytical Study of Undoped Symmetric Double Gate MOSFET (SDG)" Ajay Kumar Singh. International Journal
of Numerical Modeling: Electronic Networks, Devices and Fields, Vol. 24, issu6, 515-525,
November/December 2011 (Impact Factor 0.60) (Online ISSN: 1099-1204).
21. Low-Power Fast (LPF) SRAM cell for write/read operationC.M.R.Prabhu and Ajay Kumar Singh. IEICE Electronics
Express, vol. 6, no.18, pp. 1473-1478, 2011 (Impact Factor 0.51) (ONLINE ISSN: 1349-2543).
22. Performance Analysis of Reversed Binary Decision Diagram Pass Transistor Logic Synthesis,Thangavel
Bhuvaneswar, Vishnuvajjula Prasad, Ajay Kumar Singh, and Chinnaiyan Senthilpari. International Journal of
Circuit Theory and Applications Int. J. Circ. Theor. Appl. (2011), Published online in Wiley Online Library
(wileyonlinelibrary.com). DOI: 10.1002/cta.822 (Impact Factor 1.625), vol.41, issue 8, pp.844-853, August 2013,
(Online ISSN: 1097-007X)
23. A Data Aware (DA) 9T SRAM cell for Low Power Consumption and Improved Stability Ajay Kumar Singh, Mah Meng
Seong and C.M.R Prabhu International Journal of Circuit Theory and Applications Accepted in 2012 (Impact
Factor 1.625) (Online ISSN: 1097-007X)
24. Low Power and High Performance Single-Ended Sense Amplifier.Ajay Kumar Singh, Mah Meng Seong and C. M. R.
Prabhu. Journal of Circuits, Systems, and Computers (Published by World Scientific) Vol. 22, No. 7 (2013)
1350062 (12 pages) (Impact Factor 0.281) (Print ISSN: 0218-1266 Online ISSN: 1793-6454)
25. Reversed signal propagation BDD based Low Power Pass-Transistor Logic Synthesis. Thangavel Bhuvaneswar,
Vishnuvajjula Prasad, Ajay Kumar Singh, Accepted in IEEJ Transactions on Electrical and Electronic
Engineering (Published by Wiley) (Impact Factor 0 .343) (Online ISSN: 1931-4981) 2013 8 (S1): pp. S66
S71.
Papers in International Journal Without Impact Factor
1. Modal Cutoff condition of a doubly clad optical fibre filled with chiral material of distinct chiralities. Ajay Kumar
Singh, P.Khastgir, O.N.Singh. Photonics and Optoelectronics (Allerton Press Inc.) Vol.1, No.4, 223 1993.
2. A chirowaveguide filled with different core and chiralities: An analytical study in Microwave Region Ajay Kumar
Singh,Journal of Photonics and Optoelectronics (Allerton Press, INC.) New York (USA) Vol.5, No.4, 155-161, 1998.
3. An Analytical Model of Short Channel effects in Sub-micron MOS Devices. Ajay Kumar Singh. Journal of
Active and Passive Electronic Devices (Published by Old City Publishing, Inc.), Vol.2, No.4, 331-349,
2007 (ISSN: 1555-0281 (print), ISSN: 1555-029X (online))
4. Effect of Scaling on the Performance of the 4-Bit CPL Subtractor Circuit.European journal of Scientific
Research, Vol.20, N0.2, 239-248, 2008 (H index 9) (ISSN: 1450-216X)
5. Highly stable and wide input delta-sigma ADC for the precise control of stepper motors operating as actuators of
control valves in industry K.Diwakar, C.Senthilpari and Ajay Kumar Singh European Journal of Scientific Research,
Vol.22, no.1, 6-15, 2008 (H index 9) (ISSN: 1450-216X)
6. An efficient 16-bit Non-clocked Pass gates adder circuit with improved performance on power
constraint. C.Senthilpari, K.Diwaker, A. Arokiasamy, S.Kavitha, Ajay Kumar Singh European Journal of
Scientific Research, Vol.28, no.3, 451-461, 2009 (H ndex 9) (ISSN:1450-216X)
7. A Theoretical study of the threshold voltage sensitivity to process variation in symmetric double gate MOS
devices Ajay Kumar Singh Canadian Journal of Pure and Applied Sciences (CJPAS), Vol.3, no.3,
975-981, 2009 (ISSN 1920-3853).(Global Impact Factor for 2012 = 2.657)
8. Super-Fast Low Power (SFLP) SRAM Cell for Read/Write Operation C.M.R. Prabhu and Ajay Kumar
Singh International Journal of Computer Applications, Vol. 76, no.5, 1-5, August 2013, (ISSN0975 8887).
9. Power Efficient, High Performance SRAM array in 90nm CMOS Process Ajay Kumar Singh*, Mah Meng
Seong, International Journal Of Engineering And Computer Science, Vol.2, issue9, 2848-2855,
September 2013. (ISSN:2319-7242),
Papers in International Journals
1. Effect of the core size on the higher order modes of a chirofiber filled with different core and cladding
chiralities. Ajay Kumar Singh, R. Annatha Krishnan, R. Viswanathan, P. Khastgir. Journal of Optics (Published by
Optical Society of INDIA) Vol. 26, No. 4, 161, 1997 (ISSN: 0972-8821 (print version), ISSN: 0974-6900 (electronic
version)
2. A Theoretical Study of the effect of the core chirality and V-parameter on the Modal properties of a chirofiber Ajay
Kumar Singh, Rao Harshraj Journal of Optics (Published by Optical Society of India) Vol.28, No.2, 97-102, 1999
((ISSN: 0972-8821 (print version), ISSN: 0974-6900 (electronic version))
3. Design of low power SRAM cell for write/read operation Ajay Kumar Singh and CMR Prabhu Asian J. Phys,
Vol.17, No 2, 273-278, 2008 (ISSN: 0971-3093).
4. Binary-Aware high performance static random access memory cell, C.M.R Prabhu and Ajay Kumar Singh Asian
Journal of Physics, Vol.18, no.1, 57-62, 2009 ((ISSN: 0971-3093).

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Proceedings

Papers in International Conference

1. Power Deduction in Digital Signal Processing Circuit using Inventive CPL Subtractor Circuit C.Senthilpari, K.Diwakar,
C.M.R.Prabhu and Ajay Kumar Singh 2006 IEEE International Conference on Semiconductor Electronics,
29 Nov.-1Dec. 2006, Kuala lumpur, Malaysia, (ICSE 2006 Proceedings) pp.820-824.
2. Statistical analysis of Power delay estimation in adder circuit using non-clocked pass gate
families. C.Senthilpari, Ajay Kumar Singh and A.Arokiasamy 4th International Conference on Electrical and
Computer Engineering (ICECE) 2006, Dhaka, Bangladesh, pp.509-513.
3. Low Power and high speed 8x8 bit multiplier using non-clocked Pass Transistor Logics C.Senthilpari, K.Diwakar
and Ajay Kumar Singh International Conference on intelligence and advance systems, (ICIAS) 2007,
25th -28th Nov.2007, KL Convention Center, Kuala Lumpur, Malaysia, pp. 1374-1378 ISBN
1-4244-1356-7.
4. Design of Low Leakage SRAM cell for Write0 Operation C.M.R Prabhu, and Ajay Kumar Singh ISCO 2008,
Karpagam College of Engineering, Coimbatore-32, India (1-2 Feb.2008)
5. Switching converter with highly stable Delta-Sigma Modulator. K.Diwakar, C.Senthilpari and Ajay Kumar
Singh ICSE 2008, Johor Bahru, Malaysia (25th -27th) Nov. 2008, pp. 11-17
6. Analog Multiplier with high accuracy K. Diwakar, C.Senthilpari, Ajay Kumar Singh, Lim Way Soong International
Conference on Computational Intelligence, Communication Systems and Networks (IEEE Computer
Society) 2009, 23rd July-25th July 2009 Indore, India pp. 62-66.
7. Weights Binary Decision Diagram (WBDD) and its Application to Matrix Multiplication T.Bhuvaneswari,
V.C.Prasad, Ajay Kumar Singh, P.W.C. Prasad 2009 Conference on Innovative Technologies in Intelligent
Systems and Industrial Applications (CITISIA) 2009) Monash University, Sunway Campus, Malaysia,
25-26th July 2009 pp. 470-475.
8. 9T Balanced SRAM Cell for Low Power Operation CMR Prabhu , Ajay Kumar Singh, Ting Hou, Soo Pin IEEE
Symposium on Industrial Electronics and Applications (ISIEA 2009), 4-6 October 2009, Kuala Lumpur,
Malaysia, pp.68-72.
9. A Proposed Symmetric and Balanced 11-T SRAM Cell for lower power consumption Ajay Kumar Singh, CMR
Prabhu , Ting Hou, Soo Pin TENCON 2009 (International technical conference of IEEE) Singapore, 23-26
Nov.2009.
10. High speed and High throughput 8x8 bit multiplier using a Shannon-based adder cell C.Senthilpari,
K.M.Diwakar, Ajay Kumar Singh TENCON 2009 (International technical conference of IEEE) Singapore,
23-26 Nov.2009.
11. A Proposed 10-T Full Adder Cell for Low Power Consumption. Ajay Kumar Singh, C.M.R. Prabhu, Khaldon M.
Almadhagi, Saeed F. Farea, and Khaled Shaban, ECTI-CON 2010Thailand 19-21May 2010
12. Multiple BDD based Matrix Multiplication. T.Bhuvaneswari, V.C.Prasad, Ajay Kumar Singh, ICSE2010 Proc.
2010, Melaka, Malaysia-28-30 June 2010, pp. 130-134.
13. Design of 8-T SRAM cell using double gate nMOS transistor (8-T nDG SRAM Cell) for low power consumption during
write operation Ajay Kumar Singh, C.M.R. Prabhu, , Khaled Abdullah Shaban Binslim and Saeed Faisal Saeed
Farea 1st International Conference on Emerging Trends in Signal Processing and VLSI
Design, (SPVL-2010), GNEC Convention Center, Hyderabad- India, 11-13 June 2010, pp. 870-875.
14. A Proposed Tail Transistor Based SRAM Cell, C.M.R. Prabhu, Ajay Kumar Singh 2010 IEEE Symposium on
Industrial Electronics and Applications (ISIEA 2010), 3-5th October-2010, Penang Malaysia, pp.
505-508.
15. Low-Power Fast Static Random Access Memory Cell C.M.R. Prabhu, Ajay Kumar Singh 2010 IEEE Conference on
Open systems on Computer Applications and Industrial Electronics (ICCAIE 2010), December 5-7, 2010,
Seri Pacific Hotel Kuala Lumpur, Malaysia, pp. 5-8.
16. A Proposed 7T Bitline Coupled (BLC) SRAM Cell for Write Power Reduction. Ajay Kumar Singh, Mah Meng Seong,
C.M.R Prabhu ECTI-CON 2012, May 16-18, 2012, Hua Hin Thailand
17. Weights Binary Decision Diagrams (WBDD) Based Homology Detection T.Bhuvaneswari, V.C.Prasad, Ajay Kumar
singh International Conference on Information Technology, System and Management ( ICITSM 2012
). Date : 25 26 March, 2012, Proceedings @ IJARCSSE (ISSN : 2277 128X )
(http://www.ijarcsse.com/index.php ) IJITCS ( ISSN : 2091-1610 ).
Paper in National Conference
1. A General analytical study of propagation modes of weakly guiding Tapered Optical waveguides.Ajay Kumar Singh,
P.Khastgir, P.K.Choudhary, O.N.Singh, S.P.Ojha Proceedings of Antennas and Propagation Symposia-92 (CUSAT)
pp.152 Edited by: Prof. K.G.Nair and Prof. C.S.Sridhar
2. Mobility of carriers in the presence of Edge potential for short channel devices. J.Prashanth, S.Agrawal
and A.K.Singh INAE Conference on NANOTECHNOLOGY (ICON2003), Dec.22-23, 2003 Chandigarh (India)
pp.561-565.
Paper Presented in Conference but Not Published.
1. A study of the propagation characteristics of some Tapered and Chiral Optical waveguides. In National Laser
Symposium-1995, Organized under the National Laser Programme, Department of Atomic Energy,

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Govt. of India, at IRDE, Raipur, Dehradun. 10-14 February 1995.

2. Low Power SRAM Cell Design Techniques, MAL Technical & Innovation Symposium 2012, 17-20th July
2012-Infineon Melaka-Malaysia.
Seminar/Conference Attended and Presented Paper.
1. APSYM-CUSAT 92, National Symposium on Antennas and propagationCochin University of Science and Technology,
Department of Electronics, Kochi-682002. 29-31 December 1992.
2. National Laser Symposium-1995.Organized under the National Laser Programme, Department of Atomic Energy,
Govt. of India, at IRDE, Raipur, Dehradun. 10-14 February 1995
3. INAE Conference On NANOTECHNOLOGY (ICON-2003). Held at CSIO, Chandigarh, 22-23 December 2003
4. 1st International Conference on Emerging Trends in Signal Processing and VLSI Design, (SPVL-2010), GNEC
Convention Center, Hyderabad- India, 11-13 June 2010.
Article, Magazine and Interview

Invited Talk in Conference

1. MAL Technical & Innovation Symposium 2012, 17-20th July 2012-Infineon Melaka-Malaysia (Presented a technical
paper on Low Power SRAM Cell Design Techniques)
Others

1. Received President-MMU appreciation letter for teaching evaluation more than 4 for courses like circuit theory,
Applied Electronics, Fabrication technology etc.
2. Qualified NET exam Under CSIR (New Delhi-India) 1991.
3. Supervised many students for their Final Year Projects
4. Appointed as an Expert for many Proposal Defense Seminar for PhD as well as Master Students.

Research and Development

Project and Consultancy

MAJOR PROJECT
1. Project Title: Design and Implementation of a Power Efficient 0.2V, 32kb Embedded Memory compiler
in 45nm CMOS (Project Number: 03-02-01-SF0203)
Date of Commencement: August 2012
Awarding Agency: Ministry of Science and Technology (MOSTI) , Government of Malaysia, Under e-Science Fund
Amount of Project: Two Hundred Fifty three thousand only Ringgit Malaysia (RM253,000.00)
OTHER MINOR PROJECT
1. UGC (India) Project on Microprocessor based PCR Machine 1996-98 (Rs.10, 000).
2. UGC (India) Project on A theoretical Study of the propagation characteristics of Tapered Waveguide
1999-2000 (Rs.10,000).
3. Low Power ALU/SRAM design: Seed Fund MMU-Malaysia (2010-2011s) (RM 20,000)

Teaching and Supervision

Supervision Undergraduate and Postgraduate

PhD
1. Mr C. Senthil Pari: Design of 32-BIT Arithmetic Logic Unit Using Shannon Theorem Based Adder
Approach (Awarded-2010)
2. Mr. Krishna Moorthy Diwakar: Stable wide input Delta-sigma Modulator based single/three phase
switching converter (Awarded-2011)
3. Mr. C.M.R Prabhu: Design and implementation of low power, high performance SRAM
cell (Awarded-2012)
4. Ms. T. Bhuvaneswari: Binary Decision Diagram (BDD) based new methodologies for performance analysis
of analysis of pass transistor logic (PTL) synthesis and other applications (Defended)

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Master
1. Mr. Bhanu Pratap Singh: Implementation of Fast Multiplier Algorithms (Completed in 2003-BITS-Pilani
India, for his Master in Microelectronics Degree).
2. Mr. Mah Meng Seong: Design and Implementation of Power Efficient Embedded SRAM Array
(Submitted Thesis)-Multimedia University-Melaka-Malaysia

Academic Recognition and Leadership

Assessor and Examiner

1. External Moderator for the subject Analog Electronics 1 and 2 for centre for Diploma Programme (MMU-Melaka)
2011/2012/2013
2. Internal Examiner for MEng. (Microelectronics) final project of Mr Ung Chee Kong
3. As an expert member of Programme Conversion from Master to PhD (structure A)
4. Internal Examiner for the Master of Engineering in Embedded System dissertation of Ms Lim Siu Tean on
problem Design and Development of a Leakage current checking system for Semiconductor Devices.
5. Internal Examiner for Master of Engineering in Embedded System dissertation of Mr Tan Yoong Chuen on
Development of Wireless Power Consumption Monitoring System- 2012
6. Team Member of Lets Excel Programme (Probation 1-2012)
7. Member for Observation Session (2012) of the new Lecturers
8. PhD external examiner for Study and Development of Congestion Detection and Control Algorithm for Wireless
Sensor Networks (Sathyabama University Jeppiaar Nagar CHENNAI-India)
Referee and Evaluation Committee

Reviewer of International Journals

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9.

IEEE Transactions on Nanotechnology

International Journal of Electronics
IET Micro & Nano Letters'
IET Circuits, Devices and Systems
Microelectronics Journal
Journal of the Association of Arab Universities for Basic and Applied Sciences
Journal of Circuits, Systems and Computer
Computer Science Journal, Malaysia
International Journal of Signal and Imaging Systems Engineering (IJSISE).

Academic and Professional Association

Academic
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Industrial Training Programme (ITP-MMU)) (2005-2009)

Academic & Corporate Planning (ACP) Committee (FET-ACP-2010,2011)
English Waiver Committee for postgraduate (FET-MMU)
Internal reviewer for the research proposal-e-science Fund (FET-MMU)
MMU internal review panel (2011)
Research and Development committee of Faculty (MMU-2011, 2012, 2013)
FET equipment Evaluation Committee (MMU-2011-2012)
FET Credit Transfer Committee (MMU-2012/2013)
Nucleus Member of Educational Development Division (BITS-Pilani 1995-2000)
Nucleus Member of Engineering Service Division (BITS-Pilani 2000-2005 May)

Technical Services
1. Invited in technical program committee for CICSyN2010 (2nd Int Conference on Computational Intelligence,
Communication Systems and Networks).
2. Invited for a session chair for the ECTI-CON 2010 at Chiang Mai (Thailand) TPM2-2: Analog Circuits III
3. As a Chairperson for Infineon-MMU technical Symposium 2010.
4. Technical program committee for CIMSim2010 (Computational Intelligence, Modeling and Simulation 2010).
5. Technical program committee for UKSim2010 (UKSim 12th International Conference on Computer Modeling and
Simulation).
6. Technical program committee for ISMS2010 (1st International Conference on Intelligent Systems, Modeling and
Simulation).

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7. As a panel reviewer in Infineon-MMU technical Symposium held on 18th April 2011.

8. Technical Program Committee for ISCI 2012 (2012 IEEE Symposium on Computers & Informatics)
9. Technical program committee for ISI'12 (2012 International Symposium on Intelligent Informatics), Chennai, India,
August 4-5, 2012.
10. Reviewer in 4th International Conference on Intelligent and Advanced Systems (ICIAS 2012)
11. Technical Programme Committee of ISIEA 2012 (2012 IEEE Symposium on Industrial Electronics and Applications)
12. As an expert in ISBEIA 2012 (2012 IEEE Symposium on Business, Engineering & Industrial Applications).
13. Technical Committee of PECON 2012 (2012 IEEE International Power and Energy Conference)
14. Technical Committee of 2012 IEEE Symposium on Computer Applications and Industrial Electronics (ISCAIE 2012)
15. Technical Programme Committee of 2012 IEEE Symposium on Computer Applications and Industrial Electronics
(ISCAIE 2012)
16. As an expert for SCORED 2012 (2012 IEEE Student Conference on Research and Development)
17. Technical Programme Committee of Second International Symposium on Intelligent Informatics (ISI13), August
23-24, 2013, Mysore, India.
18. Technical Programme Committee of BEIAC 2013.
19. A a reviewer on the technical program committee for the 2014 IEEE Innovative Smart Grid Technologies Conference
- Asia (ISGT ASIA) (ISGT14).
20. The Technical Programme Committee of Third International Symposium on Intelligent Informatics (ISI14),
September 24-27, 2014, Delhi, India.
21. Technical program committee for IJCDS' V3 (Int Journal of Computing and Digital Systems).
22. Technical program committee for the 2014 IEEE Symposium on Computer Applications and Industrial Electronics
(ISCAIE 2014)
23. As a designated reviewer on the technical program committee for the 2014 IEEE TENSYMP - IEEE Region 10
Symposium (TENSYMP'14).
Membership- Professional Association
1. The Institution of Electronics and Telecommunication Engineers, India (Fellow)
2. IEEE Senior Member (80398921)
Services to the University

1.
2.
3.
4.
5.

Chairperson For Open Day 2011-FET-MMU-Melaka (Malaysia)

Chairperson For Digital VLSI Design Research Group-MMU-Malaysia (2012/2013)
Lab In-charge of Computer Based Training Lab.-MMU-Malaysia
Astt. Group Leader of ITP (Industrial Training Programme) for Electronics-FET-MMU-Melaka (Malaysia)-2009-2010)
Lab in-charge of VLSI CAD Lab (BITS-Pilani 2000-2005 May)

Referees

1. Prof. S.P. Gupta

Professor of Eminence, Department of Pharmaceutical Technology
Meerut Institute of Engineering and Technology
NH-58, Baghpat Road Bypass Crossing, Meerut-250 005 (U.P), India
Ph: + 91-121-2439019 ( or 2439057), ext. 2045; Mobile: + 91-9368222297
Fax: + 91-121-2439058, Email: spgbits@gmail.com
2. Prof. C Venkataseshaiah
Faculty of Engineering &Technology (FET)
Multimedia University,
Jalan Ayer Keroh Lama- 75450
Melaka-Malaysia
Ph.:+6-062523176
Fax: +606-2316552, Email: ventataseshaiah@mmu.edu.my

This curriculum vitae (CV) is generated from The Institute for Postgraduate Studies (IPS) website.
Copyright 2015 Multimedia University

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