A Dissertation

(For M.Tech. degree)

DIGITAL UP CONVERTOR FOR WCDMA

COMMUNICATION TRANSMITTER
Submitted by
Lovekesh Singla
Roll Number: (21113010)
Under the supervision of
Er. Sunita Rani
( Assistant Professor )
Electronics and Communication Engineering Section

Yadavindra College of Engineering,

Punjabi University Guru Kashi Campus,
Talwandi Sabo

CANDIDATE DECLARATION
I hereby certify that the work which is being presented in the thesis entitled DIGITAL
UP CONVERTOR for a WCDMA Communication Transmitter by Lovekesh in partial
fulfillment of required for the award the degree of M.Tech. (ECE 4th Sem.) submitted in the
Electronics and Communication Engineering section of Yadavindra College of Engineering,
Talwandi Sabo under Punjabi University, Patiala in the authentic record of my own work
carried out during a period from February 2013 to July 2013 under the supervision ofEr.Sunita
Rani (Assistant ProfesssorDeptt. ECE).The matter presented in this thesis has not been
submitted by me in any other University/ institute for the award of M.Tech. degree.

LOVEKESH
(Roll No. 21113010 )
This is to certify that the above statement made by the candidate is correct to the best of my
knowledge and belief.

(Er. SUNITA RANI)

Assistant Professor (ECE)
The M.Tech Viva-Voce Examination of KiranBala has been held on ____________ and
accepted.

(Signature of Internal Examiner)

(Signature of External Examiner)

(Signature of Deans Nominee)

(Signature of Section Incharge)
2

ABSTRACT
Digital communication refers to the transmission of information using discrete messages. There
are noteworthy advantages of transmitting data using discrete messages. It allows for enhanced
signal processing and quality control for example errors caused by noise and interference can
be detected and corrected systematically.
A communication system uses multirate filters in several ways. Multirate processing finds
application in shaping filters, in channelizers, in interpolators, in efficient bandwidth and
sample rate reduction schemes, in anti-alias filtering, and in many other applications. For a
digital up converter for a WCDMA Communication system. Multistage approach has been used
to reduce the hardware requirement. The results have been presented for a Vertex-5 device.

ACKNOWLEDGEMENT
It gives me immense pleasure to express my sincere gratitude to my esteemed supervisor
Mrs. Sunita Rani Assistant Professor (ECE), Yadavindra College of Engineering Talwandi
Sabo, for his dexterous guidance, invaluable and untiring help, ever encouraging attitude
and supervision throughout my study.
I owe my sincere gratitude to whole faculty and staff of Electronics and Communication
Engineering section of Yadavindra College of Engineering, Talwandi Sabo for their
encouragement and unfailing interest and sincere suggestions from time to time during this
work. I find no word to acknowledge the help and inspiration rendered by my family and
friends for this thesis. I thank almighty for giving me strength and blessing to complete the
thesis work.

Lovekesh

TABLE OF CONTENTS
Title

Page No.

Candidate Declaration....ii
Abstract..iii
Acknowledgement.iv
List of Figures.v
List of Tablesvii
Abbreviations.ix
Chapter 1:.1
Introduction.1
1.1introduction and motivation1
1.2 Problem Formulation5
1.3 Objective..5
1.4 Research mathodlogy...6
Organization of Thesis
Chapter 2:..8
Literature survey8
Literature survey8
chapter 3:........................................................................................................................11
Interpolation Filter Structure..11
3.1Introduction.15
3.1.2 Basic concepts of Interpolation.15
3.2 Different structures of Interpolation filter..17
3.2.1 Direct Form Structure of FIR Interpolato 20
3.2.2 Polyphase Structure of FIR Interpolator..17
3.2.3 Multistage Implementation of an Interpolator.20
3.2.4 Comparison of different structures21
3.3 Different types of Interpolatio22
3.3.1 Review of Interpolation filter design methods23
3.2.1.1 Window based Design24
3.3.1.2 Minimum Mean Square Error (MMSE) Design.24
5

3.1.1.3 Equiripple Linear Phase FIR desigen27

3.3.1.4 Half-band Filter based Design..28
3.3.1.5 Cascaded Integer Comb (CIC) filter based design..30
3.3.2 The Farrow Structure33
3.3 summary..36
chapter 4:.37
Basics of Field Programmable Gate Array..37
4.1Introduction37
4.2 A brief introduction toField-programmable gate arrays(FPGAs).37
4.3 Proposed Digital up Converter For WCDMA System39
4.3.1 Introduction39
4.4 Digital UP Converter For WCDMA System40
Chapter 5:.42
Simulation and Results.42
5(b) After optimization interpolator resource utilization and power consumption.46
Chapter 6:..............................................48
Conclusion and Future Work...48
6.1 Conclusion.48
6.2 Future Scope..48
References50

LIST OF FIGURE
6

Fig. 1.1 Block diagram of Transmitter

Fig. 1.2 Interpolator for a WCDMA System

Fig. 1.3 Block Diagram of an Interpolator.

Fig. 1.4 Typical waveforms and spectrum for interpolation by a factor L=3

Fig. 3.1.2(a) Block Diagram of an Interpolator

12

Fig. 3.1.2(b) Typical waveforms and spectrum for interpolation by a factor L=3

13

Fig. 3.2.1(a) Conventional Direct Form Structure of FIR Interpolator

16

Fig. 3.2.1(b) Efficient Direct Form Structure of FIR Interpolator

16

Fig. 3.2.1(c) Efficient Direct Form Structure with Reduced Number of Multiplications

17

Fig. 3.2.2(a) Polyphase Structure for Interpolator

19

Fig. 3.2.2(b) Signal representation in the Polyphase Interpolation (L=3)

19

Fig. 3.2.2(c) Polyphase Structure of an Interpolator with Commutator

20

Fig. 3.2.3(a) Multistage Interpolator

21

Fig. 3.3.1.2(a) Filter Design Set-up for MMSE method

25

Fig. 3.3.1.2(b) Impulse Response and Frequency Response of Minimum Mean Square Error
Interpolation Filter

26

Fig. 3.3.1.3(a) Magnitude Response of Low-Pass Equiripple Interpolation Filter for L=5
and 10

27

Fig. 3.3.1.4(a) Halfband Interpolation Filter Design for (N=15)

29

Fig. 3.3.1.4(b) Computationally Efficient Design of Halfband Interpolation Filter

29

Fig. 3.3.1.5(a) Block diagram of CIC filter

30

Fig. 3.3.1.5(b) Block diagram of CIC Interpolation filter

32

Fig. 4.3.1.5(c) K-stage CIC Interpolator

33

Fig. 4.3.1.5(d) Comparison of Magnitude response of CIC interpolator for single stage, two
stage, three stage and four stage

33

Fig. 3.3.2(a) The Farrow Structure

34

Fig. 3.3.2(b) Polyphase structure of M+1th FIR filter

34

Fig. 4.1 FPGA functional blocks

38

Fig.4.2(a)WCDMA Interpoltor System Generator Implementation

40Fig4.2(b) Filter section system generator implementation

41

Fig 5(a)Freuuency response of SRRC filter

42

Fig 5(b)Frequency response of 1st half band lowpass FIR filter

42

Fig 5(c) Frequency response of 2nd half band lowpass FIR filter

43

Fig 5(d) Frequency response of 3rd half band lowpass FIR filter

43

Fig 5(e) IF Data of I and Q channal

44

Fig.5(f) PSD for Single-Carrier WCDMA Waveform Centered at 12 MHz Spectral Mask
Shaded

44

Fig 5(g) RTLSchmatic diagram 45Fig 5(h) Internal RTL Schmatic diagram

45

LIST OF TABLE
Table 5.1 resources utilization and power consumption before optimization ofinterpolator for
WCDMA

46

Table 5.2 Resources utilization Summary, power consumption and max. operating
frequency

47

Table 5.3 Table of comparison

48

LIST OF ABBREVIATIONS
RRC

Root Raise Cosine

PSD

Power Spectral Density

DUC

Digital Up Converter

DDS

Direct Digital Synthesizer

10