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Design Study
Design Study
Design Study
This article is the documentation to a code snippet that originated from a discussion
on comp.dsp.
The task is to design a root-raised cosine filter with a rolloff of =0.15 that
interpolates to 64x the symbol rate at the input.
The code snippet shows a solution that is relatively straightforward to design and
achieves reasonably good efficiency using only FIR filters.
data, without utilizing any similarities or common terms between nearby output
samples.
Also, the high number of coefficients could be problematic (note that all given
coefficient counts could be divided by two in a hardware implementation due to the
symmetry of the impulse response)
ALIASING
To understand both pulse shape filtering and sample rate conversion, it may be
useful to recall that a digital signal represents a sequence of infinitely narrow pulses
at the sample locations.
The spectrum contains an infinite number of replicas, or aliases, at multiples of the
sampling rate:
stages,
Figure: impulse responses on absolute time axis (in units of symbol durations)
Even though the impulse responses of the final stages are short, they are far from
negligible with regard to the computational effort, as they run at a much higher
sample rate than the first stages.
As a general rule, it is often a good design strategy is to implement all filtering at
the lowest possible rate.
ERROR SIMULATION
The testbench eval_RRC_resampler.m from the code snippet evaluates the impulse
response of the design by performing the upsampling- and filtering operations on a
unity pulse test signal. The test signal is longer than the cascaded impulse responses
of all stages, thus no truncation error is introduced.
The signal may be considered a regular stream of pulses that repeats after the
(arbitrary) length of the test signal). Under that assumption, test signals are cyclic
and bandlimited, which allows to represent them exactly via a finite set of Fourier
coefficients. Thus, performing a simple FFT will convert freely between time- and
frequency domain, without the need for windowing and without introducing error other
than numerical inaccuracy.
An ideal root-raised cosine filtered reference signal is acquired by performing RRCfiltering on the test pulse in the frequency domain. Again, under the assumption that
the test pulse is one cycle of a periodic sequence, there is no approximation
involved: The impulse response has infinite length, but it is allowed to extend into
previous and following cycles. It wraps around.
Now with the response of an ideal RRC-filter as reference signal, it is time-aligned
with the filter output using the method described here (code here). The difference is
considered unwanted signal energy, and can be further divided into in-channel error
Figure: input signal, output signal and in-channel error signal after the ip1 filter.
Figure : input signal, output signal and in-channel error signal after the ip2 filter.
Figure: input signal, output signal and in-channel error signal after the ip3 filter.
Figure : input signal, output signal and in-channel error signal after the ip3 filter.
EQUALIZATION
The overall in-channel error is consistent with the design specifications of the
individual stages. Nonetheless, at a few frequencies, the errors add up constructively.
The in-band error can be improved by equalizing the frequency response of the
sample rate conversion in the pulse shaping filter.
This is implemented in the code snippet as option:
Run eval_RRC_resampler with mode="evalIdeal".
The frequency response of the sample rate conversion will be written
intointerpolatorFrequencyResponse.mat.
Run design_RRC_filter with mode=equalized. It will design an equalizer with
a pre-distorted frequency response into RRC_equalized.dat instead of the
conventionalRRC.dat file.
Re-run eval_RRC_resampler with mode=evalEqualized to evaluate the
design with the equalized RRC filter.
Use of the equalized pulse shape filter improves the average in-channel error by 1.3
dB and the peak error by more than 3 dB at no additional cost. The downside is that
the design process gets more complex.
Lacking accurate requirements, the design has not been optimized extensively for
use of equalization. By using equalization more aggressively, it may be feasible to
chop away a couple of taps from the rate conversion filters.
The picture below shows the error spectrum at the output of the equalized design:
The design target for the in-channel error of the equalized RRC filter
in design_RRC_filter.mis -43 dB.
Also the simulated peak error at the output of the design
from eval_RRC_resampler.m is -43.0 dB. This confirms that the equalized filter works
as expected.
SUMMARY
This article describes a design study on a root-raised cosine pulse shape/interpolateby-64 filter using cascaded FIR stages with the following features:
Filtering and rate conversion tasks are both specified and implemented
separately.
All filtering is implemented at the lowest possible rate.
An equalized FIR filter stage is used to reduce distortion on the wanted signal
The design process is somewhat lengthy but in the end quite straightforward, to the
point where it could be automated (add a couple of iteration loops to the design
scripts to iterate the required number of taps per stage).
At least for the given example, the savings over a plain polyphase implementation
are substantial. A further reduction in computational load is possible, if the sample
rate conversion is partly replaced with a non-FIR type filter (i.e. CIC)