ARMv4T Partial Instruction Set Summary

Operation
Move

Arithmetic

Logical

Compare

Branch

Load

Store

Load Multiple

Store Multiple
Miscellaneous

Pseudo-instructions

Move
with NOT
CPSR to register
SPSR to register
register to CPSR
register to SPSR
immediate to CPSR
immediate to SPSR
Add
with carry
Subtract
with carry
reverse subtract
reverse subtract with carry
Multiply
with accumulate
unsigned long
unsigned long with accumulate
signed long
signed long with accumulate
AND
OR
XOR
Bit clear
Rotates and shifts
Compare
negated
Bitwise test
Equivalence test
Branch
with link
and exchange
Return from subroutine
Load word
using User mode privileges
Load byte
signed
using User mode privileges
Load half-word
signed
Store word
using User mode privileges
Store byte
using User mode privileges
Store half-word
Pop, or Block data load
using User mode privileges
return and restore CPSR
Push, or Block data store
using User mode privileges
Swap word
Swap byte
Software interrupt
No operation
Load variable
Move constant
Load address
long version

Syntax
mov{cond}{s} Rd, shift_op
mvn{cond}{s} Rd, shift_op
mrs{cond} Rd, cpsr
mrs{cond} Rd, spsr
msr{cond} cpsr_fields, Rm
msr{cond} spsr_fields, Rm
msr{cond} cpsr_fields, #imm8r
msr{cond} spsr_fields, #imm8r
add{cond}{s} Rd, Rn, shift_op
adc{cond}{s} Rd, Rn, shift_op
sub{cond}{s} Rd, Rn, shift_op
sbc{cond}{s} Rd, Rn, shift_op
rsb{cond}{s} Rd, Rn, shift_op
rsc{cond}{s} Rd, Rn, shift_op
mul{cond}{s} Rd, Rm, Rs
mla{cond}{s} Rd, Rm, Rs, Rn
umull{cond}{s} RdLo, RdHi, Rm, Rs
umlal{cond}{s} RdLo, RdHi, Rm, Rs
smull{cond}{s} RdLo, RdHi, Rm, Rs
smlal{cond}{s} RdLo, RdHi, Rm, Rs
and{cond}{s} Rd, Rn, shift_op
orr{cond}{s} Rd, Rn, shift_op
eor{cond}{s} Rd, Rn, shift_op
bic{cond}{s} Rd, Rn, shift_op
Usually mov{cond}{s} Rd, shift_op
cmp{cond} Rn, shift_op
cmn{cond} Rn, shift_op
tst{cond} Rn, shift_op
teq{cond} Rn, shift_op
b{cond} label
bl{cond} label
bx{cond} Rm
Usually mov pc, lr or bx lr
ldr{cond} Rd, am2
ldr{cond}t Rd, am2P
ldr{cond}b Rd, am2
ldr{cond}sb Rd, am3
ldr{cond}bt Rd, am2P
ldr{cond}h Rd, am3
ldr{cond}sh Rd, am3
str{cond} Rd, am2
str{cond}t Rd, am2P
str{cond}b Rd, am2
str{cond}bt Rd, am2P
str{cond}h Rd, am3
ldm{cond}{am4L} Rd{!}, {reglist}
ldm{cond}{am4L} Rd{!}, {reglistpc}^
ldm{cond}{am4L} Rd{!}, {reglist+pc}^
stm{cond}{am4S} Rd{!}, {reglist}
stm{cond}{am4S} Rd{!}, {reglist}^
swp{cond} Rd, Rm, [Rn]
swp{cond}b Rd, Rm, [Rn]
swi{cond} imm24
nop{cond}
ldr{cond} Rd, label
ldr{cond} Rd, =imm32
adr{cond} Rd, label
adr{cond}l Rd, label

Page Num.
A456 (156)
A468 (168)
A460 (160)
A460 (160)
A462 (162)
A462 (162)
A462 (162)
A462 (162)
A46 (106)
A44 (104)
A498 (198)
A476 (176)
A472 (172)
A474 (174)
A466 (166)
A454 (154)
A4111 (211)
A4109 (209)
A480 (180)
A478 (178)
A48 (108)
A470 (170)
A426 (126)
A412 (112)
A456 (156)
A425 (125)
A423 (123)
A4107 (207)
A4106 (206)
A410 (110)
A410 (110)
A419 (119)
A411 (111)
A437 (137)
A450 (150)
A440 (140)
A446 (146)
A442 (142)
A444 (144)
A448 (148)
A488 (188)
A496 (196)
A490 (190)
A492 (192)
A494 (194)
A430 (130)
A432 (132)
A434 (134)
A484 (184)
A486 (186)
A4102 (202)
A4104 (204)
A4100 (200)

N
N

N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N

S updates
Z
C
Z
C

Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z

C
C
C
C
C
C
C?
C?
C?
C?
C?
C?
C
C
C
C
C
C
C
C
C

V
V
V
V
V
V

V?
V?
V?
V?

V
V

Action and Comments

Rd := shift_op
Rd := NOT(shift_op)
Rd := CPSR
Rd := SPSR; Not valid in System or User modes
CPSR := Rd (selected bytes only)
SPSR := Rd (selected bytes only); Not valid in System or User modes
CPSR := imm8r (selected bytes only)
SPSR := imm8r (selected bytes only); Not valid in System or User modes
Rd := Rn + shift_op
Rd := Rn + shift_op + Carry
Rd := Rn shift_op
Rd := Rn shift_op NOT(Carry)
Rd := shift_op Rn
Rd := shift_op Rn NOT(Carry)
Rd := Rm Rs (lower 32 bits only)
Rd := (Rm Rs) + Rn (lower 32 bits only)
RdHi,RdLo := unsigned(Rm Rs)
RdHi,RdLo := unsigned(RdHi,RdLo + Rm Rs)
RdHi,RdLo := signed(Rm Rs)
RdHi,RdLo := signed(RdHi,RdLo + Rm Rs)
Rd := Rn AND shift_op
Rd := Rn OR shift_op
Rd := Rn XOR shift_op
Rd := Rn AND NOT(shift_op)
Usually Rd := shift_op; May use other instructions (eg, add, sub)
Update CPSR flags for Rn shift_op
Update CPSR flags for Rn + shift_op
Update CPSR flags for Rn AND shift_op
Update CPSR flags for Rn XOR shift_op
R15 := address of label; Jump to label
R14 := R15 4; R15 := address of label; Call subroutine/function at label
R15 := Rm; Changes to Thumb mode if bit 0 of Rm is 1
R15 := R14
Rd := word stored at address am2
Rd := word stored at address am2P; Usually used in non-User modes
Rd := ZeroExtend(byte at address am2)
Rd := SignExtend(byte at address am3)
Rd := ZeroExtend(byte at address am2P); Usually used in non-User modes
Rd := ZeroExtend(half-word at address am3)
Rd := SignExtend(half-word at address am3)
Store word in Rd at address am2
Store word in Rd at address am2P; Usually used in non-User modes
Store byte in Rd[7..0] at address am2
Store byte in Rd[7..0] at address am2P; Usually used in non-User modes
Store half-word in Rd[15..0] at address am3
Load all listed registers from address in Rd
Load all listed registers (PC register not listed) from address in Rd; Not valid in User mode
Load registers, CPSR := SPSR, branch to PC; Not valid in User or System modes
Store all listed registers to address in Rd
Store all listed registers to address in Rd; Usually used in non-User modes
temp := word at address in Rn, store Rm to address in Rn, Rd := temp
temp := ZeroExtend(byte at address in Rn), store Rm[7..0] to address in Rn, Rd := temp
Branch-and-link to address 0x00000008 in Supervisor mode
Does nothing; translates to mov{cond} r0, r0
Rd := word stored at address label; translates to ldr{cond} Rd, [r15, #offset]
mov Rd, #imm32 or ldr Rd, [r15, #offset]
add Rd, r15, #offset
Two-instruction form of adr

ARMv4T Partial Instruction Set Tables

Register Names and Aliases
Reg
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13
r14
r15

Aliases
a1
a2
a3
a4
v1
v2
v3
v4
v5
v6 or sb
v7 or sl
v8 or fp
ip
sp
lr
pc

Data Processing Mode: shifter_op

Purpose in ARM Thumb Procedure Call Standard

Argument/result/scratch register 1
Argument/result/scratch register 2
Argument/result/scratch register 3
Argument/result/scratch register 4
Variable register 1
Variable register 2
Variable register 3
Variable register 4
Variable register 5
Variable register 6; sometimes Stack Base register
Variable register 7; sometimes Stack Limit register
Variable register 8; usually Frame Pointer register
Intra-procedure-call scratch register
Stack Pointer
Link Register
Program Counter

Operation
Immediate value
Register
Logical shift left immediate
Logical shift left by register
Logical shift right immediate
Logical shift right by register
Arithmetic shift right immediate
Arithmetic shift right by register
Rotate right immediate
Rotate right by register
Rotate right with extend

28

24

N Z C V Undef.

16

Undef.

8 7 6 5 4

Undef.

I FT

Mode

Program Status Register Modes

Value
0b10000
0b10001
0b10010
0b10011
0b10111
0b11011
0b11111

Mode
User
Fast Interrupt
Interrupt
Supervisor
Abort
Undefined
System

Accessible registers
PC, R14R0, CPSR
PC, R14_fiqR8_fiq, R7R0, CPSR, SPSR_fiq
PC, R14_irqR13_irq, R12R0, CPSR, SPSR_irq
PC, R14_svcR13_svc, R12R0, CPSR, SPSR_svc
PC, R14_abtR13_abt, R12R0, CPSR, SPSR_abt
PC, R14_undR13_und, R12R0, CPSR, SPSR_und
PC, R14R0, CPSR

Program Status Register Fields: fields

Suffix
c
x
s
f

Bits in PSRs
07
815
1623
2431

Description
Control field mask
Extension field mask (no bits currently defined)
Status field mask (no bits currently defined)
Flags field mask (bits 2427 undefined)

Description
Equal
Not equal
Carry set/unsigned higher or same
Carry clear/unsigned lower
Minus/negative
Plus/positive or zero
Overflow
No overflow
Unsigned higher
Unsigned lower or same
Signed greater than or equal
Signed less than
Signed greater than
Signed less than or equal
Always (unconditional, default)

#imm5
Rs
#imm5
Rs
#imm5
Rs
#imm5
Rs

Allowed 031 only

Allowed 132 only
Allowed 132 only
Allowed 131 only

Operation
Pre-indexed Immediate offset
Zero offset
Register offset
Scaled register offset

Syntax
[Rn, #imm12]{!}
[Rn]
[Rn, Rm]{!}
[Rn, Rm, lsl #imm5]{!}
[Rn, Rm, lsr #imm5]{!}
[Rn, Rm, asr #imm5]{!}
[Rn, Rm, ror #imm5]{!}
[Rn, Rm, rrx]{!}
[Rn], #imm12
Post-indexed Immediate offset
Register offset
[Rn], Rm
Scaled register offset [Rn], Rm, lsl #imm5
[Rn], Rm, lsr #imm5
[Rn], Rm, asr #imm5
[Rn], Rm, ror #imm5
[Rn], Rm, rrx

Condition flags state

Z set
Z clear
C set
C clear
N set
N clear
V set
V clear
C set and Z clear
C clear or Z set
N equal to V
N not equal to V
Z clear and N equal to V
Z set and N not equal to V
Irrelevant

Cmts.
[Rn, #0]
031 only
132 only
132 only
131 only

Suffix
ia
ib
da
db

Non-stack Addressing Mode

Increment after
Increment before
Decrement after
Decrement before

Suffix
ia
ib
da
db

Non-stack Addressing Mode

Increment after
Increment before
Decrement after
Decrement before

Operation
Post-indexed Immediate offset
Register offset
Scaled register offset

Syntax
[Rn], #imm12
[Rn], Rm
[Rn], Rm, lsl
[Rn], Rm, lsr
[Rn], Rm, asr
[Rn], Rm, ror
[Rn], Rm, rrx

031 only
132 only
132 only
131 only

Cmts.

#imm5
#imm5
#imm5
#imm5

Suffix
fd
ed
fa
ea

Stack Addressing Mode

Full descending
Empty descending
Full ascending
Empty ascending

Store Multiple Data Mode: am4S

Suffix
ea
fa
ed
fd

Stack Addressing Mode

Empty ascending
Full ascending
Empty descending
Full descending

Exception Vector Table

Address
0x00000000
0x00000004
0x00000008
0x0000000C
0x00000010
0x00000014
0x00000018
0x0000001C

Mode
Supervisor
Undefined
Supervisor
Abort
Abort
(None)
Interrupt
Fast Interrupt

Exception Type
Reset
Undefined instruction
Software interrupt
Prefetch abort (instruction fetch abort)
Data abort (data access memory abort)
(Not used)
Normal-priority interrupt
High-priority (fast) interrupt

Miscellaneous

Load or Store with Translation Mode: am2P

Optional Condition Field: cond

Mnemonic
EQ
NE
CS or HS
CC or LO
MI
PL
VS
VC
HI
LS
GE
LT
GT
LE
AL

Load Multiple Data Mode: am4L

Comments

Load or Store Word/Unsigned Byte Mode: am2

Program Status Register Format

31

Syntax
#imm8r
Rm
Rm, lsl
Rm, lsl
Rm, lsr
Rm, lsr
Rm, asr
Rm, asr
Rm, ror
Rm, ror
Rm, rrx

031 only
132 only
132 only
131 only

Load or Store Half-Word/Signed Byte Mode: am3

Operation

Syntax

Comments

Pre-indexed Immediate offset

Zero offset
Register offset
Post-indexed Immediate offset
Register offset

[Rn, #imm8]{!}
[Rn]
[Rn, Rm]{!}
[Rn], #imm8
[Rn], Rm

Note: not imm8r

Same as [Rn, #0]

Symbol
imm5
imm8
imm8r
imm12
imm24
imm32
{s}
N
Z
C
V
C?
V?
I
F
T
{reglist}
{reglistpc}
{reglist+pc}
{!}

Note: not imm8r

Meaning
Immediate 5-bit number, either 031, 132 or 131
Immediate 8-bit number, between 0255
A 32-bit number that can be formed by rotating an 8-bit
number (0255) by an even number between 0 and 30
Immediate 12-bit number, between 04095
Immediate 24-bit number, between 016,777,215
Immediate 32-bit number, between 04,294,967,295
If present, the instruction will update the condition flags
Negative flag: 1 if result is negative
Zero flag: 1 if result is zero
Carry flag
Signed Overflow flag
Carry flag ends in an unpredictable state, if flags are set
Overflow flag ends in an unpredictable state, if flags are set
Interrupt Disable bit in the PSRs: 1 to disable interrupts
Fast Interrupt Disable bit: 1 to disable fast interrupts
ARM or Thumb state: 0 for ARM execution, 1 for Thumb
List of registers separated by commas or dashes, surrounded by braces, eg, {r0,r1,r2} or {r0r3,r5}
List of registers that does not include PC (R15)
List of registers that does include PC (R15)
If present, the instruction updates the base register after
the memory transfer.
Post-indexed accesses always update the base register
Either + or - may be supplied; + is assumed if not present

This document contains a summary of the ARMv4T instruction set architecture in tabular format. It does not list every instruction available in the
ARM architecture: the coprocessor instructions, in particular, have not been listed. Page numbers refer to both the printed and on-line versions of
the ARM Architecture Reference Manual, Second Edition, published by Addison-Wesley in December 2000 (ISBN 0-201-73719-1).
This document was created by John Zaitseff for the Digital Systems Laboratory at the University of New South Wales.
Copyright 2003, School of Electrical Engineering and Telecommunications, University of New South Wales, Sydney, Australia. All rights reserved.