Department of Electronics &Communications Engineering

PVP Siddhartha Institute of Technology

01: VLSI DESIGN

Programme: B.Tech (ECE)
Year: III / IV
Course: (Core/elective/depth/breath)
Credits: 4

Semester: 6
Hours: 4+1

Course Context and Overview (100 words):

This is an introductory course in VLSI Systems and Design. CMOS logic circuits and
fabrication process will be introduced first, followed by advanced topics such as design
optimization for speed, power and testing. At the completion of this course, a student should be
able to design and analyze digital circuits.
Prerequisites Courses: DICA
Course Outcomes:

At the end of the course student will be able to

Demonstrate the knowledge of different VLSI fabrication processes and CMOS Logic
Design.

Design different MOS logical circuits.

Identify the interactions between MOSFET parameters and circuit performance

Analyze the effects of Scaling.

Configure PLDs, CPLDs and FPGAs.

Design Digital Systems with VHDL programming.

Course Contents:

Topics

Lecture Hours

UNIT I Introduction:
Introduction to VLSI Design
Introduction to IC Technology
MOS,
PMOS, NMOS
CMOS production process
BiCMOS production process

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1
1
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2
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Department of Electronics &Communications Engineering

PVP Siddhartha Institute of Technology

Comparison between CMOS and BiCMOS

UNIT-II BASIC ELECTRICAL PROPERTIES:

Basic electrical properties of MOS Circuits:; Ids Vds relations

MOS transistor threshold voltage

gm , gds ,

wo,, pass transistor,

nMOS inverter

Various pull ups

CMOS figure of merit

Inverter analysis and design

Bi-CMOS inverters

Latch-up

10

UNIT-III : MOS and BiCMOS Circuit Design Processes:

CMOS Design flow MOS Layers, Stick diagrams

Design rules and layout

Design rules for wires

Contacts and transistors layout diagrams for NMOS & CMOS inverters

2um design rules

1.2um design rules,

Layout and symbolic diagrams

UNIT-IV : Basic circuit concepts

Basic circuit concepts Introduction

Sheet Resistance delays

Driving its concept to MOS

calculations large capacitance loads

Course Design Template version 1.0

Department of Electronics &Communications Engineering

PVP Siddhartha Institute of Technology

Wiring capacitance and Delay calculations

Fan in & fan-out, choice of layers

Transistor switches

Realization of gates

UNIT-V : SCALING OF MOS CIRCUITS

scaling models and factors

Scaling factors

Limitations of scaling

Limitations of scaling

Switch logic and gate logic

UNIT-VI : SEMICONDUCTOR INTEGRATED CIRCUTE DESIGN

Introduction

PLA

PAL

FPGAs

CPLDs

Standard cells

Semicustom design and full custom designs

UNIT-VII : DIGITAL DESIGN USING HDL

VLSI design Flow
Hardware simulation and synthesis
Elements of VHDL, Packages

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Variable assignments and sequential statements.

Subprograms

Comparison of VHDL and Verilog HDL

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UNIT-VIII : VHDL MODELLING

Inside a logic synthesizer

Constraints and technology libraries

functional gate level verification

Place and route ,post layout simulation

Course Design Template version 1.0

Department of Electronics &Communications Engineering

PVP Siddhartha Institute of Technology

Static timings and net-list formats

Programming approach for VHDL synthesis

Learning resources:
Text books;
1. Essentials of VLSI Circuits and Systems- Kamran Eshraghian, Douglas and A Pucknell, PHI.
PrivateLimited, 2005.
2 Principles of CMOS VLSI Design - Weste and Eshraghian, Pearson Education, 1999.
References:
1. Chip Design for Submicron VLSI: CMOS Layout & Simulation, - John P. Uyemura,
ThomsonLearning,2005.
2. Introduction to VLSI Circuits and Systems - John .P. Uyemura, JohnWiley, 2003.
3. Digital Integrated Circuits - John M. Rabaey, PHI, EEE, 1997.
4. Modern VLSI Design - Wayne Wolf, Pearson Education, 3rd Edition, 1997.
5. VLSI Technology S.M. SZE, 2nd Edition, TMH, 2003.
6. Fundamentals of Logic Design with VHDL Stephen. Brown and ZvonkoVranesic, TMH, 2005
Additional Resources:
1. http://nptel.ac.in/

Program Outcomes (POs):

Students will be able to:
a) Demonstrate knowledge of Mathematics, Random Process, Numerical Methods, Physics
and Chemistry
b) Design analog and digital electronic circuits and conduct experiments, analyze and
interpret data.
c) Develop communication systems those meet the desired specifications and requirements.
d) Visualize and work on laboratory and multidisciplinary tasks.
e) Identify, formulate and solve communication engineering problems.
f) Understand professional and ethical responsibilities
g) Communicate effectively in both verbal and written form
h) Have confidence for self-education and ability for life-long learning.
i) Understand the impact of engineering solutions on society and also will be aware of
contemporary issues.
j) Demonstrate skills to use modern engineering tools, software and equipment to analyze
problems in communication engineering.
k) Participate and succeed in competitive examinations like GRE, GATE etc.

Gain knowledge of different VLSI fabrication processes and CMOS Logic Design.

Course Design Template version 1.0

Department of Electronics &Communications Engineering

PVP Siddhartha Institute of Technology

Design different MOS logical circuits.

Identify the interactions between MOSFET parameters and circuit performance

Analyze the effects of Scaling.

Program PLDs, CPLDs and FPGAs.

Design Digital Systems with VHDL programming.

Table: Mapping of course outcomes with program outcomes (CO/ Competency PO Matrix):
COS
/POS
CLO 1

CLO 2

CLO 3

CLO 4

CLO 5

CLO 6

M1 - Lecture interspersed with discussions

M3 - Tutorial
M5 - Group Discussion
M7 Presentation (PPT)
M9 - Video Lectures (NPTEL, SONET, MIT etc)
Instructional Methods:

M2 - Lecture with a quiz

M4 Demonstration (Models/Charts/Field Visit)
M6 - Group Assignment/Projects
M8 Asynchronous Discussions

COs

CLO/ Competency

CLO 1

Gain knowledge of different VLSI fabrication processes and

Instructional Methods

CMOS Logic Design.

CLO 2

BUILD Design concepts for different MOS logical circuits .

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M1, M3, M7,M9

M1, M3, M7,M9

Department of Electronics &Communications Engineering

CLO 3

Identify the interactions between MOSFET

PVP Siddhartha Institute of Technology

parameters and
M1, M3, M7,M9

circuit performance.
CLO 4

Understand the effects of Scaling.

M1, M3, M7,M9

CLO 5

Program PLDs, CPLDs and FPGAs.

M1, M3, M7,M9

CLO 6

Design Digital Systems with VHDL programming.

M1, M3, M6,M7

Assessment / Evaluation Methods:

Assessment Tool
MID -1
Online Quiz-1
MID-2
Online Quiz-2
Final Examination

Weightage(Marks)
15
25
10
15
25
10
Best of two
75

Prepared By: Ch.Gangadhar

Last Update: 31/01/2015

Course Design Template version 1.0