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IEEE ELECTRON DEVICE LETTERS, VOL. 34, NO. 9, SEPTEMBER 2013

Highly Scalable Horizontal Channel 3-D NAND

Memory Excellent in Compatibility With
Conventional Fabrication Technology
Kiwamu Sakuma, Haruka Kusai, Shosuke Fujii, and Masato Koyama

Abstract We developed a stacked horizontal channel type

floating gate (HC-FG) NAND memory; a 3-D stacked NAND array
composed of conventional FG cells. With this cell structure, a
wide program/erase (P/E) window is obtained, accompanied by
superior read disturb immunity, P/E endurance, and data retention. In addition, we propose a low-cost layer select transistor
(LST) that is easily integrated with the HC-FG cell. Because the
3-D memory composed of the HC-FG cell and the LST has good
compatibility with conventional fabrication technology, further
bit cost scaling is expected.

Fig. 1. (a) Birds eye view of HC-FG NAND structure. (b) Equivalent circuit.

Index Terms 3-D NAND Flash memory, floating gate (FG)

cell, stacked horizontal channel.

I. I NTRODUCTION

LOATING gate (FG) type NAND Flash has been used

in many memory products. In addition, the demand for
high density and low cost has been satisfied by the reduction
of cell size and by increasing the number of memory levels
in a cell. Recently, prompted by the limits of reduction of
cell size, 3-D memory devices have been proposed [1][5].
In addition, 3-D NAND devices with FG-type cells, such as
dual control gate-surrounding FG [2] and sidewall control
pillar [3], have been suggested. The cell size of these structures
is, however, large owing to the gate-all-around (GAA) type
structure with FG. Their split-gate type structure complicates
the cell operation.
In this letter, we propose a 3-D memory structure with
a conventional FG cell. Compared with the 3-D FG type
structures reported so far, horizontal channel type FG
(HC-FG) structure has higher compatibility with the current
2-D FG structure in terms of fabrication process and operation
schemes. Furthermore, we introduce a lower cost layer selective structure that can be formed using a self-aligned process
and demonstrate its operation.
II. D EVICE A RCHITECTURE
Fig. 1 shows a schematic birds eye view and the equivalent circuit of the HC-FG NAND structure. Stacked memory

Manuscript received June 11, 2013; revised July 10, 2013; accepted July 18,
2013. Date of publication August 2, 2013; date of current version August 21,
2013. The review of this letter was arranged by Editor T. San.
The authors are with the Corporate Research and Development Center, Toshiba Corporation, Kawasaki 212-8582, Japan (e-mail: kiwamu.
sakuma@toshiba.co.jp).
Color versions of one or more of the figures in this letter are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/LED.2013.2274472

Fig. 2.

Schematic view of HC-FG NAND cells.

strings are connected in common to twisted-layout layer select

transistor (LST) through stacked string select line (SSL), and
shared the gate electrode for word lines (WLs) and other
transistors.
III. HC-FG NAND C ELL
Fig. 2 shows a schematic view of the HC-FG NAND
cell. Cells with the conventional FG structure are stacked
perpendicular to the substrate. In this structure, FG must
be separated between adjacent cells to avoid short circuit.
Process flow of HC-FG NAND stacked cell is shown in Fig. 3.
As shown in Fig. 3, stacked FG cell is formed by channel-first
process similar to that of the 2-D FG cell.
Fig. 4(a) shows an annular dark-field scanning transmission electron microscope (ADF-STEM) image along WL
direction of HC-FG NAND stacked cells. Four NAND strings
with double-gate structure are stacked perpendicular to the
substrate. Furthermore, it is clearly observed that conventional
FG type structure is well fabricated from the bright-field
STEM (BF-STEM) image of the cell shown in Fig. 4(b).
Because FG is formed on the recessed Si region, FGs can
be formed in self-alignment with respect to stacked channels.
The SEM image along bit line (BL) direction of the HC-FG
NAND structure is shown in Fig. 4(c). WLs with 1-m height

0741-3106 2013 IEEE

SAKUMA et al.: HIGHLY SCALABLE HORIZONTAL CHANNEL 3-D NAND MEMORY

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Fig. 3. Process flow of HC-FG NAND cells. (a) SiO2 /Si layers and hard
mask deposition, (b) line/space etch, (c) Si recess, (d) fill the space by FG,
(e) Si etch to separate adjacent FGs, (f) hard mask and SiO2 recess to divide
FG at WL etch, and (g) deposition of IPD and CG.

(b) IP D

(a)
4 th

C hannel S i

F G cell
CG

18nm

FG

3 rd F G cell
T unnel O x.

30nm

2 nd F G cell

(c)

T op view after W L etch

Fig. 5. (a) P/E speed of HC-FG NAND cell. (b) Read disturb of HC-FG NAND
cells. (c) Id Vg characteristics during 10-k P/E cycling of HC-FG NAND cell.
(d) Data retention for multilevel of HC-FG NAND cells at RT.

WL
1 st F G cell
50nm

W L length 100nm

1 m

Fig. 4. (a) ADF-STEM image along WL direction of HC-FG NAND stacked

cells with channel height of 18 nm. (b) BF-STEM image of the cell. (c) SEM
image along BL direction of HC-FG NAND structure.

are formed. Because the adjacent FGs must be separated from

one another, a hard mask was recessed to the end side of a
channel before WL etching, as shown in Fig. 3(f).
Program/erase (P/E) operation in the HC-FG NAND cell can
be carried out at the same voltage conditions as for 2-D FG
cell. Here, applying a voltage to the SSL and LST allows BL
bias to be transferred to the selected (or nonselected) memory
strings channel. Fig. 5 shows the cell characteristics of the
HC-FG NAND cell with channel height of 70 nm. The P/E
speed is shown in Fig. 5(a). V th window after P/E operation is
over 7 V, which is wide enough for multilevel operation. Read
disturb is measured as a function of read voltages in Fig. 5(b).
The threshold voltage shift (Vth) is < 0.03 V after 100-k
cycles of read operation with the read voltage of 7 V. Fig. 5(c)
shows Id Vg characteristics and V th shift during 10-k P/E
cycle operation. Increase of V th after 10-k cycling stress is
< 0.5 V for both P/E states. Data retention characteristics at
RT for multilevel operation are shown in Fig. 5(d). V th at
7 V V th window is extrapolated to be < 0.5 V after 10 years.
IV. LST S TRUCTURE
For 3-D NAND with horizontal channel structure, BL layer
selecting is more difficult than in vertical channel structure [1].
With regard to the layer selective structure of stacked BL, PN
diode [4] and normally-on SSL [5] are proposed. Because it
is, however, necessary to form a contact on a source line of
each layer, in the former structure, the formation process step
increases with increasing the number of stacked layers. On the
other hand, the latter is necessary to form normally-on channel

Fig. 6. (a) Schematic view of LST structure with common via. (b) Process
flow of LST structure. Doped area can be defined using stair-like structure.

region in each layer with sufficient precision. Therefore, a

layer selecting structure with simple process and low cost
is required. We propose a novel layer selective structure that
allows formation of normally-on regions through self-aligned
process.
Fig. 6(a) shows a schematic view of the newly proposed
LST structure. As shown in Fig. 6(a), the number of contact
vias is only one regardless of the number of the stacked BLs.
Process flow of the LST structure is shown in Fig. 6(b).
Reduction of the number of fabrication steps can be
achieved by doping impurities all at once for multilayers.
Where, the most important issue is the need to form the
doped region with high precision. Fig. 7(a) and (b) shows a
cross-sectional SEM image along BL direction of the LST
structure and the results of analysis using scanning spread
resistance microscopy (SSRM) [6] with respect to the stacked
BLs region of the LST structure, respectively. The sample
was annealed at 1000 C for 10 s after arsenic (As) doping.
Because SSRM enables us to evaluate local resistance value of
a specimen, we can determine the junction position accurately
[Fig. 7(b)]. From these results, we conclude that unintended
diffusion of As between the upper and lower Si layers (vertical
direction) does not occur. On the other hand, severe horizontal
diffusion of As occurs, leading to 70-nm overlap of doped
layer between the upper and lower Si. This horizontal diffusion
is not peculiar to our structure but is common to all structures

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IEEE ELECTRON DEVICE LETTERS, VOL. 34, NO. 9, SEPTEMBER 2013

Fig. 8.
Fig. 7. Cross-sectional (a) SEM image along BL direction of LST structure
and (b) SSRM image of stacked BLs [dashed line in Fig. 6(a)]. (c) Id Vg
characteristics of stacked BLs with LST. The amount of current depends on
the number of BLs selected by LST. Solid line: sum of the currents flowing
along each layer.
TABLE I
C OMPARISON OF 3-D FG T YPE M EMORY S TRUCTURE

2-D FG equivalent half pitch for various FG structure.

cell has higher compatibility with 2-D FG, and has good
characteristics suitable for multilevel operation. HC-FG NAND
can reduce the cell size more than GAA type 3-D structure,
as shown in Table I and Fig. 8. Furthermore, we have demonstrated a low-cost LST structure that can be formed using a
self-aligned process. In combination with twisted-layout LST
structure, reduction in chip size of the HC-FG NAND can
be achieved even when the number of stacked cells is large.
HC-FG NAND is a more realistic technology for low-cost and
ultrahigh density NAND memory.
ACKNOWLEDGMENT

using normally-on SSL [5]. The overlap is dependent on the

annealing temperature and time. Therefore, when the thermal
budget increases, it is necessary to extend the length of the
LST gate in accordance with the amount of overlap region.
In addition, the number of the LST gate increases with
increasing the number of the stacked BLs. Twisted layout
shown in Fig. 1(a) can, however, keep memory string length
constant regardless of the LST string length.
Fig. 7(c) shows the Id Vg characteristics of stacked BLs
with LST structure, as shown in Fig. 7(a); two LSTs (Gate 1
and Gate 2) and one normal transistor without normally-on
region (Gate 3). This figure shows that the amount of current
depends on the number of BLs selected by LST. As described
above, using a stair-like shape, impurity regions can be formed
in the target position in a self-aligned manner. These results
show that the LST structure can be formed by an easy process
at low cost.
V. C ONCLUSION
We have successfully demonstrated a stacked FG Flash
memory array employing HC-FG technology. HC-FG NAND

The authors would like to thank L. Zhang, T. Muraoka,

M. Shingu, and M. Kiyotoshi for their support.
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