library IEEE;

use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;

entity division is
generic(SIZE: INTEGER := ;
port(reset: in STD_LOGIC;
en: in STD_LOGIC;
clk: in STD_LOGIC;

num: in STD_LOGIC_VECTOR((SIZE - 1) downto 0);

den: in STD_LOGIC_VECTOR((SIZE - 1) downto 0);
res: out STD_LOGIC_VECTOR((SIZE - 1) downto 0);
rm: out STD_LOGIC_VECTOR((SIZE - 1) downto 0)
);
end division;

architecture behav of division is

signal buf: STD_LOGIC_VECTOR((2 * SIZE - 1) downto 0);
signal dbuf: STD_LOGIC_VECTOR((SIZE - 1) downto 0);
signal sm: INTEGER range 0 to SIZE;

alias buf1 is buf((2 * SIZE - 1) downto SIZE);

alias buf2 is buf((SIZE - 1) downto 0);
begin
p_001: process(reset, en, clk)
begin
if reset = '1' then
res <= (others => '0');
rm <= (others => '0');
sm <= 0;
elsif rising_edge(clk) then
if en = '1' then
case sm is
when 0 =>
buf1 <= (others => '0');
buf2 <= num;
dbuf <= den;
res <= buf2;
rm <= buf1;
sm <= sm + 1;
when others =>
if buf((2 * SIZE - 2) downto (SIZE - 1)) >= dbuf then
buf1 <= '0' & (buf((2 * SIZE - 3) downto (SIZE - 1)) - dbuf((SIZE - 2) downto 0));
buf2 <= buf2((SIZE - 2) downto 0) & '1';
else
buf <= buf((2 * SIZE - 2) downto 0) & '0';
end if;
if sm /= SIZE then
sm <= sm + 1;
else
sm <= 0;
end if;
end case;
end if;
end if;
end process;
end behav;

2. library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are

-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity div_binary is
Port (

ina : in std_logic_vector (15 downto 0);-- range 0 to 99;

inb: in std_logic_vector (15 downto 0);-- range 1 to 9;
quot: out std_logic_vector (15 downto 0);-- range 0 to 99;
rest : out std_logic_vector (15 downto 0));-- range 0 to 99 );

end div_binary;

architecture Behavioral of div_binary is

signal a,b: integer range 0 to 65535;

begin

a <= CONV_INTEGER(ina);
b <= CONV_INTEGER(inb);
process (a,b)

variable temp1,temp2: integer range 0 to 65535;

variable y : std_logic_vector (15 downto 0);
begin
temp1:=a;
temp2:=b;
for i in 15 downto 0 loop
if (temp1>temp2 * 2**i) then
y(i):= '1';
temp1:= temp1- temp2 * 2**i;
else y(i):= '0';
end if;
end loop;
rest <= CONV_STD_LOGIC_VECTOR (temp1 ,16);
quot<= y;
--quot<= conv_integer (y);
end process;

end Behavioral;

3. library ieee;
use ieee.std_logic_1164.all;
USE ieee.std_logic_signed.ALL;
entity nosrt is
port (in1, in2 : in std_logic_vector(3 downto 0);
clk : in std_logic ;
remainder : out std_logic_vector( 4 downto 0);
qotient : out std_logic_vector ( 3 downto 0));

end nosrt;
architecture div of nosrt is
begin
process(clk)

variable a,b : std_logic_vector( 4 downto 0);

variable c,d : std_logic_vector( 3 downto 0);
begin
if (clk'event and clk ='1') then
a :=  "0" & in1 ;
d := "0000";
c := "0000";
b:=  "0" & in2 ;
for i in  3 downto 0 loop
a := a( 3 downto 0) & "0";
case a( 4 downto 2) is
when "000"|"111" |"001" =>
 c:= c ( 2 downto 0) & "0";
  d:= d ( 2 downto 0) & "0";
when "010" |"011" =>
 c := c( 2 downto 0) & "1";
   d := d( 2 downto 0) & "0";
    a := a +(not(b)+ "00001");
  when "100"|"101" |"110" =>
c :=  c ( 2 downto 0) & "0";
 d:= d ( 2 downto 0) & "1";
 a := a + b ;
    when others =>
 a := "00000";
 end case ;
 end loop ;
 c := c + (not(d)+"0001") ;
 
 if a(4) = '1' then
 a := a + b ;
 c := c +(not("0001")+ "0001");
  end if;
 remainder <= a ;
 qotient <=  c ;
 end if ;
  end process;
 end div;

4.
signal dividend, divisor, quotient, remainder:
> > > * * * * * * * * * * * * * * * * * *unsigned(3 downto 0);
> > > * .....
> > > * process (dividend, divisor)
> > > * * variable v: unsigned(3 downto 0);
> > > * * variable done: boolean;
> > > * begin
> > > * * v := dividend;
> > > * * done := false;
> > > * * for i in 0 to 15 loop
> > > * * * if not done then
> > > * * * * if v < divisor then
> > > * * * * * quotient <= to_unsigned(i, 4);
> > > * * * * * remainder <= v;
> > > * * * * * done := true;
> > > * * * * else
> > > * * * * * v := v - divisor;
> > > * * * * end if;
> > > * * * end if;
> > > * * end loop;
> > > * end process;
http://www.scribd.com/doc/260030/DSD-Lab-Programs-Using-VHDL-Adders-
Subtractors-Comparator-Decoder-Parity-Multiplexer-FlipFlops-Counters

5. library ieee;
use ieee.std_logic_1164.all;

entity comparator is
 
  port (
    A : in  std_logic_vector(1 downto 0);
    B : in  std_logic_vector(1 downto 0);
    L_in : in std_logic;
    G_in : in std_logic;
    E_in : in std_logic;
    L : out std_logic;
    G : out  std_logic;
    E : out  std_logic);

end comparator;

architecture behav of comparator is

begin  -- behav
  process (A, B, L_in, G_in, E_in)
  begin  -- process
    if ( (A = B) and E_in = '1') then
      E <= '1';
    else
      E <= '0';
    end if;
    if (A(1)= '1' and B(1) = '0')
      or ( (A(1) = B(1)) and (A(0)='1' and B(0)= '0'))
      or ((A = B) and G_in = '1') then
      G <= '1';
    else
      G <= '0';
    end if;
    if (A(1)='0' and B(1) ='1')
      or ((A(1) = B(1)) and A(0)='0' and B(0)= '1')
      or ((A = B) and L_in = '1') then
      L <= '1';
    else
      L <= '0'; 
    end if;
 
  end process;
 
end behav;

library ieee;
use ieee.std_logic_1164.all;

entity comp_8bit is
port (
    A : in  std_logic_vector(7 downto 0);
    B : in  std_logic_vector(7 downto 0);
    L : out std_logic;
    G : out  std_logic;
    E : out  std_logic);
 
end comp_8bit;

architecture struct of comp_8bit is

component comparator
  port (
    A : in std_logic_vector(1 downto 0);
    B : in std_logic_vector(1 downto 0);
    L_in : in std_logic;
    G_in : in std_logic;
    E_in : in std_logic;
    L : out std_logic;
    G : out  std_logic;
    E : out  std_logic);
end component;
signal E_0, E_1, E_2, L_0, L_1, L_2, G_0, G_1, G_2 : std_logic;
begin  -- struct
  u1 : comparator port map (
    A => A(1 downto 0),
    B => B(1 downto 0),
    L_in => '0',
    G_in => '0',
    E_in => '1',
    G    => G_0,
    L    => L_0,
    E    => E_0);
  
  u2 : comparator port map (
    A => A(3 downto 2),
    B => B(3 downto 2),
    G_in => G_0,
    L_in => L_0,
    E_in => E_0,
    G    => G_1,
    L    => L_1,
    E    => E_1);
  u3 : comparator port map (
    A => A(5 downto 4),
    B => B(5 downto 4),
    G_in => G_1,
    L_in => L_1,
    E_in => E_1,
    L    => L_2,
    E    => E_2);
  u4 : comparator port map (
    A => A(7 downto 6),
    B => B(7 downto 6),
    G_in => G_2,
    L_in => L_2,
    E_in => E_2,
    L    => L,
    G    => G,
    E    => E);

end struct;