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Caso 1-Pic16f1705 PDF
Caso 1-Pic16f1705 PDF
Core Features
Digital Peripherals
Memory
8 Kwords Flash Program Memory
1024 Bytes Data SRAM Memory
Direct, Indirect and Relative Addressing modes
Operating Characteristics
Operating Voltage Range:
- 1.8V to 3.6V (PIC16LF1705/9)
- 2.3V to 5.5V (PIC16F1705/9)
Temperature Range:
- Industrial: -40C to 85C
- Extended: -40C to 125C
DS40001729B-page 1
PIC16(L)F1705/9
Zero-Cross Detector (ZCD):
- Detect when AC signal on pin crosses
ground
8-Bit Digital-to-Analog Converter (DAC):
- Output available externally
- Internal connections to comparators, op
amps, Fixed Voltage Reference (FVR) and
ADC
Internal Voltage Reference module
Programming/Debug Features
In-Circuit Debug Integrated On-Chip
Emulation Header for Advanced Debug:
- Provides trace, background debug and up to
32 hardware break points
In-Circuit Serial Programming (ICSP) via Two
Pins
Clocking Structure
16 MHz Internal Oscillator Block:
- 1% at calibration
- Selectable frequency range from 0 to 32 MHz
31 kHz Low-Power Internal Oscillator
External Oscillator Block with:
- Three crystal/resonator modes up to 20 MHz
- Two external clock modes up to 20 MHz
Fail-Safe Clock Monitor
Two-Speed Oscillator Start-up
Oscillator Start-up Timer (OST)
Program Memory
Flash (words)
Data SRAM
(bytes)
I/Os(2)
8-bit DAC
High-Speed/
Comparators
Op Amp
Zero Cross
Timers
(8/16-bit)
CCP
PWM
COG
EUSART
MSSP (I2C/SPI)
CLC
PPS
Debug(1)
XLP
PIC16(L)F1703
(3)
2048
256
12
2/1
I/E
PIC16(L)F1704
(1)
4096
512
12
4/1
I/E
PIC16(L)F1705
(2)
8192
1024
12
4/1
I/E
PIC16(L)F1707
(3)
2048
256
18
12
2/1
I/E
PIC16(L)F1708
(1)
4096
512
18
12
4/1
I/E
PIC16(L)F1709
(2)
8192
1024
18
12
4/1
I/E
Device
Note 1:
2:
Debugging Methods: (I) Integrated on Chip; (H) using Debug Header; E using Emulation Header.
One pin is input-only.
Note:
For other small form-factor package availability and marking information, please visit
http://www.microchip.com/packaging or contact your local sales office.
DS40001729B-page 2
PIC16(L)F1705/9
Pin Diagrams
VDD
RA5
RA4
VPP/MCLR/RA3
RC5
RC4
RC3
14
13
12
11
10
9
8
VSS
RA0/ICSPDAT
RA1/ICSPCLK
RA2
RC0
RC1
RC2
16-PIN QFN
16
15
14
13
VDD
NC
FIGURE 2:
1
2
3
4
5
6
7
PIC16(L)F1705
NC
VSS
FIGURE 1:
1
12 RA0/ICSPDAT
2
11 RA1/ICSPCLK
3 PIC16(L)F1705 10 RA2
9 RC0
4
RC4
RC3
RC2
RC1
5
6
7
8
RA5
RA4
RA3/MCLR/VPP
RC5
DS40001729B-page 3
PIC16(L)F1705/9
20-PIN PDIP, SOIC, SSOP
VDD
20
VSS
RA5
19
ICSPDAT/RA0
RA4
18
ICSPCLK/RA1
VPP/MCLR/RA3
17
RA2
RC5
16
RC0
15
RC1
14
RC2
13
RB4
12
RB5
10
11
RB6
RC4
RC3
RC6
RC7
RB7
6
7
8
20-PIN QFN
20
19
18
17
16
RA4
RA5
VDD
VSS
RA0/ICSPDAT
FIGURE 4:
PIC16(L)F1709
FIGURE 3:
1
15 RA1/ICSPCLK
2
14 RA2
3 PIC16(L)F1709 13 RC0
4
12 RC1
5
11 RC2
RC7
RB7
RB6
RB5
RB4
6
7
8
9
10
VPP/MCLR/RA3
RC5
RC4
RC3
RC6
DS40001729B-page 4
Comparator
Op Amp
DAC
Zero Cross
Timers
CCP
PWM
COG
MSSP
EUSART
CLC
Interrupt
Pull-up
13
12
AN0
VREF-
C1IN+
DAC1OUT1
IOC
ICSPDAT
RA1
12
11
AN1
VREF+
C1IN0C2IN0-
IOC
ICSPCLK
RA2
11
10
AN2
DAC1OUT2
ZCD
T0CKI(1)
COGIN(1)
INT(1)
IOC
RA3
IOC
MCLR
VPP
RA4
AN3
T1G(1)
SOSCO
IOC
CLKOUT
OSC2
RA5
T1CKI(1)
SOSCI
CLCIN3(1)
IOC
CLKIN
OSC1
RC0
10
AN4
C2IN+
OPA1IN+
SCK(1)
SCL(3)
IOC
RC1
AN5
C1IN1C2IN1-
OPA1IN-
SDI(1)
SDA(3)
CLCIN2(1)
IOC
RC2
AN6
C1IN2C2IN2-
OPA1OUT
IOC
RC3
AN7
C1IN3C2IN3-
OPA2OUT
CCP2(1)
SS(1)
CLCIN0(1)
IOC
RC4
OPA2IN-
CK(1)
CLCIN1(1)
IOC
RX(1,3)
IOC
VDD
Basic
ADC
RA0
Reference
16-Pin QFN
14-Pin PDIP/SOIC/TSSOP
TABLE 1:
I/O(2)
OPA2IN+
VDD
16
VSS
14
13
VSS
C1OUT
CPP1
PWM3OUT
COGA
SDA(3)
CK
CLC1OUT
C2OUT
CPP2
PWM4OUT
COGB
SCL(3)
DT(3)
CLC2OUT
COGC
SDO
TX
CLC3OUT
COGD
SCK
OUT(2)
Note
1:
2:
3:
Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 12-1.
All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 12-3.
These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
PIC16(L)F1705/9
DS40001729B-page 5
RC5
CCP1(1)
20-Pin QFN
ADC
Comparator
Op Amp
DAC
Zero Cross
Timers
CCP
PWM
COG
MSSP
EUSART
CLC
Interrupt
Pull-up
19
16
AN0
VREF-
C1IN+
DAC1OUT1
IOC
ICSPDAT
RA1
18
15
AN1
VREF+
C1IN0C2IN0-
IOC
ICSPCLK
RA2
17
14
AN2
DAC1OUT2
ZCD
T0CKI(1)
COGIN(1)
INT(1)
IOC
RA3
IOC
MCLR
VPP
RA4
20
AN3
T1G(1)
SOSCO
IOC
CLKOUT
OSC2
RA5
19
T1CKI
SOSCI
CLCIN3(1)
IOC
CLKIN
OSC1
RB4
13
10
AN10
OPA1IN-
SDI(1)
SDA(3)
IOC
RB5
12
AN11
OPA1IN+
RX(1,3)
IOC
RB6
11
IOC
RB7
10
CK(1)
IOC
RC0
16
IOC
IOC
SCK(1)
SCL(3)
C2IN+
13
AN4
Basic
20-Pin PDIP/
SOIC/SSOP
RA0
Reference
I/O(2)
RC1
15
12
AN5
C1IN1C2IN1-
CLCIN2(1)
RC2
14
11
AN6
C1IN2C2IN2-
OPA1OUT
IOC
RC3
AN7
C1IN3C2IN3-
OPA2OUT
CCP2(1)
CLCIN0(1)
IOC
RC4
CLCIN1(1)
IOC
IOC
(1)
RC5
RC6
AN8
OPA2IN-
SS(1)
IOC
RC7
AN9
OPA2IN+
IOC
VDD
18
VDD
VSS
20
17
VSS
OUT
Note
(2)
1:
2:
3:
CCP1
(3)
C1OUT
CPP1
PWM3OUT
COGA
SDA
CK
CLC1OUT
C2OUT
CPP2
PWM4OUT
COGB
SCL(3)
DT(3)
CLC2OUT
COGC
SDO
TX
CLC3OUT
COGD
SCK
Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 12-2.
All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 12-3.
These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
PIC16(L)F1705/9
DS40001729B-page 6
TABLE 2:
PIC16(L)F1705/9
Table of Contents
1.0 Device Overview ............................................................................................................................................................................. 9
2.0 Enhanced Mid-Range CPU........................................................................................................................................................... 17
3.0 Memory Organization.................................................................................................................................................................... 19
4.0 Device Configuration..................................................................................................................................................................... 47
5.0 Resets ........................................................................................................................................................................................... 53
6.0 Oscillator Module (with Fail-Safe Clock Monitor) .......................................................................................................................... 61
7.0 PIC16(L)F1705/9 Interrupts .......................................................................................................................................................... 79
8.0 Power-Down Mode (Sleep) ........................................................................................................................................................... 92
9.0 Watchdog Timer (WDT) ................................................................................................................................................................ 96
10.0 Flash Program Memory Control ................................................................................................................................................ 101
11.0 I/O Ports .................................................................................................................................................................................... 118
12.0 Peripheral Pin Select (PPS) Module ......................................................................................................................................... 137
13.0 Interrupt-on-Change.................................................................................................................................................................. 144
14.0 Fixed Voltage Reference (FVR) ................................................................................................................................................ 151
15.0 Temperature Indicator Module .................................................................................................................................................. 154
16.0 Comparator Module .................................................................................................................................................................. 156
17.0 Pulse-Width Modulation (PWM) ................................................................................................................................................ 165
18.0 Complementary Output Generator (COG) Module ................................................................................................................... 171
19.0 Configurable Logic Cell (CLC) .................................................................................................................................................. 203
20.0 Analog-to-Digital Converter (ADC) Module ............................................................................................................................... 218
21.0 Operational Amplifier (OPA) Modules ....................................................................................................................................... 232
22.0 8-Bit Digital-to-Analog Converter (DAC1) Module..................................................................................................................... 235
23.0 Zero-Cross Detection (ZCD) Module ........................................................................................................................................ 239
24.0 Timer0 Module .......................................................................................................................................................................... 243
25.0 Timer1 Module with Gate Control ............................................................................................................................................. 246
26.0 Timer2/4/6 Module .................................................................................................................................................................... 257
27.0 Capture/Compare/PWM Modules ............................................................................................................................................. 262
28.0 Master Synchronous Serial Port (MSSP) Module ..................................................................................................................... 270
29.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ................................................................ 323
30.0 In-Circuit Serial Programming (ICSP) ................................................................................................................................ 354
31.0 Instruction Set Summary ........................................................................................................................................................... 356
32.0 Electrical Specifications ............................................................................................................................................................ 370
33.0 DC and AC Characteristics Graphs and Charts ........................................................................................................................ 403
34.0 Development Support ............................................................................................................................................................... 425
35.0 Packaging Information .............................................................................................................................................................. 429
Appendix A: Data Sheet Revision History......................................................................................................................................... 449
The Microchip Web Site .................................................................................................................................................................... 450
Customer Change Notification Service .............................................................................................................................................. 450
Customer Support ............................................................................................................................................................................. 450
Product Identification System ........................................................................................................................................................... 451
DS40001729B-page 7
PIC16(L)F1705/9
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com. We welcome your feedback.
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
Microchips Worldwide Web site; http://www.microchip.com
Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
DS40001729B-page 8
PIC16(L)F1705/9
1.0
DEVICE OVERVIEW
Peripheral
PIC16(L)F1709
DEVICE PERIPHERAL
SUMMARY
PIC16(L)F1705
TABLE 1-1:
Temperature Indicator
CCP2
C1
C2
CLC1
CLC2
CLC3
Comparators
MSSP
Op Amp 1
Op Amp 2
PWM3
PWM4
Timer0
Timer1
Timer2
Timers
DS40001729B-page 9
PIC16(L)F1705/9
FIGURE 1-1:
Program
Flash Memory
RAM
PORTA
PORTB(1)
CLKOUT
Timing
Generation
HFINTOSC/
LFINTOSC
Oscillator
CLKIN
PORTC
CPU
Figure 2-1
MCLR
ZCD
Op Amps
PWM
Timer0
Timer1
Timer2
MSSP
Comparators
COG
Temp.
Indicator
Note
1:
2:
DS40001729B-page 10
ADC
10-Bit
FVR
DAC
CCPs
EUSART
CLCs
PIC16(L)F1709 only.
See applicable chapters for more information on peripherals.
PIC16(L)F1705/9
TABLE 1-2:
Function
Input
Type
Output
Type
RA0
TTL/ST
CMOS
AN0
AN
RA0/AN0/VREF-/C1IN+/
DAC1OUT/ICSPDAT
VREF-
AN
C1IN+
AN
DAC1OUT
AN
ICSPDAT
ST
CMOS
RA1
TTL/ST
CMOS
AN1
AN
RA1/AN1/VREF+/C1IN0-/C2IN0-/
ICSPCLK
VREF+
AN
C1IN0-
AN
C2IN0-
AN
ICSPCLK
ST
RA2
TTL/ST
CMOS
AN2
AN
DAC1OUT2
AN
ZCD
AN
RA2/AN2/DAC1OUT2/ZCD/
T0CKI(1)/COGIN(1)/INT(1)
T0CKI
TTL/ST
COGIN
TTL/ST
CMOS
INT
TTL/ST
RA3
TTL/ST
CMOS
RA3/MCLR/VPP
MCLR
ST
VPP
HV
Programming voltage.
RA4
TTL/ST
CMOS
AN3
AN
T1G
TTL/ST
SOSCO
XTAL
XTAL
RA4/AN3/T1G(1)/SOSCO/
OSC2/CLKOUT
RA5/T1CKI(1)/SOSCI/
CLCIN3(1)/OSC1/CLKIN
Description
OSC2
XTAL
CLKOUT
CMOS
FOSC/4 output.
RA5
TTL/ST
CMOS
T1CKI
TTL/ST
SOSCI
XTAL
XTAL
CLCIN3
TTL/ST
OSC1
XTAL
CLKIN
ST
ST
OD = Open-Drain
Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.
See Register 12-1.
All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the
PPS output selection registers. See Register 12-3.
These I2C functions are bidirectional. The output pin selections must be the same as the input pin
selections.
DS40001729B-page 11
PIC16(L)F1705/9
TABLE 1-2:
Function
Input
Type
Output
Type
RC0
TTL/ST
CMOS
RC0/AN4/C2IN+/OPA1IN+/
SCK(1)/SCL(3)
RC1/AN5/C1IN1-/C2IN1-/
OPA1IN-/SDI(1)/SDA(3)/
CLCIN2(1)
AN4
AN
C2IN+
AN
OPA1IN+
AN
SCK
TTL/ST
SPI clock.
SCL
I C
I2C clock.
RC1
TTL/ST
CMOS
AN5
AN
C1IN1-
AN
C2IN1-
AN
OPA1IN-
AN
SDI
CMOS
SDA
I2C
CLCIN2
TTL/ST
RC2
TTL/ST
CMOS
RC2/AN6/C1IN2-/C2IN2-/
OPA1OUT
RC3/AN7/C1IN3-/C2IN3-/
OPA2OUT/CCP2(1)/SS(1)/
CLCIN0(1)
Description
AN6
AN
C1IN2-
AN
C2IN2-
AN
OPA1OUT
AN
RC3
TTL/ST
CMOS
AN7
AN
C1IN3-
AN
C2IN3-
AN
OPA2OUT
AN
CCP2
TTL/ST
Capture/Compare/PWM2.
SS
TTL/ST
CLCIN0
TTL/ST
RC4/OPA2IN-/CK(1)/CLCIN1(1)
RC4
TTL/ST
CMOS
OPA2IN-
AN
CK
TTL/ST
CLCIN1
TTLST
RC5
TTL/ST
CMOS
OPA2IN+
AN
CCP1
TTL/ST
Capture/Compare/PWM1.
RX
TTL/ST
RC5/OPA2IN+/CCP1(1)/RX(1)
ST
OD = Open-Drain
Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.
See Register 12-1.
All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the
PPS output selection registers. See Register 12-3.
These I2C functions are bidirectional. The output pin selections must be the same as the input pin
selections.
DS40001729B-page 12
PIC16(L)F1705/9
TABLE 1-2:
Input
Type
Output
Type
VDD
VDD
Power
Positive supply.
VSS
VSS
Power
Ground reference.
C1OUT
CMOS
Comparator output.
Name
OUT(2)
Description
C2OUT
CMOS
Comparator output.
CCP1
CMOS
Capture/Compare/PWM1 output.
CCP2
CMOS
Capture/Compare/PWM2 output.
PWM3OUT
CMOS
PWM3 output.
PWM4OUT
CMOS
PWM4 output.
COGA
CMOS
COGB
CMOS
COGC
CMOS
COGD
CMOS
SDA(3)
OD
SDO
CMOS
SCK
CMOS
SCL(3)
OD
TX/CK
CMOS
DT
CMOS
CLC1OUT
CMOS
CLC2OUT
CMOS
CLC3OUT
CMOS
I
Note 1:
2:
3:
ST
I2C
OD = Open-Drain
Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.
See Register 12-1.
All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the
PPS output selection registers. See Register 12-3.
These I2C functions are bidirectional. The output pin selections must be the same as the input pin
selections.
DS40001729B-page 13
PIC16(L)F1705/9
TABLE 1-3:
RA0/AN0/VREF-/C1IN+/
DAC1OUT/ICSPDAT
RA1/AN1/VREF+/C1IN0-/C2IN0-/
ICSPCLK
RA2/AN2/DAC1OUT2/ZCD/
T0CKI(1)/COGIN(1)/INT(1)
RA3/MCLR/VPP
Function
Input
Type
Output
Type
RA0
TTL/ST
CMOS
AN0
AN
VREF-
AN
C1IN+
AN
Description
DAC1OUT
AN
ICSPDAT
ST
CMOS
RA1
TTL/ST
CMOS
AN1
AN
VREF+
AN
C1IN0-
AN
C2IN0-
AN
ICSPCLK
ST
RA2
TTL/ST
CMOS
AN2
AN
DAC1OUT
2
AN
ZCD
AN
T0CKI
ST
COGIN
ST
CMOS
INT
ST
RA3
TTL/ST
CMOS
External interrupt.
MCLR
ST
VPP
HV
Programming voltage.
RA4/AN3/T1G(1)/SOSCO/
RA4
TTL/ST
CMOS
OSC2/CLKOUT
AN3
AN
RA5/T1CKI/SOSCI/
CLCIN3(1)/OSC1/CLKIN
T1G
ST
SOSCO
XTAL
XTAL
OSC2
XTAL
CLKOUT
CMOS
FOSC/4 output.
RA5
TTL/ST
CMOS
T1CKI
ST
SOSCI
XTAL
XTAL
CLCIN3
ST
OSC1
XTAL
CLKIN
ST
2:
3:
HV = High Voltage
XTAL=Crystal levels
Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See
Register 12-2.
All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the
PPS output selection registers. See Register 12-3.
These I2C functions are bidirectional. The output pin selections must be the same as the input pin
selections.
DS40001729B-page 14
PIC16(L)F1705/9
TABLE 1-3:
RB4/AN10/OPA1IN-/SCK(1)/
SDA(3)
RB5/AN11/OPA1IN+/RX(1)
RB6/SDI(1)/SCL(3)
Function
Input
Type
Output
Type
RB4
TTL/ST
CMOS
AN10
AN
OPA1IN-
AN
SCK
ST
CMOS
SDA
I2C
OD
Description
General purpose I/O.
SPI clock.
I2C data input/output.
RB5
TTL/ST
CMOS
AN11
AN
OPA1IN+
AN
RX
ST
RB6
TTL/ST
CMOS
SDI
CMOS
SCL
2C
OD
I2C clock.
TTL/ST
CMOS
RB7/CK(1)
RB7
CK
ST
CMOS
RC0/AN4/C2IN+
RC0
TTL/ST
CMOS
RC1/AN5/C1IN1-/C2IN1-/
CLCIN2(1)
RC2/AN6/C1IN2-/C2IN2-/
OPA1OUT
RC3/AN7/C1IN3-/C2IN3-/
OPA2OUT/CCP2(1)/CLCIN0(1)
RC4/CLCIN1(1)
AN4
AN
C2IN+
AN
RC1
TTL/ST
CMOS
AN5
AN
C1IN1-
AN
C2IN1-
AN
CLCIN2
ST
RC2
TTL/ST
CMOS
AN6
AN
AN
C2IN2-
AN
OPA1OUT
AN
RC3
TTL/ST
CMOS
AN7
AN
C1IN3-
AN
C2IN3-
AN
OPA2OUT
AN
CCP2
ST
CMOS
CLCIN0
ST
RC4
TTL/ST
CMOS
CLCIN1
ST
3:
Capture/Compare/PWM2.
Configurable Logic Cell source input.
General purpose I/O.
Configurable Logic Cell source input.
2:
C1IN2-
HV = High Voltage
XTAL=Crystal levels
Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See
Register 12-2.
All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the
PPS output selection registers. See Register 12-3.
These I2C functions are bidirectional. The output pin selections must be the same as the input pin
selections.
DS40001729B-page 15
PIC16(L)F1705/9
TABLE 1-3:
RC5/CCP1(1)
RC6/AN8/OPA2IN-/SS(1)
RC7/AN9/OPA2IN+
Function
Input
Type
Output
Type
RC5
TTL/ST
CMOS
CCP1
ST
CMOS
Capture/Compare/PWM1.
RC6
TTL/ST
CMOS
AN8
AN
OPA2IN-
AN
Description
General purpose I/O.
SS
ST
RC7
TTL/ST
CMOS
AN9
AN
OPA2IN+
AN
VDD
VDD
Power
Positive supply.
VSS
VSS
Power
Ground reference.
C1OUT
CMOS
Comparator output.
C2OUT
CMOS
Comparator output.
CCP1
CMOS
Capture/Compare/PWM1 output.
CCP2
CMOS
Capture/Compare/PWM2 output.
PWM3OUT
CMOS
PWM3 output.
PWM4OUT
CMOS
PWM4 output.
COGA
CMOS
COGB
CMOS
COGC
CMOS
COGD
CMOS
(3)
OD
CMOS
OUT(2)
SDA
SDO
SCK
CMOS
SCL(3)
I2C
OD
TX/CK
CMOS
3:
DT
CMOS
CMOS
CLC2OUT
CMOS
CLC3OUT
CMOS
2:
CLC1OUT
HV = High Voltage
XTAL=Crystal levels
Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See
Register 12-2.
All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the
PPS output selection registers. See Register 12-3.
These I2C functions are bidirectional. The output pin selections must be the same as the input pin
selections.
DS40001729B-page 16
PIC16(L)F1705/9
2.0
FIGURE 2-1:
15
Configuration
15
MUX
Flash
Program
Memory
Program
Bus
16-Level
8 Level Stack
Stack
(13-bit)
(15-bit)
14
Instruction
Instruction Reg
reg
Data Bus
Program Counter
RAM
Program Memory
Read (PMR)
12
RAM Addr
Addr MUX
Direct Addr 7
5
Indirect
Addr
12
12
BSR
FSR Reg
reg
15
FSR0reg
Reg
FSR
FSR1
Reg
FSR reg
15
STATUS Reg
reg
STATUS
8
3
Power-up
Timer
OSC1/CLKIN
OSC2/CLKOUT
Instruction
Decodeand
&
Decode
Control
Timing
Generation
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
MUX
ALU
8
W reg
Internal
Oscillator
Block
VDD
VSS
DS40001729B-page 17
PIC16(L)F1705/9
2.1
2.2
2.3
2.4
Instruction Set
DS40001729B-page 18
PIC16(L)F1705/9
3.0
MEMORY ORGANIZATION
3.1
3.2
High-Endurance Flash
TABLE 3-1:
Device
High-Endurance Flash
Memory Address Range(1)
8,192
1FFFh
1F80h-1FFFh
PIC16(L)F1705/9
Note 1:
High-endurance Flash applies to the low byte of each address in the range.
DS40001729B-page 19
PIC16(L)F1705/9
FIGURE 3-1:
CALL, CALLW
RETURN, RETLW
Interrupt, RETFIE
15
3.2.1.1
RETLW Instruction
Stack Level 0
Stack Level 1
Stack Level 15
EXAMPLE 3-1:
Reset Vector
0000h
Interrupt Vector
0004h
0005h
Page 0
07FFh
0800h
Page 1
On-chip
Program
Memory
3.2.1
0FFFh
1000h
Page 2
17FFh
1800h
Page 3
Rollover to Page 0
1FFFh
2000h
constants
BRW
RETLW
RETLW
RETLW
RETLW
DATA0
DATA1
DATA2
DATA3
RETLW INSTRUCTION
;Add Index in W to
;program counter to
;select data
;Index0 data
;Index1 data
my_function
; LOTS OF CODE
MOVLW
DATA_INDEX
call constants
; THE CONSTANT IS IN W
3.2.1.2
Rollover to Page 3
DS40001729B-page 20
PIC16(L)F1705/9
EXAMPLE 3-2:
ACCESSING PROGRAM
MEMORY VIA FSR
constants
RETLW DATA0
;Index0 data
RETLW DATA1
;Index1 data
RETLW DATA2
RETLW DATA3
my_function
; LOTS OF CODE
MOVLW
LOW constants
MOVWF
FSR1L
MOVLW
HIGH constants
MOVWF
FSR1H
MOVIW
0[FSR1]
;THE PROGRAM MEMORY IS IN W
3.3
3.3.1
TABLE 3-2:
12 core registers
20 Special Function Registers (SFR)
Up to 80 bytes of General Purpose RAM (GPR)
16 bytes of common RAM
CORE REGISTERS
3.3.1.1
CORE REGISTERS
Addresses
BANKx
x00h or x80h
x01h or x81h
x02h or x82h
x03h or x83h
x04h or x84h
x05h or x85h
x06h or x86h
x07h or x87h
x08h or x88h
x09h or x89h
x0Ah or x8Ah
x0Bh or x8Bh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
STATUS Register
DS40001729B-page 21
PIC16(L)F1705/9
3.4
REGISTER 3-1:
U-0
U-0
R-1/q
TO
R-1/q
PD
R/W-0/u
R/W-0/u
(1)
DC
R/W-0/u
C(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0
Note 1:
For Borrow, the polarity is reversed. A subtraction is executed by adding the twos complement of the
second operand.
DS40001729B-page 22
PIC16(L)F1705/9
3.4.1
3.4.2
FIGURE 3-2:
0Bh
0Ch
Core Registers
(12 bytes)
3.4.3
Memory Region
00h
3.4.2.1
BANKED MEMORY
PARTITIONING
COMMON RAM
6Fh
70h
Common RAM
(16 bytes)
7Fh
3.4.4
DS40001729B-page 23
BANK 0
000h
BANK 1
080h
Core Registers
(Table 3-2)
BANK 2
100h
Core Registers
(Table 3-2)
BANK 3
180h
Core Registers
(Table 3-2)
BANK 4
200h
Core Registers
(Table 3-2)
BANK 5
280h
Core Registers
(Table 3-2)
BANK 6
300h
Core Registers
(Table 3-2)
BANK 7
380h
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
00Bh
00Ch
00Dh
00Eh
00Fh
010h
011h
012h
013h
014h
015h
016h
PORTA
PORTC
PIR1
PIR2
PIR3
TMR0
TMR1L
08Bh
08Ch
08Dh
08Eh
08Fh
090h
091h
092h
093h
094h
095h
096h
TRISA
TRISC
PIE1
PIE2
PIE3
OPTION_REG
PCON
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
LATA
LATC
CM1CON0
CM1CON1
CM2CON0
CM2CON1
CMOUT
BORCON
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
ANSELA
ANSELC
PMADRL
PMADRH
PMDATL
PMDATH
PMCON1
PMCON2
20Bh
20Ch
20Dh
20Eh
20Fh
210h
211h
212h
213h
214h
215h
216h
WPUA
WPUC
SSP1BUF
SSP1ADD
SSP1MSK
SSP1STAT
SSP1CON
SSP1CON2
28Bh
28Ch
28Dh
28Eh
28Fh
290h
291h
292h
293h
294h
295h
296h
ODCONA
ODCONC
CCPR1L
CCPR1H
CCP1CON
30Bh
30Ch
30Dh
30Eh
30Fh
310h
311h
312h
313h
314h
315h
316h
SLRCONA
SLRCONC
38Bh
38Ch
38Dh
38Eh
38Fh
390h
391h
392h
393h
394h
395h
396h
INLVLA
INLVLC
IOCAP
IOCAN
IOCAF
017h
018h
019h
01Ah
01Bh
01Ch
01Dh
01Eh
TMR1H
T1CON
T1GCON
TMR2
PR2
T2CON
097h
098h
099h
09Ah
09Bh
09Ch
09Dh
09Eh
WDTCON
OSCTUNE
OSCCON
OSCSTAT
ADRESL
ADRESH
ADCON0
ADCON1
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
FVRCON
DAC1CON0
DAC1CON1
ZCD1CON
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
VREGCON(1)
RC1REG
TX1REG
SP1BRGL
SP1BRGH
RC1STA
TX1STA
217h
218h
219h
21Ah
21Bh
21Ch
21Dh
21Eh
SSP1CON3
297h
298h
299h
29Ah
29Bh
29Ch
29Dh
29Eh
CCPR2L
CCPR2H
CCP2CON
CCPTMRS
317h
318h
319h
31Ah
31Bh
31Ch
31Dh
31Eh
397h
398h
399h
39Ah
39Bh
39Ch
39Dh
39Eh
IOCCP
IOCCN
IOCCF
01Fh
020h
09Fh
0A0h
ADCON2
11Fh
120h
19Fh
1A0h
BAUD1CON
21Fh
220h
29Fh
2A0h
31Fh
320h
39Fh
3A0h
General
Purpose
Register
80 Bytes
06Fh
070h
0EFh
0F0h
Common RAM
70h 7Fh
07Fh
Note
16Fh
170h
Accesses
70h 7Fh
0FFh
Legend:
1:
1EFh
1F0h
Accesses
70h 7Fh
17Fh
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
26Fh
270h
Accesses
70h 7Fh
1FFh
36Fh
370h
2EFh
2F0h
Accesses
70h 7Fh
27Fh
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
Accesses
70h 7Fh
2FFh
General
Purpose
Register
80 Bytes
3EFh
3F0h
Accesses
70h 7Fh
37Fh
Accesses
70h 7Fh
3FFh
PIC16(L)F1705/9
DS40001729B-page 24
TABLE 3-3:
TABLE 3-4:
BANK 0
000h
BANK 1
080h
Core Registers
(Table 3-2)
BANK 2
100h
Core Registers
(Table 3-2)
BANK 3
180h
Core Registers
(Table 3-2)
BANK 4
200h
Core Registers
(Table 3-2)
BANK 5
280h
Core Registers
(Table 3-2)
BANK 6
300h
Core Registers
(Table 3-2)
BANK 7
380h
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
00Bh
00Ch
00Dh
00Eh
00Fh
010h
011h
012h
013h
014h
015h
016h
PORTA
PORTB
PORTC
PIR1
PIR2
PIR3
TMR0
TMR1L
08Bh
08Ch
08Dh
08Eh
08Fh
090h
091h
092h
093h
094h
095h
096h
TRISA
TRISB
TRISC
PIE1
PIE2
PIE3
OPTION_REG
PCON
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
LATA
LATB
LATC
CM1CON0
CM1CON1
CM2CON0
CM2CON1
CMOUT
BORCON
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
ANSELA
ANSELB
ANSELC
PMADRL
PMADRH
PMDATL
PMDATH
PMCON1
PMCON2
20Bh
20Ch
20Dh
20Eh
20Fh
210h
211h
212h
213h
214h
215h
216h
WPUA
WPUB
WPUC
SSP1BUF
SSP1ADD
SSP1MSK
SSP1STAT
SSP1CON
SSP1CON2
28Bh
28Ch
28Dh
28Eh
28Fh
290h
291h
292h
293h
294h
295h
296h
ODCONA
ODCONB
ODCONC
CCPR1L
CCPR1H
CCP1CON
30Bh
30Ch
30Dh
30Eh
30Fh
310h
311h
312h
313h
314h
315h
316h
SLRCONA
SLRCONB
SLRCONC
38Bh
38Ch
38Dh
38Eh
38Fh
390h
391h
392h
393h
394h
395h
396h
INLVLA
INLVLB
INLVLC
IOCAP
IOCAN
IOCAF
IOCBP
IOCBN
IOCBF
017h
018h
019h
01Ah
01Bh
01Ch
01Dh
01Eh
TMR1H
T1CON
T1GCON
TMR2
PR2
T2CON
097h
098h
099h
09Ah
09Bh
09Ch
09Dh
09Eh
WDTCON
OSCTUNE
OSCCON
OSCSTAT
ADRESL
ADRESH
ADCON0
ADCON1
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
FVRCON
DAC1CON0
DAC1CON1
ZCD1CON
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
VREGCON(1)
RC1REG
TX1REG
SP1BRGL
SP1BRGH
RC1STA
TX1STA
217h
218h
219h
21Ah
21Bh
21Ch
21Dh
21Eh
SSP1CON3
297h
298h
299h
29Ah
29Bh
29Ch
29Dh
29Eh
CCPR2L
CCPR2H
CCP2CON
CCPTMRS
317h
318h
319h
31Ah
31Bh
31Ch
31Dh
31Eh
397h
398h
399h
39Ah
39Bh
39Ch
39Dh
39Eh
IOCCP
IOCCN
IOCCF
01Fh
020h
09Fh
0A0h
ADCON2
11Fh
120h
19Fh
1A0h
BAUD1CON
21Fh
220h
29Fh
2A0h
31Fh
320h
39Fh
3A0h
06Fh
070h
0EFh
0F0h
Common RAM
70h 7Fh
07Fh
16Fh
170h
Accesses
70h 7Fh
0FFh
Legend:
DS40001729B-page 25
Note
1:
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
1EFh
1F0h
Accesses
70h 7Fh
17Fh
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
26Fh
270h
Accesses
70h 7Fh
1FFh
General
Purpose
Register
80 Bytes
27Fh
36Fh
370h
2EFh
2F0h
Accesses
70h 7Fh
General
Purpose
Register
80 Bytes
Accesses
70h 7Fh
2FFh
General
Purpose
Register
80 Bytes
3EFh
3F0h
Accesses
70h 7Fh
37Fh
Accesses
70h 7Fh
3FFh
PIC16(L)F1705/9
General
Purpose
Register
80 Bytes
BANK 8
400h
BANK 9
480h
Core Registers
(Table 3-2)
40Bh
40Ch
40Dh
40Eh
40Fh
410h
411h
412h
413h
414h
415h
416h
417h
418h
419h
41Ah
41Bh
41Ch
41Dh
41Eh
41Fh
420h
TMR4
PR4
T4CON
TMR6
PR6
T6CON
Core Registers
(Table 3-2)
48Bh
48Ch
48Dh
48Eh
48Fh
490h
491h
492h
493h
494h
495h
496h
497h
498h
499h
49Ah
49Bh
49Ch
49Dh
49Eh
49Fh
4A0h
General
Purpose
Register
80 Bytes
46Fh
470h
Accesses
70h 7Fh
80Bh
80Ch
Unimplemented
Read as 0
86Fh
870h
8EFh
8F0h
Accesses
70h 7Fh
87Fh
Legend:
Accesses
70h 7Fh
97Fh
A7Fh
7FFh
BANK 23
B80h
Core Registers
(Table 3-2)
B0Bh
B0Ch
Unimplemented
Read as 0
Core Registers
(Table 3-2)
B8Bh
B8Ch
Unimplemented
Read as 0
Unimplemented
Read as 0
BEFh
BF0h
B6Fh
B70h
Accesses
70h 7Fh
AFFh
Accesses
70h 7Fh
BANK 22
Core Registers
(Table 3-2)
Accesses
70h 7Fh
B7Fh
Unimplemented
Read as 0
Accesses
70h 7Fh
B00h
AEFh
AF0h
78Bh
78Ch
78Dh
78Eh
78Fh
790h
791h
792h
793h
794h
795h
796h
797h
798h
799h
79Ah
79Bh
79Ch
79Dh
79Eh
79Fh
7A0h
7EFh
7F0h
77Fh
A8Bh
A8Ch
Core Registers
(Table 3-2)
Unimplemented
Read as 0
BANK 21
Accesses
70h 7Fh
76Fh
770h
A80h
A6Fh
A70h
70Bh
70Ch
70Dh
70Eh
70Fh
710h
711h
712h
713h
714h
715h
716h
717h
718h
719h
71Ah
71Bh
71Ch
71Dh
71Eh
71Fh
720h
Accesses
70h 7Fh
Unimplemented
Read as 0
Accesses
70h 7Fh
9FFh
6EFh
6F0h
Core Registers
(Table 3-2)
Unimplemented
Read as 0
COG1PHR
COG1PHF
COG1BLKR
COG1BLKF
COG1DBR
COG1DBF
COG1CON0
COG1CON1
COG1RIS
COG1RSIM
COG1FIS
COG1FSIM
COG1ASD0
COG1ASD1
COG1STR
BANK 15
780h
Core Registers
(Table 3-2)
Unimplemented
Read as 0
BANK 20
A0Bh
A0Ch
9EFh
9F0h
96Fh
970h
Accesses
70h 7Fh
8FFh
98Bh
98Ch
68Bh
68Ch
68Dh
68Eh
68Fh
690h
691h
692h
693h
694h
695h
696h
697h
698h
699h
69Ah
69Bh
69Ch
69Dh
69Eh
69Fh
6A0h
6FFh
A00h
Core Registers
(Table 3-2)
Unimplemented
Read as 0
Unimplemented
Read as 0
BANK 14
700h
Core Registers
(Table 3-2)
Accesses
70h 7Fh
BANK 19
Core Registers
(Table 3-2)
Unimplemented
Read as 0
64Fh
650h
PWM3DCL
PWM3DCH
PWM3CON
PWM4DCL
PWM4DCH
PWM4CON
General
Purpose
Register
48 Bytes
67Fh
980h
90Bh
90Ch
60Bh
60Ch
60Dh
60Eh
60Fh
610h
611h
612h
613h
614h
615h
616h
617h
618h
619h
61Ah
61Bh
61Ch
61Dh
61Eh
61Fh
620h
Accesses
70h 7Fh
BANK 18
BANK 13
680h
Core Registers
(Table 3-2)
66Fh
670h
5FFh
900h
Core Registers
(Table 3-2)
General
Purpose
Register
80 Bytes
Accesses
70h 7Fh
BANK 17
88Bh
88Ch
58Bh
58Ch
58Dh
58Eh
58Fh
590h
591h
592h
593h
594h
595h
596h
597h
598h
599h
59Ah
59Bh
59Ch
59Dh
59Eh
59Fh
5A0h
5EFh
5F0h
57Fh
880h
Core Registers
(Table 3-2)
OPA1CON
OPA2CON
BANK 12
600h
Core Registers
(Table 3-2)
General
Purpose
Register
80 Bytes
Accesses
70h 7Fh
BANK 16
800h
50Bh
50Ch
50Dh
50Eh
50Fh
510h
511h
512h
513h
514h
515h
516h
517h
518h
519h
51Ah
51Bh
51Ch
51Dh
51Eh
51Fh
520h
56Fh
570h
4FFh
BANK 11
580h
Core Registers
(Table 3-2)
General
Purpose
Register
80 Bytes
4EFh
4F0h
47Fh
BANK 10
500h
Accesses
70h 7Fh
BFFh
PIC16(L)F1705/9
DS40001729B-page 26
TABLE 3-5:
TABLE 3-6:
BANK 24
C00h
BANK 25
C80h
Core Registers
(Table 3-2)
C0Bh
C0Ch
C0Dh
C0Eh
C0Fh
C10h
C11h
C12h
C13h
C14h
C15h
C16h
C17h
C18h
C19h
C1Ah
C1Bh
C1Ch
C1Dh
C1Eh
C1Fh
C20h
Core Registers
(Table 3-2)
C8Bh
C8Ch
C8Dh
C8Eh
C8Fh
C90h
C91h
C92h
C93h
C94h
C95h
C96h
C97h
C98h
C99h
C9Ah
C9Bh
C9Ch
C9Dh
C9Eh
C9Fh
CA0h
Unimplemented
Read as 0
CFFh
Core Registers
(Table 3-2)
D0Bh
D0Ch
D0Dh
D0Eh
D0Fh
D10h
D11h
D12h
D13h
D14h
D15h
D16h
D17h
D18h
D19h
D1Ah
D1Bh
D1Ch
D1Dh
D1Eh
D1Fh
D20h
Unimplemented
Read as 0
CEFh
CF0h
Accesses
70h 7Fh
Legend:
D6Fh
D70h
D8Bh
D8Ch
D8Dh
D8Eh
D8Fh
D90h
D91h
D92h
D93h
D94h
D95h
D96h
D97h
D98h
D99h
D9Ah
D9Bh
D9Ch
D9Dh
D9Eh
D9Fh
DA0h
Accesses
70h 7Fh
D7Fh
BANK 29
E80h
Core Registers
(Table 3-2)
BANK 30
F00h
Core Registers
(Table 3-2)
BANK 31
F80h
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
E0Bh
E0Ch
E0Dh
E0Eh
E0Fh
E10h
E11h
E12h
E13h
E14h
E15h
E16h
E17h
See Table 3-7 for
E18h register mapping
E19h
details
E1Ah
E1Bh
E1Ch
E1Dh
E1Eh
E1Fh
E20h
E8Bh
E8Ch
E8Dh
E8Eh
E8Fh
E90h
E91h
E92h
E93h
E94h
E95h
E96h
E97h
See Table 3-7 for
E98h register mapping
E99h
details
E9Ah
E9Bh
E9Ch
E9Dh
E9Eh
E9Fh
EA0h
F0Bh
F0Ch
F0Dh
F0Eh
F0Fh
F10h
F11h
F12h
F13h
F14h
F15h
F16h
F17h
See Table 3-7 for
F18h register mapping
F19h
details
F1Ah
F1Bh
F1Ch
F1Dh
F1Eh
F1Fh
F20h
F8Bh
F8Ch
F8Dh
F8Eh
F8Fh
F90h
F91h
F92h
F93h
F94h
F95h
F96h
F97h
See Table 3-8 for
F98h register mapping
F99h
details
F9Ah
F9Bh
F9Ch
F9Dh
F9Eh
F9Fh
FA0h
E6Fh
E70h
EEFh
EF0h
F6Fh
F70h
FEFh
FF0h
Unimplemented
Read as 0
DEFh
DF0h
BANK 28
E00h
Core Registers
(Table 3-2)
Unimplemented
Read as 0
Accesses
70h 7Fh
CFFh
BANK 27
D80h
Accesses
70h 7Fh
DFFh
Accesses
70h 7Fh
E7Fh
Accesses
70h 7Fh
EFFh
Accesses
70h 7Fh
F7Fh
Accesses
70h 7Fh
FFFh
DS40001729B-page 27
PIC16(L)F1705/9
C6Fh
C70h
BANK 26
D00h
PIC16(L)F1705/9
TABLE 3-7:
PPSLOCK
INTPPS
T0CKIPPS
T1CKIPPS
T1GPPS
CCP1PPS
CCP2PPS
COGINPPS
SSPCLKPPS
SSPDATPPS
SSPSSPPS
RXPPS
CKPPS
CLCIN0PPS
CLCIN1PPS
CLCIN2PPS
CLCIN3PPS
Bank 29
E8Ch
E8Dh
E8Eh
E8Fh
E90h
E91h
E92h
E93h
E94h
E95h
E96h
E97h
E98h
E99h
E9Ah
E9Bh
E9Ch
E9Dh
E9Eh
E9Fh
EA0h
EA1h
EA2h
EA3h
EA4h
EA5h
EA6h
EA7h
EA8h
EA9h
EAAh
EABh
EACh
EADh
EAEh
EAFh
EB0h
EB1h
EB2h
EB3h
EB4h
EB5h
EB6h
EB7h
EB8h
EB9h
EBAh
EBBh
EBCh
EBDh
EBEh
EBFh
EC0h
E6Fh
Legend:
Note 1:
DS40001729B-page 28
RA0PPS
RA1PPS
RA2PPS
RA4PPS
RA5PPS
RB4PPS(1)
RB5PPS(1)
RB6PPS(1)
RB7PPS(1)
RC0PPS
RC1PPS
RC2PPS
RC3PPS
RC4PPS
RC5PPS
RC6PPS(1)
RC7PPS(1)
Bank 30
F0Ch
F0Dh
F0Eh
F0Fh
F10h
F11h
F12h
F13h
F14h
F15h
F16h
F17h
F18h
F19h
F1Ah
F1Bh
F1Ch
F1Dh
F1Eh
F1Fh
F20h
F21h
F22h
F23h
F24h
F25h
F26h
F27h
F28h
F29h
F2Ah
F2Bh
F2Ch
F2Dh
F2Eh
F2Fh
F30h
F31h
F32h
F33h
F34h
F35h
F36h
F37h
F38h
F39h
F3Ah
F3Bh
F3Ch
F3Dh
F3Eh
F3Fh
F40h
EEFh
CLCDATA
CLC1CON
CLC1POL
CLC1SEL0
CLC1SEL1
CLC1SEL2
CLC1SEL3
CLC1GLS0
CLC1GLS1
CLC1GLS2
CLC1GLS3
CLC2CON
CLC2POL
CLC2SEL0
CLC2SEL1
CLC2SEL2
CLC2SEL3
CLC2GLS0
CLC2GLS1
CLC2GLS2
CLC2GLS3
CLC3CON
CLC3POL
CLC3SEL0
CLC3SEL1
CLC3SEL2
CLC3SEL3
CLC3GLS0
CLC3GLS1
CLC3GLS2
CLC3GLS3
F6Fh
PIC16(L)F1705/9
TABLE 3-8:
PIC16(L)F1705/9 MEMORY
MAP, BANK 31
Bank 31
F8Ch
FE3h
FE4h
FE5h
FE6h
FE7h
FE8h
FE9h
FEAh
FEBh
FECh
FEDh
FEEh
FEFh
Legend:
Unimplemented
Read as 0
STATUS_SHAD
WREG_SHAD
BSR_SHAD
PCLATH_SHAD
FSR0L_SHAD
FSR0H_SHAD
FSR1L_SHAD
FSR1H_SHAD
STKPTR
TOSL
TOSH
= Unimplemented data memory locations,
read as 0,
DS40001729B-page 29
PIC16(L)F1705/9
3.4.5
TABLE 3-9:
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
Bank 0-31
x00h or
INDF0
x80h
x01h or
INDF1
x81h
x02h or
PCL
x82h
x03h or
STATUS
x83h
TO
PD
DC
x04h or
FSR0L
x84h
x05h or
FSR0H
x85h
x06h or
FSR1L
x86h
x07h or
FSR1H
x87h
x08h or
BSR
x88h
x09h or
WREG
x89h
x0Bh or
INTCON
x8Bh
GIE
Note
1:
BSR4
BSR3
BSR2
BSR1
BSR0
Working Register
x0Ah or
PCLATH
x8Ah
Legend:
TMR0IE
INTE
IOCIE
TMR0IF
IOCIF
DS40001729B-page 30
PIC16(L)F1705/9
TABLE 3-10:
Addr
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
--uu uuuu
Bank 0
00Ch PORTA
00Dh PORTB(3)
00Eh PORTC
RA5
RA4
RA3
RA2
RA1
RA0
--xx xxxx
RB7
RB6
RB5
RB4
xxxx ----
uuuu ----
RC7(3)
RC6(3)
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx
uuuu uuuu
00Fh
Unimplemented
010h
Unimplemented
011h
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
0000 0-00
0000 0-00
012h
PIR2
OSFIF
C2IF
C1IF
BCL1IF
TMR6IF
TMR4IF
CCP2IF
000- 00--
000- 00--
013h
PIR3
COGIF
ZCDIF
CLC3IF
CLC2IF
CLC1IF
--00 -000
--00 -000
014h
Unimplemented
015h
TMR0
xxxx xxxx
uuuu uuuu
uuuu uuuu
016h
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
017h
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
uuuu uuuu
018h
T1CON
0000 00-0
uuuu uu-u
019h
T1GCON
0000 0x00
uuuu uxuu
TMR1CS<1:0>
TMR1GE
T1GPOL
T1CKPS<1:0>
T1GTM
T1GSPM
T1OSCEN
T1SYNC
T1GGO/
DONE
T1GVAL
TMR1ON
T1GSS<1:0>
01Ah TMR2
xxxx xxxx
uuuu uuuu
01Bh PR2
xxxx xxxx
uuuu uuuu
-000 0000
-000 0000
01Ch T2CON
01Dh
to
01Fh
T2OUTPS<3:0>
TMR2ON
T2CKPS<1:0>
Unimplemented
Bank 1
TRISA5
TRISA4
(1)
TRISA2
TRISA1
TRISA0
--11 1111
--11 1111
08Dh TRISB
TRISB7
TRISB6
TRISB5
TRISB4
1111 ----
1111 ----
08Eh TRISC
TRISC7(3)
TRISC6(3)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
08Ch TRISA
(3)
1111 1111
1111 1111
08Fh
Unimplemented
090h
Unimplemented
091h
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
092h
PIE2
OSFIE
C2IE
C1IE
BCL1IE
TMR6IE
TMR4IE
CCP2IE
000- 0000
000- 0000
093h
PIE3
COGIE
ZCDIE
CLC3IE
CLC2IE
CLC1IE
--00 -000
--00 -000
094h
095h
OPTION_REG
WPUEN
INTEDG
TMR0CS
TMR0SE
096h
PCON
STKOVF
STKUNF
RWDT
097h
WDTCON
098h
OSCTUNE
099h
OSCCON
SPLLEN
09Ah OSCSTAT
SOSCR
Unimplemented
PSA
1111 1111
1111 1111
BOR
00-1 11qq
qq-q qquu
SWDTEN
--01 0110
--01 0110
--00 0000
--00 0000
0011 1-00
0011 1-00
00q0 --00
qqqq --0q
uuuu uuuu
PS<2:0>
RMCLR
RI
POR
WDTPS<4:0>
TUN<5:0>
IRCF<3:0>
PLLR
OSTS
HFIOFR
HFIOFL
MFIOFR
SCS<1:0>
LFIOFR
HFIOFS
09Bh ADRESL
xxxx xxxx
09Ch ADRESH
xxxx xxxx
uuuu uuuu
-000 0000
-000 0000
0000 -000
0000 -000
0000 ----
0000 ----
09Dh ADCON0
09Eh ADCON1
ADFM
09Fh ADCON2
Legend:
Note
1:
2:
3:
4:
CHS<4:0>
ADCS<2:0>
TRIGSEL<3:0>
GO/DONE
ADNREF
ADON
ADREF<1:0>
DS40001729B-page 31
PIC16(L)F1705/9
TABLE 3-10:
Addr
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Bank 2
10Ch LATA
10Dh LATB(3)
10Eh LATC
LATA5
LATA4
LATA2
LATA1
LATA0
--xx -xxx
--uu -uuu
LATB7
LATB6
LATB5
LATB4
xxxx ----
uuuu ----
LATC7(3)
LATC6(3)
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0
xxxx xxxx
uuuu uuuu
10Fh
Unimplemented
110h
Unimplemented
111h
CM1CON0
C1ON
C1OUT
00-0 0100
00-0 0100
112h
CM1CON1
C1INTP
C1INTN
0000 0000
0000 0000
113h
CM2CON0
C2ON
C2OUT
00-0 0100
00-0 0100
114h
CM2CON1
C2INTP
C2INTN
0000 0000
0000 0000
115h
CMOUT
MC2OUT
MC1OUT
---- --00
---- --00
116h
BORCON
SBOREN
BORFS
BORRDY
1x-- ---q
uu-- ---u
117h
FVRCON
FVREN
FVRRDY
TSEN
TSRNG
CDAFVR<1:0>
118h
DAC1CON0
DAC1EN
---
DAC1OE1
DAC1OE2
DAC1PSS<1:0>
119h
DAC1CON1
11Ah
Unimplemented
11Bh
Unimplemented
0-00 --00
0-00 --00
11Ch ZCD1CON
C1POL
C1ZLF
C1SP
C2ZLF
C2SP
C1PCH<2:0>
C2POL
C1HYS
C1SYNC
C1NCH<2:0>
C2PCH<2:0>
C2HYS
C2SYNC
C2NCH<2:0>
ADFVR<1:0>
---
DAC1NSS
DAC1R<7:0>
ZCD1EN
ZCD1OUT
ZCD1POL
ZCD1INTP
ZCD1INTN
0q00 0000
0q00 0000
0-00 00-0
0-00 00-0
0000 0000
0000 0000
11Dh
Unimplemented
11Eh
Unimplemented
11Fh
Unimplemented
Bank 3
18Ch ANSELA
ANSA4
ANSA2
ANSA1
ANSA0
---1 1111
---1 1111
18Dh ANSELB(3)
ANSB5
ANSB4
--11 ----
--11 ----
ANSC7(3)
ANSC6(3)
ANSC5(2)
ANSC4(2)
ANSC3
ANSC2
ANSC1
ANSC0
18Eh ANSELC
1111 1111
1111 1111
18Fh
Unimplemented
190h
Unimplemented
191h
PMADRL
0000 0000
0000 0000
192h
PMADRH
1000 0000
1000 0000
193h
PMDATL
xxxx xxxx
uuuu uuuu
194h
PMDATH
--xx xxxx
--uu uuuu
195h
PMCON1
CFGS
-000 x000
-000 q000
196h
PMCON2
197h
VREGCON(4)
(1)
FREE
WRERR
WREN
WR
RD
198h
Unimplemented
199h
RC1REG
19Ah TX1REG
VREGPM
Reserved
0000 0000
0000 0000
---- --01
---- --01
0000 0000
0000 0000
0000 0000
0000 0000
19Bh SP1BRGL
BRG<7:0>
0000 0000
0000 0000
19Ch SP1BRGH
BRG<15:8>
0000 0000
0000 0000
0000 0000
19Dh RC1STA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 0000
19Eh TX1STA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
0000 0010
0000 0010
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
01-0 0-00
01-0 0-00
19Fh BAUD1CON
Legend:
Note
1:
2:
3:
4:
DS40001729B-page 32
PIC16(L)F1705/9
TABLE 3-10:
Addr
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
--11 1111
Bank 4
20Ch WPUA
20Dh WPUB(3)
20Eh WPUC
WPUA5
WPUA4
WPUA3
WPUA2
WPUA1
WPUA0
--11 1111
WPUB7
WPUB6
WPUB5
WPUB4
1111 ----
1111 ----
WPUC7(3)
WPUC6(3)
WPUC5
WPUC4
WPUC3
WPUC2
WPUC1
WPUC0
1111 1111
1111 1111
20Fh
Unimplemented
210h
Unimplemented
211h
SSP1BUF
xxxx xxxx
uuuu uuuu
212h
SSP1ADD
0000 0000
0000 0000
213h
SSP1MSK
1111 1111
1111 1111
214h
SSP1STAT
SMP
CKE
D/A
215h
SSP1CON1
WCOL
SSPOV
SSPEN
CKP
216h
SSP1CON2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
217h
SSP1CON3
ACKTIM
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
218h
21Fh
ADD<7:0>
MSK<7:0>
S
R/W
UA
BF
0000 0000
0000 0000
0000 0000
0000 0000
SEN
0000 0000
0000 0000
DHEN
0000 0000
0000 0000
SSPM<3:0>
Unimplemented
Bank 5
28Ch ODCONA
28Dh ODCONB(3)
28Eh ODCONC
ODA5
ODA4
ODA2
ODA1
ODA0
--00 -000
--00 -000
ODB7
ODB6
ODB5
ODB4
0000 ----
0000 ----
ODC7(3)
ODC6(3)
ODC5
ODC4
ODC3
ODC2
ODC1
ODC0
0000 0000
0000 0000
28Fh
Unimplemented
290h
Unimplemented
291h
CCPR1L
xxxx xxxx
uuuu uuuu
292h
CCPR1H
293h
CCP1CON
DC1B<1:0>
CCP1M<3:0>
xxxx xxxx
uuuu uuuu
--00 0000
--00 0000
uuuu uuuu
294h
297h
Unimplemented
298h
CCPR2L
xxxx xxxx
299h
CCPR2H
xxxx xxxx
uuuu uuuu
--00 0000
--00 0000
0000 0000
0000 0000
--00 -000
29Ah CCP2CON
29Bh
29Dh
DC2B<1:0>
CCP2M<3:0>
Unimplemented
29Eh CCPTMRS
29Fh
P4TSEL<1:0>
P3TSEL<1:0>
C2TSEL<1:0>
C1TSEL<1:0>
Unimplemented
Bank 6
30Ch SLRCONA
30Dh SLRCONB(3)
30Eh SLRCONC
30Fh
31Fh
Legend:
Note
1:
2:
3:
4:
SLRA5
SLRA4
SLRA2
SLRA1
SLRA0
--00 -000
SLRB7
SLRB6
SLRB5
SLRB4
0000 ----
0000 ----
SLRC7(3)
SLRC6(3)
SLRC5
SLRC4
SLRC3
SLRC2
SLRC1
SLRC0
0000 0000
0000 0000
Unimplemented
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as 0, r = reserved.
Shaded locations are unimplemented, read as 0.
Unimplemented, read as 1.
PIC16(L)F1705 only.
PIC16(L)F1709 only.
Unimplemented on PIC16LF1705/9.
DS40001729B-page 33
PIC16(L)F1705/9
TABLE 3-10:
Addr
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Bank 7
38Ch INLVLA
INLVLA5
INLVLA4
INLVLA3
INLVLA2
INLVLA1
INLVLA0
--11 1111
--11 1111
INLVLB7
INLVLB6
INLVLB5
INLVLB4
1111 ----
1111 ----
38Eh INLVLC
INLVLC7(3)
INLVLC6(3)
INLVLC5
INLVLC4
INLVLC3
INLVLC2
INLVLC1
INLVLC0
1111 1111
1111 1111
38Fh
Unimplemented
390h
Unimplemented
391h
IOCAP
IOCAP5
IOCAP4
IOCAP3
IOCAP2
IOCAP1
IOCAP0
--00 0000
--00 0000
392h
IOCAN
IOCAN5
IOCAN4
IOCAN3
IOCAN2
IOCAN1
IOCAN0
--00 0000
--00 0000
393h
IOCAF
IOCAF5
IOCAF4
IOCAF3
IOCAF2
IOCAF1
IOCAF0
--00 0000
--00 0000
394h
IOCBP(3)
IOCBP7
IOCBP6
IOCBP5
IOCBP4
0000 ----
0000 ----
395h
IOCBN(3)
IOCBN7
IOCBN6
IOCBN5
IOCBN4
0000 ----
0000 ----
396h
IOCBF(3)
IOCBF7
IOCBF6
IOCBF5
IOCBF4
0000 ----
0000 ----
397h
IOCCP
IOCCP7(3)
IOCCP6(3)
IOCCP5
IOCCP4
IOCCP3
IOCCP2
IOCCP1
IOCCP0
0000 0000
0000 0000
398h
IOCCN
IOCCN7(3)
IOCCN6(3)
IOCCN5
IOCCN4
IOCCN3
IOCCN2
IOCCN1
IOCCN0
0000 0000
0000 0000
IOCCF
IOCCF7(3)
IOCCF6(3)
IOCCF5
IOCCF4
IOCCF3
IOCCF2
IOCCF1
IOCCF0
0000 0000
0000 0000
Unimplemented
Unimplemented
uuuu uuuu
38Dh INLVLB(3)
399h
39Ah
39Fh
Bank 8
40Ch
414h
415h
TMR4
xxxx xxxx
416h
PR4
xxxx xxxx
uuuu uuuu
417h
T4CON
-000 0000
-000 0000
uuuu uuuu
T4OUTPS<3:0>
TMR4ON
T4CKPS<1:0>
418h
41Bh
Unimplemented
41Ch TMR6
xxxx xxxx
41Dh PR6
xxxx xxxx
uuuu uuuu
-000 0000
-000 0000
Unimplemented
Unimplemented
Unimplemented
00-0 --00
00-0 --00
00-0 --00
00-0 --00
41Eh T6CON
41Fh
T6OUTPS<3:0>
TMR6ON
T6CKPS<1:0>
Bank 9
48Ch
to
49Fh
Bank 10
50Ch
510h
511h
OPA1CON
512h
514h
515h
OPA2CON
516h
51Fh
Legend:
Note
1:
2:
3:
4:
OPA1EN
OPA1SP
OPA1UG
OPA1PCH<1:0>
Unimplemented
OPA2EN
OPA2SP
OPA2UG
OPA2PCH<1:0>
Unimplemented
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as 0, r = reserved.
Shaded locations are unimplemented, read as 0.
Unimplemented, read as 1.
PIC16(L)F1705 only.
PIC16(L)F1709 only.
Unimplemented on PIC16LF1705/9.
DS40001729B-page 34
PIC16(L)F1705/9
TABLE 3-10:
Addr
Name
Value on all
other
Resets
Unimplemented
Unimplemented
xx-- ----
uu-- ----
xxxx xxxx
uuuu uuuu
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 11
D8Ch
to
DADh
Bank 12
60Ch
to
616h
617h
PWM3DCL
618h
PWM3DCH
619h
PWM3CON
61Ah PWM4DCL
PWMxDCL<1:0>
61Dh
61Fh
PWMxDCH<9:2>
PWM3EN
0-x0 ----
u-uu ----
00-- ----
uu-- ----
0000 0000
uuuu uuuu
0-x0 ----
u-uu ----
Unimplemented
Unimplemented
PWMxDCL<1:0>
PWM3OUT PWM3POL
61Bh PWM4DCH
61Ch PWM4CON
PWMxDCH<9:2>
PWM4EN
PWM4OUT PWM4POL
Bank 13
68Ch
to
690h
691h
COG1PHR
--xx xxxx
--uu uuuu
692h
COG1PHF
--xx xxxx
--uu uuuu
693h
COG1BLKR
--xx xxxx
--uu uuuu
694h
COG1BLKF
--xx xxxx
--uu uuuu
695h
COG1DBR
--xx xxxx
--uu uuuu
696h
COG1DBF
--xx xxxx
--uu uuuu
697h
COG1CON0
G1EN
G1LD
00-0 0000
00-0 0000
698h
COG1CON1
G1RDBS
G1FDBS
G1POLD
G1POLC
G1POLB
G1POLA
00-- 0000
00-- 0000
G1RIS6
G1RIS5
G1RIS4
G1RIS3
G1RIS2
G1RIS1
G1RIS0
-000 0000
-000 0000
69Ah COG1RSIM
G1RSIM6
G1RSIM5
G1RSIM4
G1RSIM3
G1RSIM2
G1RSIM1
G1RSIM0
-000 0000
-000 0000
69Bh COG1FIS
-000 0000
-000 0000
699h
COG1RIS
G1FIS5
G1FIS4
G1FIS3
G1FIS2
G1FIS1
G1FIS0
G1FSIM5
G1FSIM4
G1FSIM3
G1FSIM2
G1FSIM1
G1FSIM0
-000 0000
-000 0000
0001 01--
0001 01--
G1AS1E
G1AS0E
---- 0000
---- 0000
G1STRA
0000 0001
0000 0001
G1FSIM6
69Dh COG1ASD0
G1ASE
G1ARSEN
69Eh COG1ASD1
G1SDATD
G1MD<2:0>
G1FIS6
69Ch COG1FSIM
69Fh COG1STR
G1CS<1:0>
G1SDATC
G1ASDBD<1:0>
G1SDATB
G1SDATA
G1ASDAC<1:0>
G1AS3E
G1STRD
G1AS2E
G1STRC
G1STRB
Bank 14-27
x0Ch/
x8Ch
x1Fh/
x9Fh
Legend:
Note
1:
2:
3:
4:
Unimplemented
DS40001729B-page 35
PIC16(L)F1705/9
TABLE 3-10:
Addr
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
---- ---0
---- ---0
Bank 28
E0Ch
E0Eh
Unimplemented
E0Fh PPSLOCK
E10h INTPPS
INTPPS<4:0>
---0 0010
---u uuuu
E11h
T0CKIPPS
T0CKIPPS<4:0>
---0 0010
---u uuuu
E12h T1CKIPPS
T1CKIPPS<4:0>
---0 0101
---u uuuu
E13h T1GPPS
T1GPPS<4:0>
---0 0100
---u uuuu
E14h CCP1PPS
CCP1PPS<4:0>
---1 0101
---u uuuu
E15h CCP2PPS
CCP2PPS<4:0>
---1 0011
---u uuuu
PPSLOCKED
Unimplemented
E16h
E17h COGINPPS
E18h
E1Fh
COGINPPS<4:0>
Unimplemented
E20h SSPCLKPPS
E21h SSPDATPPS
E22h SSPSSPPS
E23h
E25h CKPPS
---0 0010
---u uuuu
SSPCLKPPS<4:0>
SSPCLKPPS<4:0>
SSPDATPPS<4:0>
SSPDATPPS<4:0>
SSPSSPPS<4:0>
SSPSSPPS<4:0>
RXPPS<4:0>
RXPPS<4:0>
CKPPS<4:0>
CKPPS<4:0>
Unimplemented
E24h RXPPS
E26h
Unimplemented
E27h
Unimplemented
E28h CLCIN0PPS
CLCIN0PPS<4:0>
---1 0011
---u uuuu
E29h CLCIN1PPS
CLCIN1PPS<4:0>
---1 0100
---u uuuu
E2Ah CLCIN2PPS
CLCIN2PPS<4:0>
---1 0001
---u uuuu
E2Bh CLCIN3PPS
CLCIN3PPS<4:0>
---0 0101
---u uuuu
E2Ch
to
E7Fh
Legend:
Note
1:
2:
3:
4:
Unimplemented
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as 0, r = reserved.
Shaded locations are unimplemented, read as 0.
Unimplemented, read as 1.
PIC16(L)F1705 only.
PIC16(L)F1709 only.
Unimplemented on PIC16LF1705/9.
DS40001729B-page 36
PIC16(L)F1705/9
TABLE 3-10:
Addr
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Bank 29
E8Ch
E8Fh
E90h RA0PPS
Unimplemented
RA0PPS<4:0>
---0 0000
---u uuuu
E91h RA1PPS
RA1PPS<4:0>
---0 0000
---u uuuu
E92h RA2PPS
RA2PPS<4:0>
---0 0000
---u uuuu
E93h
Unimplemented
E94h RA4PPS
E95h RA5PPS
RA4PPS<4:0>
---0 0000
---u uuuu
RA5PPS<4:0>
---0 0000
---u uuuu
E96h
Unimplemented
E97h
Unimplemented
E98h
Unimplemented
E99h
Unimplemented
E9Ah
Unimplemented
E9Bh
Unimplemented
(3)
E9Ch RB4PPS
RB4PPS<4:0>
---0 0000
---u uuuu
E9Dh RB5PPS(3)
RB5PPS<4:0>
---0 0000
---u uuuu
(3)
E9Eh RB6PPS
RB6PPS<4:0>
---0 0000
---u uuuu
E9Fh
RB7PPS(3)
RB7PPS<4:0>
---0 0000
---u uuuu
EA0h RC0PPS
RC0PPS<4:0>
---0 0000
---u uuuu
EA1h RC1PPS
RC1PPS<4:0>
---0 0000
---u uuuu
EA2h RC2PPS
RC2PPS<4:0>
---0 0000
---u uuuu
EA3h RC3PPS
RC3PPS<4:0>
---0 0000
---u uuuu
EA4h RC4PPS
RC4PPS<4:0>
---0 0000
---u uuuu
EA5h RC5PPS
RC5PPS<4:0>
---0 0000
---u uuuu
EA6h RC6PPS(3)
RC6PPS<4:0>
---0 0000
---u uuuu
EA7h
RC7PPS<4:0>
---0 0000
---u uuuu
RC7PPS(3)
EA8h
EEFh
Legend:
Note
1:
2:
3:
4:
Unimplemented
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as 0, r = reserved.
Shaded locations are unimplemented, read as 0.
Unimplemented, read as 1.
PIC16(L)F1705 only.
PIC16(L)F1709 only.
Unimplemented on PIC16LF1705/9.
DS40001729B-page 37
PIC16(L)F1705/9
TABLE 3-10:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
MLC3OUT
MLC2OUT
MLC1OUT
---- -000
---- -000
F10h CLC1CON
LC1EN
LC1OUT
LC1INTP
0-x0 0000
0-00 0000
F11h
LC1POL
LC1G1POL
x--- xxxx
0--- uuuu
F12h CLC1SEL0
LC1D1S<4:0>
---x xxxx
---u uuuu
F13h CLC1SEL1
LC1D2S<4:0>
---x xxxx
---u uuuu
F14h CLC1SEL2
LC1D3S<4:0>
---x xxxx
---u uuuu
F15h CLC1SEL3
LC1D4S<4:0>
---x xxxx
---u uuuu
Addr
Name
Bit 7
Bank 30
F0Ch
F0Eh
Unimplemented
F0Fh CLCDATA
CLC1POL
LC1INTN
LC1MODE<2:0>
F16h CLC1GLS0
LC1G1D1N
xxxx xxxx
uuuu uuuu
F17h CLC1GLS1
LC1G2D1N
xxxx xxxx
uuuu uuuu
F18h CLC1GLS2
LC1G3D1N
xxxx xxxx
uuuu uuuu
F19h CLC1GLS3
LC1G4D1N
xxxx xxxx
uuuu uuuu
F1Ah CLC2CON
LC2EN
LC2OUT
LC2INTP
F1Bh CLC2POL
LC2POL
F1Ch CLC2SEL0
F1Dh CLC2SEL1
F1Eh CLC2SEL2
F1Fh CLC2SEL3
LC2INTN
LC2MODE<2:0>
0-00 0000
0-00 0000
0--- xxxx
0--- uuuu
LC2D1S<4:0>
---x xxxx
---u uuuu
LC2D2S<4:0>
---x xxxx
---u uuuu
LC2D3S<4:0>
---x xxxx
---u uuuu
LC2D4S<4:0>
---x xxxx
---u uuuu
LC2G1POL
F20h CLC2GLS0
LC2G1D1N
xxxx xxxx
uuuu uuuu
F21h CLC2GLS1
LC2G2D1N
xxxx xxxx
uuuu uuuu
F22h CLC2GLS2
LC2G3D1N
xxxx xxxx
uuuu uuuu
F23h CLC2GLS3
LC2G4D1N
xxxx xxxx
uuuu uuuu
F24h CLC3CON
LC3EN
LC3OUT
LC3INTP
F25h CLC3POL
LC3POL
F26h CLC3SEL0
F27h CLC3SEL1
F28h CLC3SEL2
F29h CLC3SEL3
LC3INTN
LC3MODE<2:0>
0-00 0000
0-00 0000
0--- xxxx
0--- uuuu
LC3D1S<4:0>
---x xxxx
---u uuuu
LC3D2S<4:0>
---x xxxx
---u uuuu
LC3D3S<4:0>
---x xxxx
---u uuuu
LC3D4S<4:0>
---x xxxx
---u uuuu
LC3G1POL
F2Ah CLC3GLS0
LC3G1D1N
xxxx xxxx
uuuu uuuu
F2Bh CLC3GLS1
LC3G2D1N
xxxx xxxx
uuuu uuuu
F2Ch CLC3GLS2
LC3G3D1N
xxxx xxxx
uuuu uuuu
F2Dh CLC3GLS3
LC3G4D1N
xxxx xxxx
uuuu uuuu
F2Eh
F6Fh
Unimplemented
Legend:
Note
1:
2:
3:
4:
DS40001729B-page 38
PIC16(L)F1705/9
TABLE 3-10:
Addr
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
---- -xxx
---- -uuu
xxxx xxxx
uuuu uuuu
---x xxxx
---u uuuu
-xxx xxxx
uuuu uuuu
Bank 31
F8Ch
to
FE3h
Unimplemented
FE4h STATUS_
SHAD
FE5h WREG_
SHAD
DC
FE6h BSR_SHAD
FE7h PCLATH_
SHAD
FE8h FSR0L_
SHAD
xxxx xxxx
uuuu uuuu
FE9h FSR0H_
SHAD
xxxx xxxx
uuuu uuuu
FEAh FSR1L_
SHAD
xxxx xxxx
uuuu uuuu
FEBh FSR1H_
SHAD
xxxx xxxx
uuuu uuuu
FECh
Unimplemented
FEDh STKPTR
FEEh TOSL
FEFh TOSH
Legend:
Note
1:
2:
3:
4:
---1 1111
---1 1111
xxxx xxxx
uuuu uuuu
-xxx xxxx
-uuu uuuu
DS40001729B-page 39
PIC16(L)F1705/9
3.5
3.5.3
FIGURE 3-3:
PC
LOADING OF PC IN
DIFFERENT SITUATIONS
14
PCH
14
PCH
PCL
PCLATH
PC
ALU Result
PCL
11
OPCODE <10:0>
PC
14
PCH
PCL
0
CALLW
PCLATH
PC
Instruction with
PCL as
Destination
GOTO, CALL
PCLATH
14
PCH
W
PCL
0
BRW
PC + W
14
PCH
3.5.4
BRANCHING
15
PC
The CALLW instruction enables computed calls by combining PCLATH and W to form the destination address.
A computed CALLW is accomplished by loading the W
register with the desired address and executing CALLW.
The PCL register is loaded with the value of W and
PCH is loaded with PCLATH.
PCL
0
BRA
15
PC + OPCODE <8:0>
3.5.1
MODIFYING PCL
3.5.2
COMPUTED GOTO
DS40001729B-page 40
PIC16(L)F1705/9
3.6
3.6.1
Stack
Note:
FIGURE 3-4:
TOSH:TOSL
0x0F
STKPTR = 0x1F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
TOSH:TOSL
0x1F
0x0000
STKPTR = 0x1F
DS40001729B-page 41
PIC16(L)F1705/9
FIGURE 3-5:
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
TOSH:TOSL
FIGURE 3-6:
0x00
Return Address
STKPTR = 0x00
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
TOSH:TOSL
DS40001729B-page 42
0x06
Return Address
0x05
Return Address
0x04
Return Address
0x03
Return Address
0x02
Return Address
0x01
Return Address
0x00
Return Address
STKPTR = 0x06
PIC16(L)F1705/9
FIGURE 3-7:
TOSH:TOSL
3.6.2
0x0F
Return Address
0x0E
Return Address
0x0D
Return Address
0x0C
Return Address
0x0B
Return Address
0x0A
Return Address
0x09
Return Address
0x08
Return Address
0x07
Return Address
0x06
Return Address
0x05
Return Address
0x04
Return Address
0x03
Return Address
0x02
Return Address
0x01
Return Address
0x00
Return Address
STKPTR = 0x10
OVERFLOW/UNDERFLOW RESET
3.7
Indirect Addressing
DS40001729B-page 43
PIC16(L)F1705/9
FIGURE 3-8:
INDIRECT ADDRESSING
0x0000
0x0000
Traditional
Data Memory
0x0FFF
0x1000
0x1FFF
0x0FFF
Reserved
0x2000
Linear
Data Memory
0x29AF
0x29B0
FSR
Address
Range
0x7FFF
0x8000
Reserved
0x0000
Program
Flash Memory
0xFFFF
Note:
0x7FFF
Not all memory regions are completely implemented. Consult device memory tables for memory limits.
DS40001729B-page 44
PIC16(L)F1705/9
3.7.1
FIGURE 3-9:
BSR
Indirect Addressing
From Opcode
7
0
Bank Select
Location Select
FSRxH
0
FSRxL
0
Bank Select
11111
Bank 31
Location Select
0x00
0x7F
DS40001729B-page 45
PIC16(L)F1705/9
3.7.2
3.7.3
FIGURE 3-10:
7
FSRnH
0 0 1
FSRnL
FIGURE 3-11:
7
1
FSRnH
PROGRAM FLASH
MEMORY MAP
0
Location Select
Location Select
0x2000
FSRnL
0x8000
0x0000
0x020
Bank 0
0x06F
0x0A0
Bank 1
0x0EF
0x120
Program
Flash
Memory
(low 8
bits)
Bank 2
0x16F
0xF20
Bank 30
0x29AF
DS40001729B-page 46
0xF6F
0xFFFF
0x7FFF
PIC16(L)F1705/9
4.0
DEVICE CONFIGURATION
4.1
Configuration Words
DS40001729B-page 47
PIC16(L)F1705/9
4.2
REGISTER 4-1:
R/P-1
R/P-1
FCMEN
IESO
CLKOUTEN
R/P-1
R/P-1
U-1
BOREN<1:0>
bit 13
R/P-1
(1)
CP
R/P-1
R/P-1
MCLRE
PWRTE
bit 8
R/P-1
R/P-1
R/P-1
WDTE<1:0>
R/P-1
R/P-1
FOSC<2:0>
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
0 = Bit is cleared
1 = Bit is set
bit 13
bit 12
bit 11
bit 10-9
bit 8
Unimplemented: Read as 1
bit 7
bit 6
bit 5
bit 4-3
DS40001729B-page 48
PIC16(L)F1705/9
REGISTER 4-1:
bit 2-0
Note 1:
DS40001729B-page 49
PIC16(L)F1705/9
REGISTER 4-2:
(1)
R/P-1
DEBUG
R/P-1
(2)
LPBOR
R/P-1
(3)
BORV
R/P-1
R/P-1
STVREN
PLLEN
bit 13
bit 8
R/P-1
U-1
U-1
U-1
U-1
R/P-1
ZCDDIS
PPS1WAY
R/P-1
R/P-1
WRT<1:0>
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
0 = Bit is cleared
1 = Bit is set
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6-3
Unimplemented: Read as 1
bit 2
bit 1-0
Note 1:
2:
3:
The LVP bit cannot be programmed to 0 when Programming mode is entered via LVP.
The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers
and programmers. For normal device operation, this bit should be maintained as a 1.
See VBOR parameter for specific trip point voltages.
DS40001729B-page 50
PIC16(L)F1705/9
4.3
Code Protection
4.3.1
4.4
Write Protection
4.5
User ID
DS40001729B-page 51
PIC16(L)F1705/9
4.6
4.7
REGISTER 4-3:
DEV<13:8>
bit 13
R
bit 8
R
DEV<7:0>
bit 7
bit 0
Legend:
R = Readable bit
1 = Bit is set
bit 13-0
0 = Bit is cleared
DEV<13:0>: Device ID bits
Device
DEVID<13:0> Values
PIC16F1705
PIC16LF1705
PIC16F1709
PIC16LF1709
REGISTER 4-4:
REV<13:8>
bit 13
R
bit 8
R
REV<7:0>
bit 7
bit 0
Legend:
R = Readable bit
1 = Bit is set
bit 13-0
0 = Bit is cleared
REV<13:0>: Revision ID bits
DS40001729B-page 52
PIC16(L)F1705/9
5.0
RESETS
FIGURE 5-1:
MCLRE
VPP/MCLR
Sleep
WDT
Time-out
Device
Reset
Power-on
Reset
VDD
BOR
Active(1)
Brown-out
Reset
LPBOR
Reset
Note 1:
LFINTOSC
Power-up
Timer
PWRTE
DS40001729B-page 53
PIC16(L)F1705/9
5.1
5.2
The POR circuit holds the device in Reset until VDD has
reached an acceptable level for minimum operation.
Slow rising VDD, fast operating speeds or analog
performance may require greater than minimum VDD.
The PWRT, BOR or MCLR features can be used to
extend the start-up period until all device operation
conditions have been met.
5.1.1
TABLE 5-1:
BOREN<1:0>
SBOREN
Device Mode
BOR Mode
11
Active
Awake
Active
10
Sleep
Disabled
Active
Disabled
Disabled
01
00
Note 1: In these specific cases, Release of POR and Wake-up from Sleep, there is no delay in start-up. The BOR
ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR
circuit is forced on by the BOREN<1:0> bits.
5.2.1
BOR IS ALWAYS ON
5.2.2
5.2.3
DS40001729B-page 54
PIC16(L)F1705/9
FIGURE 5-2:
BROWN-OUT SITUATIONS
VDD
VBOR
Internal
Reset
TPWRT(1)
VDD
VBOR
Internal
Reset
< TPWRT
TPWRT(1)
VDD
VBOR
Internal
Reset
Note 1:
5.3
TPWRT(1)
REGISTER 5-1:
R/W-1/u
R/W-0/u
U-0
U-0
U-0
U-0
U-0
R-q/u
SBOREN
BORFS(1)
BORRDY
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5-1
Unimplemented: Read as 0
bit 0
Note 1:
DS40001729B-page 55
PIC16(L)F1705/9
5.4
5.4.1
ENABLING LPBOR
5.4.1.1
5.5
MCLR
5.6
5.7
RESET Instruction
5.8
5.9
5.10
TABLE 5-2:
MCLR CONFIGURATION
MCLRE
LVP
MCLR
Disabled
Enabled
Enabled
5.5.1
MCLR ENABLED
5.5.2
MCLR DISABLED
DS40001729B-page 56
Power-Up Timer
5.11
Start-up Sequence
The total time-out will vary based on oscillator configuration and Power-up Timer configuration. See
Section 6.0 Oscillator Module (with Fail-Safe
Clock Monitor) for more information.
The Power-up Timer and oscillator start-up timer run
independently of MCLR Reset. If MCLR is kept low
long enough, the Power-up Timer and oscillator
start-up timer will expire. Upon bringing MCLR high, the
device will begin execution after 10 FOSC cycles (see
Figure 5-3). This is useful for testing purposes or to
synchronize more than one device operating in parallel.
PIC16(L)F1705/9
FIGURE 5-3:
VDD
Internal POR
TPWRT
Power-up Timer
MCLR
TMCLR
Internal RESET
Oscillator Modes
External Crystal
TOST
Internal Oscillator
Oscillator
FOSC
FOSC
DS40001729B-page 57
PIC16(L)F1705/9
5.12
TABLE 5-3:
RMCLR
RI
POR
BOR
TO
PD
Condition
Power-on Reset
Brown-out Reset
WDT Reset
TABLE 5-4:
STATUS
Register
PCON
Register
Power-on Reset
0000h
---1 1000
00-- 110x
0000h
---u uuuu
uu-- 0uuu
0000h
---1 0uuu
uu-- 0uuu
WDT Reset
0000h
---0 uuuu
uu-- uuuu
PC + 1
---0 0uuu
uu-- uuuu
Brown-out Reset
0000h
---1 1uuu
00-- 11u0
---1 0uuu
uu-- uuuu
---u uuuu
uu-- u0uu
Condition
PC + 1
(1)
0000h
0000h
---u uuuu
1u-- uuuu
0000h
---u uuuu
u1-- uuuu
DS40001729B-page 58
PIC16(L)F1705/9
5.13
5.14
REGISTER 5-2:
R/W/HS-0/q
R/W/HS-0/q
U-0
STKOVF
STKUNF
R/W/HC-1/q R/W/HC-1/q
RWDT
R/W/HC-1/q
R/W/HC-q/u
R/W/HC-q/u
RI
POR
BOR
RMCLR
bit 7
bit 0
Legend:
HC = Bit is cleared by hardware
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
bit 1
bit 0
DS40001729B-page 59
PIC16(L)F1705/9
TABLE 5-5:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
BORCON
SBOREN
BORFS
BORRDY
55
PCON
STKOVF
STKUNF
RWDT
RMCLR
RI
POR
BOR
59
STATUS
TO
PD
DC
22
WDTCON
SWDTEN
99
WDTPS<4:0>
Legend: = unimplemented location, read as 0. Shaded cells are not used by Resets.
DS40001729B-page 60
PIC16(L)F1705/9
6.0
6.1
Overview
DS40001729B-page 61
PIC16(L)F1705/9
SIMPLIFIED PIC MCU CLOCK SOURCE BLOCK DIAGRAM
FIGURE 6-1:
Secondary
Oscillator Timer1
SOSCO
T1OSCEN
Enable
Oscillator
SOSCI
T1OSC
01
External
Oscillator
OSC2
0
Sleep
00
PRIMUX
OSC1
4 x PLL
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
250 kHz
125 kHz
62.5 kHz
31.25 kHz
PLLMUX
500 kHz
Source
16 MHz
(HFINTOSC)
500 kHz
(MFINTOSC)
31 kHz
Source
INTOSC
SCS<1:0>
31 kHz
0000
31 kHz (LFINTOSC)
Inputs
FOSC<2:0>
PLLEN or
SPLLEN
0
=100
1
=00
100
00
DS40001729B-page 62
1X
1111
MUX
HFPLL
Postscaler
Internal
Oscillator
Block
FOSC
To CPU and
Peripherals
IRCF<3:0>
SCS
Sleep
0
1
Outputs
IRCF
PRIMUX
PLLMUX
=1110
1110
PIC16(L)F1705/9
6.2
6.2.1
FIGURE 6-2:
OSC1/CLKIN
Clock from
Ext. System
PIC MCU
FOSC/4 or I/O(1)
Note 1:
OSC2/CLKOUT
6.2.1.1
EC Mode
6.2.1.2
DS40001729B-page 63
PIC16(L)F1705/9
FIGURE 6-3:
QUARTZ CRYSTAL
OPERATION (LP, XT OR
HS MODE)
FIGURE 6-4:
CERAMIC RESONATOR
OPERATION
(XT OR HS MODE)
PIC MCU
PIC MCU
OSC1/CLKIN
C1
To Internal
Logic
Quartz
Crystal
C2
Note 1:
2:
OSC1/CLKIN
RS(1)
RF(2)
C1
Sleep
OSC2/CLKOUT
RP(3)
C2 Ceramic
RS(1)
Resonator
Note 1:
Note 1: Quartz
crystal
characteristics
vary
according to type, package and
manufacturer. The user should consult the
manufacturer data sheets for specifications
and recommended application.
2: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
3: For oscillator design assistance, reference
the following Microchip Application Notes:
AN826, Crystal Oscillator Basics and
Crystal Selection for rfPIC and PIC
Devices (DS00826)
AN849, Basic PIC Oscillator Design
(DS00849)
AN943, Practical PIC Oscillator
Analysis and Design (DS00943)
AN949, Making Your Oscillator Work
(DS00949)
DS40001729B-page 64
To Internal
Logic
RF(2)
Sleep
OSC2/CLKOUT
6.2.1.3
PIC16(L)F1705/9
6.2.1.4
4x PLL
6.2.1.5
Secondary Oscillator
FIGURE 6-5:
Note 1: Quartz
crystal
characteristics
vary
according to type, package and
manufacturer. The user should consult the
manufacturer data sheets for specifications
and recommended application.
2: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
3: For oscillator design assistance, reference
the following Microchip Application Notes:
AN826, Crystal Oscillator Basics and
Crystal Selection for rfPIC and PIC
Devices (DS00826)
AN849, Basic PIC Oscillator Design
(DS00849)
AN943, Practical PIC Oscillator
Analysis and Design (DS00943)
AN949, Making Your Oscillator Work
(DS00949)
TB097, Interfacing a Micro Crystal
MS1V-T1K 32.768 kHz Tuning Fork
Crystal to a PIC16F690/SS (DS91097)
AN1288, Design Practices for
Low-Power External Oscillators
(DS01288)
QUARTZ CRYSTAL
OPERATION
(SECONDARY
OSCILLATOR)
PIC MCU
SOSCI
C1
To Internal
Logic
32.768 kHz
Quartz
Crystal
C2
SOSCO
DS40001729B-page 65
PIC16(L)F1705/9
6.2.1.6
External RC Mode
6.2.2
The external Resistor-Capacitor (EXTRC) mode supports the use of an external RC circuit. This allows the
designer maximum flexibility in frequency choice while
keeping costs to a minimum when clock accuracy is not
required.
The RC circuit connects to OSC1. OSC2/CLKOUT is
available for general purpose I/O or CLKOUT. The
function of the OSC2/CLKOUT pin is determined by the
CLKOUTEN bit in Configuration Words.
Figure 6-6 shows the external RC mode connections.
FIGURE 6-6:
EXTERNAL RC MODES
VDD
PIC MCU
REXT
OSC1/CLKIN
Internal
Clock
CEXT
VSS
FOSC/4 or I/O(1)
OSC2/CLKOUT
2.
3.
DS40001729B-page 66
PIC16(L)F1705/9
6.2.2.1
HFINTOSC
6.2.2.2
MFINTOSC
The
Medium-Frequency
Internal
Oscillator
(MFINTOSC) is a factory calibrated 500 kHz internal
clock source. The frequency of the MFINTOSC can be
altered via software using the OSCTUNE register
(Register 6-3).
The output of the MFINTOSC connects to a postscaler
and multiplexer (see Figure 6-1). One of nine
frequencies derived from the MFINTOSC can be
selected via software using the IRCF<3:0> bits of the
OSCCON register. See Section 6.2.2.7 Internal
Oscillator Clock Switch Timing for more information.
The MFINTOSC is enabled by:
Configure the IRCF<3:0> bits of the OSCCON
register for the desired HF frequency, and
FOSC<2:0> = 100, or
Set the System Clock Source (SCS) bits of the
OSCCON register to 1x
The Medium-Frequency Internal Oscillator Ready bit
(MFIOFR) of the OSCSTAT register indicates when the
MFINTOSC is running.
6.2.2.3
6.2.2.4
LFINTOSC
DS40001729B-page 67
PIC16(L)F1705/9
6.2.2.5
Note:
6.2.2.6
DS40001729B-page 68
PIC16(L)F1705/9
6.2.2.7
5.
6.
7.
DS40001729B-page 69
PIC16(L)F1705/9
FIGURE 6-7:
HFINTOSC/
MFINTOSC
HFINTOSC/
MFINTOSC
Oscillator Delay(1)
2-cycle Sync
Running
LFINTOSC
0
IRCF <3:0>
System Clock
HFINTOSC/
MFINTOSC
HFINTOSC/
MFINTOSC
2-cycle Sync
Running
LFINTOSC
IRCF <3:0>
System Clock
LFINTOSC
HFINTOSC/MFINTOSC
LFINTOSC
Oscillator Delay(1) 2-cycle Sync
Running
HFINTOSC/
MFINTOSC
IRCF <3:0>
=0
System Clock
Note:
DS40001729B-page 70
PIC16(L)F1705/9
6.3
Clock Switching
6.3.3
SECONDARY OSCILLATOR
6.3.1
6.3.4
6.3.2
DS40001729B-page 71
PIC16(L)F1705/9
6.4
6.4.1
TABLE 6-1:
Switch From
Switch To
Frequency
Oscillator Delay
LFINTOSC(1)
Sleep/POR
MFINTOSC(1)
HFINTOSC(1)
31 kHz
31.25 kHz-500 kHz
31.25 kHz-16 MHz
2 cycles
Sleep/POR
EC, RC(1)
DC 32 MHz
2 cycles
LFINTOSC
EC,
RC(1)
DC 32 MHz
1 cycle of each
Sleep/POR
Secondary Oscillator
32 kHz-20 MHz
LP, XT, HS(1)
MFINTOSC(1)
HFINTOSC(1)
2 s (approx.)
LFINTOSC(1)
31 kHz
PLL inactive
PLL active
2 ms (approx.)
Note 1:
16-32 MHz
1 cycle of each
PLL inactive.
DS40001729B-page 72
PIC16(L)F1705/9
6.4.2
1.
2.
3.
4.
5.
6.
7.
TWO-SPEED START-UP
SEQUENCE
6.4.3
FIGURE 6-8:
TWO-SPEED START-UP
INTOSC
TOST
OSC1
1022 1023
OSC2
Program Counter
PC - N
PC
PC + 1
System Clock
DS40001729B-page 73
PIC16(L)F1705/9
6.5
6.5.3
FIGURE 6-9:
External
Clock
LFINTOSC
Oscillator
64
31 kHz
(~32 s)
488 Hz
(~2 ms)
Sample Clock
6.5.1
FAIL-SAFE OPERATION
FAIL-SAFE DETECTION
6.5.2
6.5.4
Clock
Failure
Detected
6.5.5
DS40001729B-page 74
PIC16(L)F1705/9
FIGURE 6-10:
Sample Clock
Oscillator
Failure
System
Clock
Output
Clock Monitor Output
(Q)
Failure
Detected
OSCFIF
Test
Note:
Test
Test
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
DS40001729B-page 75
PIC16(L)F1705/9
6.6
REGISTER 6-1:
R/W-0/0
SPLLEN
R/W-1/1
R/W-1/1
R/W-1/1
IRCF<3:0>
U-0
R/W-0/0
R/W-0/0
SCS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-3
bit 2
Unimplemented: Read as 0
bit 1-0
Note 1:
2:
DS40001729B-page 76
PIC16(L)F1705/9
REGISTER 6-2:
R-1/q
R-0/q
R-q/q
R-0/q
R-0/q
R-q/q
R-0/0
R-0/q
SOSCR
PLLR
OSTS
HFIOFR
HFIOFL
MFIOFR
LFIOFR
HFIOFS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
q = Conditional
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS40001729B-page 77
PIC16(L)F1705/9
REGISTER 6-3:
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
TUN<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
111111 =
000000 = Oscillator module is running at the factory-calibrated frequency
000001 =
011110 =
011111 = Maximum frequency
TABLE 6-2:
Name
Bit 6
Bit 5
Bit 4
OSCCON
SPLLEN
OSCSTAT
SOSCR
PLLR
OSCTUNE
PIR2
OSFIF
C2IF
C1IF
PIE2
OSFIE
C2IE
C1IE
T1CON
Legend:
Bit 3
IRCF<3:0>
TMR1CS<1:0>
OSTS
Bit 1
HFIOFR
HFIOFL
Bit 0
SCS<1:0>
MFIOFR
LFIOFR
76
HFIOFS
TUN<5:0>
BCL1IF
T1CKPS<1:0>
Register
on Page
77
78
TMR6IF
TMR4IF
CCP2IF
89
BCL1IE
TMR6IE
T1OSCEN
T1SYNC
TMR4IE
CCP2IE
86
TMR1ON
254
= unimplemented location, read as 0. Shaded cells are not used by clock sources.
TABLE 6-3:
Name
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
CONFIG1
13:8
FCMEN
IESO
CLKOUTEN
7:0
CP
MCLRE
PWRTE
Legend:
Bit 2
WDTE<1:0>
Bit 10/2
Bit 9/1
BOREN<1:0>
FOSC<2:0>
Bit 8/0
Register
on Page
48
= unimplemented location, read as 0. Shaded cells are not used by clock sources.
DS40001729B-page 78
PIC16(L)F1705/9
7.0
PIC16(L)F1705/9 INTERRUPTS
Operation
Interrupt Latency
Interrupts During Sleep
INT Pin
Automatic Context Saving
FIGURE 7-1:
INTERRUPT LOGIC
TMR0IF
TMR0IE
Peripheral Interrupts
(TMR1IF) PIR1<0>
(TMR1IE) PIE1<0>
Wake-up
(If in Sleep mode)
INTF
INTE
IOCIF
IOCIE
Interrupt
to CPU
PEIE
PIRn<7>
PIEn<7>
GIE
DS40001729B-page 79
PIC16(L)F1705/9
7.1
Operation
7.2
Interrupt Latency
The INTCON, PIR1 and PIR2 registers record individual interrupts via interrupt flag bits. Interrupt flag bits will
be set, regardless of the status of the GIE, PEIE and
individual interrupt enable bits.
The following events happen when an interrupt event
occurs while the GIE bit is set:
Current prefetched instruction is flushed
GIE bit is cleared
Current Program Counter (PC) is pushed onto the
stack
Critical registers are automatically saved to the
shadow registers (See Section 7.5 Automatic
Context Saving)
PC is loaded with the interrupt vector 0004h
The firmware within the Interrupt Service Routine (ISR)
should determine the source of the interrupt by polling
the interrupt flag bits. The interrupt flag bits must be
cleared before exiting the ISR to avoid repeated
interrupts. Because the GIE bit is cleared, any interrupt
that occurs while executing the ISR will be recorded
through its interrupt flag, but will not cause the
processor to redirect to the interrupt vector.
The RETFIE instruction exits the ISR by popping the
previous address from the stack, restoring the saved
context from the shadow registers and setting the GIE
bit.
For additional information on a specific interrupts
operation, refer to its peripheral chapter.
Note 1: Individual interrupt flag bits are set,
regardless of the state of any other
enable bits.
2: All interrupts will be ignored while the GIE
bit is cleared. Any interrupt occurring
while the GIE bit is clear will be serviced
when the GIE bit is set again.
DS40001729B-page 80
PIC16(L)F1705/9
FIGURE 7-2:
INTERRUPT LATENCY
OSC1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKR
Interrupt Sampled
during Q1
Interrupt
GIE
PC
Execute
PC-1
PC
1 Cycle Instruction at PC
PC+1
0004h
0005h
NOP
NOP
Inst(0004h)
PC+1/FSR
ADDR
New PC/
PC+1
0004h
0005h
Inst(PC)
NOP
NOP
Inst(0004h)
FSR ADDR
PC+1
PC+2
0004h
0005h
INST(PC)
NOP
NOP
NOP
Inst(0004h)
Inst(0005h)
FSR ADDR
PC+1
0004h
0005h
INST(PC)
NOP
NOP
Inst(0004h)
Inst(PC)
Interrupt
GIE
PC
Execute
PC-1
PC
2 Cycle Instruction at PC
Interrupt
GIE
PC
Execute
PC-1
PC
3 Cycle Instruction at PC
Interrupt
GIE
PC
Execute
PC-1
PC
3 Cycle Instruction at PC
PC+2
NOP
NOP
DS40001729B-page 81
PIC16(L)F1705/9
FIGURE 7-3:
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKOUT (3)
(4)
INT pin
(1)
(1)
INTF
(5)
GIE
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
Note 1:
PC
Inst (PC)
Inst (PC 1)
PC + 1
Inst (PC + 1)
Inst (PC)
PC + 1
Forced NOP
0004h
Inst (0004h)
Forced NOP
0005h
Inst (0005h)
Inst (0004h)
2:
Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3:
4:
For minimum width of INT pulse, refer to AC specifications in Section 32.0 Electrical Specifications.
5:
DS40001729B-page 82
PIC16(L)F1705/9
7.3
7.4
INT Pin
7.5
W register
STATUS register (except for TO and PD)
BSR register
FSR registers
PCLATH register
Upon exiting the Interrupt Service Routine, these registers are automatically restored. Any modifications to
these registers during the ISR will be lost. If modifications to any of these registers are desired, the corresponding shadow register should be modified and the
value will be restored when exiting the ISR. The
shadow registers are available in Bank 31 and are
readable and writable. Depending on the users
application, other registers may also need to be saved.
DS40001729B-page 83
PIC16(L)F1705/9
7.6
REGISTER 7-1:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R-0/0
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
Note:
The IOCIF Flag bit is read-only and cleared when all the interrupt-on-change flags in the IOCxF registers
have been cleared by software.
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
DS40001729B-page 84
PIC16(L)F1705/9
REGISTER 7-2:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note:
DS40001729B-page 85
PIC16(L)F1705/9
REGISTER 7-3:
R/W-0/0
R/W-0/0
R/W-0/0
OSFIE
C2IE
C1IE
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
BCL1IE
TMR6IE
TMR4IE
CCP2IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
Unimplemented: Read as 0
bit 3
bit 2
bit 1
bit 0
Note:
DS40001729B-page 86
PIC16(L)F1705/9
REGISTER 7-4:
U-0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
COGIE
ZCDIE
CLC3IE
CLC2IE
CLC1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5
bit 4
bit 3
Unimplemented: Read as 0
bit 2
bit 1
bit 0
Note:
DS40001729B-page 87
PIC16(L)F1705/9
REGISTER 7-5:
R/W-0/0
R/W-0/0
R-0/0
R-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note:
DS40001729B-page 88
PIC16(L)F1705/9
REGISTER 7-6:
R/W-0/0
R/W-0/0
R/W-0/0
OSFIF
C2IF
C1IF
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
BCL1IF
TMR6IF
TMR4IF
CCP2IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
Unimplemented: Read as 0
bit 3
bit 2
bit 1
bit 0
Note:
DS40001729B-page 89
PIC16(L)F1705/9
REGISTER 7-7:
U-0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
COGIF
ZCDIF
CLC3IF
CLC2IF
CLC1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5
bit 4
bit 3
Unimplemented: Read as 0
bit 2
bit 1
bit 0
Note:
DS40001729B-page 90
PIC16(L)F1705/9
TABLE 7-1:
Name
INTCON
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
84
OPTION_REG WPUEN
PIE1
TMR1GIE
ADIE
PIE2
OSFIE
C2IE
PIE3
PIR1
TMR1GIF
ADIF
PIR2
OSFIF
PIR3
RCIE
PSA
PS<2:0>
245
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
85
C1IE
BCL1IE
TMR6IE
TMR4IE
CCP2IE
86
COGIE
ZCDIE
CLC3IE
CLC2IE
CLC1IE
87
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
88
C2IF
C1IF
BCL1IF
TMR6IF
TMR4IF
CCP2IF
89
COGIF
ZCDIF
CLC3IF
CLC2IF
CLC1IF
90
Legend: = unimplemented location, read as 0. Shaded cells are not used by interrupts.
DS40001729B-page 91
PIC16(L)F1705/9
8.0
8.1
1.
2.
3.
4.
5.
6.
1.
2.
3.
4.
5.
6.
7.
8.
9.
DS40001729B-page 92
PIC16(L)F1705/9
8.1.1
FIGURE 8-1:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKIN(1)
TOST(3)
CLKOUT(2)
Interrupt flag
GIE bit
(INTCON reg.)
Instruction Flow
PC
Instruction
Fetched
Instruction
Executed
Note
1:
2:
3:
4:
Processor in
Sleep
PC
Inst(PC) = Sleep
Inst(PC - 1)
PC + 1
PC + 2
PC + 2
Inst(PC + 1)
Inst(PC + 2)
Sleep
Inst(PC + 1)
PC + 2
Forced NOP
0004h
0005h
Inst(0004h)
Inst(0005h)
Forced NOP
Inst(0004h)
DS40001729B-page 93
PIC16(L)F1705/9
8.2
8.2.1
8.2.2
Note:
The Low-Power Sleep mode is beneficial for applications that stay in Sleep mode for long periods of time.
The Normal mode is beneficial for applications that
need to wake from Sleep quickly and frequently.
DS40001729B-page 94
PIC16(L)F1705/9
8.3
REGISTER 8-1:
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0/0
R/W-1/1
VREGPM
Reserved
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-2
Unimplemented: Read as 0
bit 1
bit 0
Note 1:
2:
PIC16F1705/9 only.
See Section 32.0 Electrical Specifications.
TABLE 8-1:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
84
IOCAP
IOCAP5
IOCAP4
IOCAP3
IOCAP2
IOCAP1
IOCAP0
146
IOCAN
IOCAN5
IOCAN4
IOCAN3
IOCAN2
IOCAN1
IOCAN0
146
Name
INTCON
IOCAF5
IOCAF4
IOCAF3
IOCAF2
IOCAF1
IOCAF0
147
IOCBP(1)
IOCBP7
IOCBP6
IOCBP5
IOCBP4
147
(1)
IOCBN
IOCBN7
IOCBN6
IOCBN5
IOCBN4
148
IOCBF(1)
IOCBF7
IOCBF6
IOCBF5
IOCBF4
148
IOCCP
IOCCP7(1)
IOCCP6(1)
IOCCP5
IOCCP4
IOCCP3
IOCCP2
IOCCP1
IOCCP0
149
IOCCN
IOCCN7(1)
IOCCN6(1)
IOCCN5
IOCCN4
IOCCN3
IOCCN2
IOCCN1
IOCCN0
149
IOCCF
IOCCF7(1)
IOCCF6(1)
IOCCF5
IOCCF4
IOCCF3
IOCCF2
IOCCF1
IOCCF0
149
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
85
PIE2
OSFIE
C2IE
C1IE
BCL1IE
TMR6IE
TMR4IE
CCP2IE
86
PIE3
COGIE
ZCDIE
CLC3IE
CLC2IE
CLC1IE
87
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
88
PIR2
OSFIF
C2IF
C1IF
BCL1IF
TMR6IF
TMR4IF
CCP2IF
89
IOCAF
PIR3
COGIF
ZCDIF
CLC3IF
CLC2IF
CLC1IF
90
STATUS
TO
PD
DC
22
VREGCON(2)
VREGPM
Reserved
95
WDTCON
SWDTEN
99
Legend:
Note 1:
2:
WDTPS<4:0>
= unimplemented location, read as 0. Shaded cells are not used in Power-Down mode.
PIC16(L)F1709 only.
PIC16F1705/9 only.
DS40001729B-page 95
PIC16(L)F1705/9
9.0
FIGURE 9-1:
WDTE<1:0> = 01
SWDTEN
WDTE<1:0> = 11
LFINTOSC
23-bit Programmable
Prescaler WDT
WDT Time-out
WDTE<1:0> = 10
Sleep
DS40001729B-page 96
WDTPS<4:0>
PIC16(L)F1705/9
9.1
9.4
9.2
9.2.1
WDT IS ALWAYS ON
TABLE 9-1:
Any Reset
CLRWDT instruction is executed
Device enters Sleep
Device wakes up from Sleep
Oscillator fail
WDT is disabled
Oscillator Start-up Timer (OST) is running
9.5
9.2.3
9.2.2
WDTE<1:0>
SWDTEN
Device
Mode
11
10
WDT
Mode
Active
Awake Active
1
01
Sleep
X
0
00
9.3
Disabled
Active
Disabled
Disabled
Time-Out Period
DS40001729B-page 97
PIC16(L)F1705/9
TABLE 9-2:
WDT
WDTE<1:0> = 00
WDTE<1:0> = 01 and SWDTEN = 0
WDTE<1:0> = 10 and enter Sleep
CLRWDT Command
Cleared
DS40001729B-page 98
PIC16(L)F1705/9
9.6
REGISTER 9-1:
U-0
R/W-0/0
R/W-1/1
R/W-0/0
R/W-1/1
R/W-1/1
(1)
WDTPS<4:0>
bit 7
R/W-0/0
SWDTEN
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-1
bit 0
Note 1:
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
DS40001729B-page 99
PIC16(L)F1705/9
TABLE 9-3:
Name
Bit 6
OSCCON
SPLLEN
STATUS
WDTCON
Bit 5
Bit 4
Bit 3
IRCF<3:0>
Bit 2
Bit 1
TO
PD
Bit 0
SCS<1:0>
DC
WDTPS<4:0>
Register
on Page
76
22
SWDTEN
99
Legend: x = unknown, u = unchanged, = unimplemented locations read as 0. Shaded cells are not used by
Watchdog Timer.
TABLE 9-4:
Name
CONFIG1
Bits
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
IESO
CLKOUTEN
13:8
FCMEN
7:0
CP
MCLRE
PWRTE
WDTE<1:0>
Bit 10/2
Bit 9/1
Bit 8/0
BOREN<1:0>
FOSC<2:0>
Register
on Page
48
Legend: = unimplemented location, read as 0. Shaded cells are not used by Watchdog Timer.
DS40001729B-page 100
PIC16(L)F1705/9
10.0
PMCON1
PMCON2
PMDATL
PMDATH
PMADRL
PMADRH
10.1
10.1.1
10.2
See Table 10-1 for Erase Row size and the number of
write latches for Flash program memory.
DS40001729B-page 101
PIC16(L)F1705/9
TABLE 10-1:
FLASH MEMORY
ORGANIZATION BY DEVICE
Device
PIC16(L)F1705
PIC16(L)F1709
10.2.1
Row Erase
(words)
Write
Latches
(words)
32
32
Write
the
desired
address
to
the
PMADRH:PMADRL register pair.
Clear the CFGS bit of the PMCON1 register.
Then, set control bit RD of the PMCON1 register.
FIGURE 10-1:
FLASH PROGRAM
MEMORY READ
FLOWCHART
Start
Read Operation
Select
Program or Configuration Memory
(CFGS)
Select
Word Address
(PMADRH:PMADRL)
End
Read Operation
DS40001729B-page 102
PIC16(L)F1705/9
FIGURE 10-2:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
Flash ADDR
Flash Data
PC + 1
INSTR (PC)
INSTR(PC - 1)
executed here
PMADRH,PMADRL
INSTR (PC + 1)
BSF PMCON1,RD
executed here
PC
+3
PC+3
PMDATH,PMDATL
INSTR(PC + 1)
instruction ignored
Forced NOP
executed here
PC + 5
PC + 4
INSTR (PC + 3)
INSTR(PC + 2)
instruction ignored
Forced NOP
executed here
INSTR (PC + 4)
INSTR(PC + 3)
executed here
INSTR(PC + 4)
executed here
RD bit
PMDATH
PMDATL
Register
EXAMPLE 10-1:
PMADRL
PROG_ADDR_LO
PMADRL
PROG_ADDR_HI
PMADRH
BCF
BSF
NOP
NOP
PMCON1,CFGS
PMCON1,RD
;
;
;
;
MOVF
MOVWF
MOVF
MOVWF
PMDATL,W
PROG_DATA_LO
PMDATH,W
PROG_DATA_HI
;
;
;
;
DS40001729B-page 103
PIC16(L)F1705/9
10.2.2
FIGURE 10-3:
FLASH PROGRAM
MEMORY UNLOCK
SEQUENCE FLOWCHART
Start
Unlock Sequence
Write 055h to
PMCON2
Write 0AAh to
PMCON2
Initiate
Write or Erase operation
(WR = 1)
4. NOP instruction
5. NOP instruction
Once the WR bit is set, the processor will always force
two NOP instructions. When an Erase Row or Program
Row operation is being performed, the processor will stall
internal operations (typical 2 ms), until the operation is
complete and then resume with the next instruction.
When the operation is loading the program memory write
latches, the processor will always force the two NOP
instructions and continue uninterrupted with the next
instruction.
End
Unlock Sequence
DS40001729B-page 104
PIC16(L)F1705/9
10.2.3
FIGURE 10-4:
FLASH PROGRAM
MEMORY ERASE
FLOWCHART
Start
Erase Operation
Disable Interrupts
(GIE = 0)
Select
Program or Configuration Memory
(CFGS)
Unlock Sequence
Figure 10-3
(FIGURE
x-x)
Re-enable Interrupts
(GIE = 1)
End
Erase Operation
DS40001729B-page 105
PIC16(L)F1705/9
EXAMPLE 10-2:
Required
Sequence
BCF
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
BCF
BSF
BSF
INTCON,GIE
PMADRL
ADDRL,W
PMADRL
ADDRH,W
PMADRH
PMCON1,CFGS
PMCON1,FREE
PMCON1,WREN
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
NOP
55h
PMCON2
0AAh
PMCON2
PMCON1,WR
BCF
BSF
DS40001729B-page 106
PMCON1,WREN
INTCON,GIE
; Disable writes
; Enable interrupts
PIC16(L)F1705/9
10.2.4
1.
2.
3.
DS40001729B-page 107
0 7
5 4
PMADRH
-
r9
r8
r7
r6
r5
PMADRL
r4
r3
r2
r1
r0
c4
c3
c2
c1
5
-
PMDATH
PMDATL
c0
Rev. 10-000004A_A0
0
8
14
Program Memory Write Latches
10
14
PMADRL<4:0>
Write Latch #0
00h
14
CFGS = 0
PMADRH<6:0>:
PMADRL<7:5>
Row
Address
Decode
14
14
Write Latch #1
01h
14
14
14
14
Row
Addr
Addr
Addr
Addr
000h
0000h
0001h
001Eh
001Fh
001h
0020h
0021h
003Eh
003Fh
002h
0040h
0041h
005Eh
005Fh
3FEh
7FC0h
7FC1h
7FDEh
7FDFh
3FFh
7FE0h
7FE1h
7FFEh
7FFFh
400h
CFGS = 1
8000h - 8003h
8004h 8005h
8006h
8007h 8008h
8009h - 801Fh
USER ID 0 - 3
reserved
DEVICE ID
Dev / Rev
Configuration
Words
reserved
Configuration Memory
PIC16(L)F1705/9
DS40001729B-page 108
FIGURE 10-5:
PIC16(L)F1705/9
FIGURE 10-6:
Start
Write Operation
Disable Interrupts
(GIE = 0)
Select
Program or Config. Memory
(CFGS)
Enable Write/Erase
Operation (WREN = 1)
Last word to
write ?
Yes
No
Unlock Sequence
(Figure10-3
x-x)
Figure
Increment Address
(PMADRH:PMADRL++)
Unlock Sequence
(Figure10-3
x-x)
Figure
Disable
Write/Erase Operation
(WREN = 0)
Re-enable Interrupts
(GIE = 1)
End
Write Operation
DS40001729B-page 109
PIC16(L)F1705/9
EXAMPLE 10-3:
;
;
;
;
;
;
;
INTCON,GIE
PMADRH
ADDRH,W
PMADRH
ADDRL,W
PMADRL
LOW DATA_ADDR
FSR0L
HIGH DATA_ADDR
FSR0H
PMCON1,CFGS
PMCON1,WREN
PMCON1,LWLO
;
;
;
;
;
;
;
;
;
;
;
;
;
MOVIW
MOVWF
MOVIW
MOVWF
FSR0++
PMDATL
FSR0++
PMDATH
MOVF
XORLW
ANDLW
BTFSC
GOTO
PMADRL,W
0x1F
0x1F
STATUS,Z
START_WRITE
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
55h
PMCON2
0AAh
PMCON2
PMCON1,WR
;
;
;
;
;
;
;
;
PMADRL,F
LOOP
PMCON1,LWLO
55h
PMCON2
0AAh
PMCON2
PMCON1,WR
;
;
;
;
;
;
;
;
;
;
;
;
;
Required
Sequence
LOOP
NOP
INCF
GOTO
Required
Sequence
START_WRITE
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
NOP
BCF
BSF
DS40001729B-page 110
PMCON1,WREN
INTCON,GIE
PIC16(L)F1705/9
10.3
FIGURE 10-7:
FLASH PROGRAM
MEMORY MODIFY
FLOWCHART
Start
Modify Operation
Read Operation
(Figure10-1
x.x)
Figure
Modify Image
The words to be modified are
changed in the RAM image
Erase Operation
(Figure10-4
x.x)
Figure
Write Operation
use RAM image
(Figure10-6
x.x)
Figure
End
Modify Operation
DS40001729B-page 111
PIC16(L)F1705/9
10.4
TABLE 10-2:
Address
Function
Read Access
Write Access
8000h-8003h
8005h-8006h
8007h-8008h
User IDs
Device ID/Revision ID
Configuration Words 1 and 2
Yes
Yes
Yes
Yes
No
No
EXAMPLE 10-4:
* This code block will read 1 word of program memory at the memory address:
*
PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables;
*
PROG_DATA_HI, PROG_DATA_LO
BANKSEL
MOVLW
MOVWF
CLRF
PMADRL
PROG_ADDR_LO
PMADRL
PMADRH
BSF
BCF
BSF
NOP
NOP
BSF
PMCON1,CFGS
INTCON,GIE
PMCON1,RD
INTCON,GIE
;
;
;
;
;
;
MOVF
MOVWF
MOVF
MOVWF
PMDATL,W
PROG_DATA_LO
PMDATH,W
PROG_DATA_HI
;
;
;
;
DS40001729B-page 112
PIC16(L)F1705/9
10.5
Write/Verify
FIGURE 10-8:
FLASH PROGRAM
MEMORY VERIFY
FLOWCHART
Start
Verify Operation
Read Operation
(Figure
x.x)
Figure
10-1
PMDAT =
RAM image
?
Yes
No
No
Fail
Verify Operation
Last
Word ?
Yes
End
Verify Operation
DS40001729B-page 113
PIC16(L)F1705/9
10.6
REGISTER 10-1:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
PMDAT<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
REGISTER 10-2:
U-0
U-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
PMDAT<13:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
REGISTER 10-3:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PMADR<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
PMADR<7:0>: Specifies the Least Significant bits for program memory address
DS40001729B-page 114
PIC16(L)F1705/9
REGISTER 10-4:
U-1
R/W-0/0
R/W-0/0
R/W-0/0
(1)
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PMADR<14:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 1
bit 6-0
PMADR<14:8>: Specifies the Most Significant bits for program memory address
Note 1:
Unimplemented, read as 1.
DS40001729B-page 115
PIC16(L)F1705/9
REGISTER 10-5:
U-1
R/W-0/0
(1)
CFGS
R/W-0/0
LWLO
R/W/HC-0/0
R/W/HC-x/q(2)
R/W-0/0
R/S/HC-0/0
R/S/HC-0/0
FREE
WRERR
WREN
WR
RD
(3)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 1
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
3:
DS40001729B-page 116
PIC16(L)F1705/9
REGISTER 10-6:
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
TABLE 10-3:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
84
PMCON1
(1)
CFGS
LWLO
FREE
WRERR
WREN
WR
RD
116
PMCON2
117
PMADRL<7:0>
114
PMADRL
PMADRH
(1)
PMADRH<6:0>
PMDATL
115
PMDATL<7:0>
PMDATH
114
PMDATH<5:0>
114
Legend: = unimplemented location, read as 0. Shaded cells are not used by Flash program memory.
Note 1: Unimplemented, read as 1.
TABLE 10-4:
Name
CONFIG1
CONFIG2
Legend:
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
13:8
CLKOUTEN
7:0
CP
MCLRE
PWRTE
13:8
LVP
DEBUG
LPBOR
BORV
7:0
ZCDDIS
PPS1WAY
WDTE<1:0>
Bit 10/2
Bit 9/1
Bit 8/0
BOREN<1:0>
FOSC<1:0>
STVREN
PLLEN
WRT<1:0>
Register
on Page
48
50
= unimplemented location, read as 0. Shaded cells are not used by Flash program memory.
DS40001729B-page 117
PIC16(L)F1705/9
11.0
I/O PORTS
FIGURE 11-1:
D
Write LATx
Write PORTx
TRISx
CK
VDD
Data Register
Data Bus
I/O pin
Read PORTx
To digital peripherals
To analog peripherals
ANSELx
VSS
PIC16(L)F1705
PIC16(L)F1709
PORTC
Device
PORTB
TABLE 11-1:
Read LATx
DS40001729B-page 118
PIC16(L)F1705/9
11.1
11.1.1
PORTA Registers
DATA REGISTER
11.1.5
11.1.2
DIRECTION CONTROL
11.1.3
OPEN-DRAIN CONTROL
11.1.4
11.1.6
ANALOG CONTROL
EXAMPLE 11-1:
;
;
;
;
INITIALIZING PORTA
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
MOVLW
MOVWF
PORTA
PORTA
LATA
LATA
ANSELA
ANSELA
TRISA
B'00111000'
TRISA
;
;Init PORTA
;Data Latch
;
;
;digital I/O
;
;Set RA<5:3> as inputs
;and set RA<2:0> as
;outputs
DS40001729B-page 119
PIC16(L)F1705/9
11.1.7
DS40001729B-page 120
PIC16(L)F1705/9
11.2
REGISTER 11-1:
U-0
U-0
R/W-x/x
R/W-x/x
R-x/x
R/W-x/x
R/W-x/x
R/W-x/x
RA5
RA4
RA3
RA2
RA1
RA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
Note 1:
Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return
of actual I/O pin values.
REGISTER 11-2:
U-0
U-0
R/W-1/1
R/W-1/1
U-1
R/W-1/1
R/W-1/1
R/W-1/1
TRISA5
TRISA4
(1)
TRISA2
TRISA1
TRISA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-4
bit 3
Unimplemented: Read as 1
bit 2-0
Note 1:
Unimplemented, read as 1.
DS40001729B-page 121
PIC16(L)F1705/9
REGISTER 11-3:
U-0
U-0
R/W-x/u
R/W-x/u
U-0
R/W-x/u
R/W-x/u
R/W-x/u
LATA5
LATA4
LATA2
LATA1
LATA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-4
bit 3
Unimplemented: Read as 0
bit 2-0
Note 1:
Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return
of actual I/O pin values.
REGISTER 11-4:
U-0
U-0
U-0
R/W-1/1
U-0
R/W-1/1
R/W-1/1
R/W-1/1
ANSA4
ANSA2
ANSA1
ANSA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-5
Unimplemented: Read as 0
bit 4
bit 3
Unimplemented: Read as 0
bit 2-0
ANSA<2:0>: Analog Select between Analog or Digital Function on pins RA<2:0>, respectively
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
0 = Digital I/O. Pin is assigned to port or digital special function.
Note 1:
When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
DS40001729B-page 122
PIC16(L)F1705/9
REGISTER 11-5:
U-0
U-0
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
WPUA5
WPUA4
WPUA3
WPUA2
WPUA1
WPUA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
Note 1:
2:
Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
The weak pull-up device is automatically disabled if the pin is configured as an output.
REGISTER 11-6:
U-0
U-0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
ODA5
ODA4
ODA2
ODA1
ODA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-4
bit 3
Unimplemented: Read as 0
bit 2-0
DS40001729B-page 123
PIC16(L)F1705/9
REGISTER 11-7:
U-0
U-0
R/W-1/1
R/W-1/1
U-0
R/W-1/1
R/W-1/1
R/W-1/1
SLRA5
SLRA4
SLRA2
SLRA1
SLRA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-4
bit 3
Unimplemented: Read as 0
bit 2-0
REGISTER 11-8:
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
INLVLA5
INLVLA4
INLVLA3
INLVLA2
INLVLA1
INLVLA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
DS40001729B-page 124
PIC16(L)F1705/9
TABLE 11-2:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSELA
ANSA4
ANSA2
ANSA1
ANSA0
122
INLVLA
INLVLA5
INLVLA4
INLVLA3
INLVLA2
INLVLA1
INLVLA0
124
LATA
LATA5
LATA4
LATA2
LATA1
LATA0
122
ODA5
ODA4
ODA2
ODA1
ODA0
123
Name
WPUEN
INTEDG
PORTA
RA5
RA4
RA3
RA2
RA1
RA0
121
SLRCONA
SLRA5
SLRA4
SLRA2
SLRA1
SLRA0
124
ODCONA
OPTION_REG
TMR0CS TMR0SE
TRISA
TRISA5
TRISA4
WPUA
WPUA5
WPUA4
PSA
(1)
WPUA3
PS<2:0>
245
TRISA2
TRISA1
TRISA0
121
WPUA2
WPUA1
WPUA0
123
Legend: x = unknown, u = unchanged, = unimplemented locations read as 0. Shaded cells are not used by
PORTA.
Note 1: Unimplemented, read as 1.
TABLE 11-3:
Name
CONFIG1
Legend:
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
13:8
FCMEN
IESO
CLKOUTEN
7:0
CP
MCLRE
PWRTE
Bit 10/2
Bit 9/1
Bit 8/0
BOREN<1:0>
WDTE<1:0>
FOSC<2:0>
Register
on Page
48
DS40001729B-page 125
PIC16(L)F1705/9
11.3
PORTB Registers
(PIC16(L)F1709 only)
11.3.4
11.3.1
DIRECTION CONTROL
11.3.2
OPEN-DRAIN CONTROL
11.3.3
11.3.5
DS40001729B-page 126
ANALOG CONTROL
11.3.6
PIC16(L)F1705/9
11.4
REGISTER 11-9:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
U-0
U-0
U-0
U-0
RB7
RB6
RB5
RB4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
bit 3-0
Unimplemented: Read as 0
Note 1:
Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is
return of actual I/O pin values.
R/W-1/1
R/W-1/1
R/W-1/1
U-0
U-0
U-0
U-0
TRISB7
TRISB6
TRISB5
TRISB4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
bit 3-0
Unimplemented: Read as 0
DS40001729B-page 127
PIC16(L)F1705/9
REGISTER 11-11: LATB: PORTB DATA LATCH REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
U-0
U-0
U-0
U-0
LATB7
LATB6
LATB5
LATB4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
bit 3-0
Unimplemented: Read as 0
Note 1:
Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is
return of actual I/O pin values.
U-0
R/W-1/1
R/W-1/1
U-0
U-0
U-0
U-0
ANSB5
ANSB4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-4
ANSB<5:4>: Analog Select between Analog or Digital Function on pins RB<5:4>, respectively
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
bit 3-0
Unimplemented: Read as 0
Note 1:
When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
DS40001729B-page 128
PIC16(L)F1705/9
REGISTER 11-13: WPUB: WEAK PULL-UP PORTB REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
U-0
U-0
U-0
U-0
WPUB7
WPUB6
WPUB5
WPUB4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
bit 3-0
Unimplemented: Read as 0
Note 1:
2:
Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
The weak pull-up device is automatically disabled if the pin is configured as an output.
R/W-0/0
R/W-0/0
R/W-0/0
U-0
U-0
U-0
U-0
ODB7
ODB6
ODB5
ODB4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
bit 3-0
Unimplemented: Read as 0
DS40001729B-page 129
PIC16(L)F1705/9
REGISTER 11-15: SLRCONB: PORTB SLEW RATE CONTROL REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
U-0
U-0
U-0
U-0
SLRB7
SLRB6
SLRB5
SLRB4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
bit 3-0
Unimplemented: Read as 0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
U-0
U-0
U-0
INLVLB7
INLVLB6
INLVLB5
INLVLB4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
bit 3-0
Unimplemented: Read as 0
TABLE 11-4:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSB5
ANSB4
128
INLVLB7
INLVLB6
INLVLB5
INLVLB4
130
LATB
LATB7
LATB6
LATB5
LATB4
128
ODCONB
ODB7
ODB6
ODB5
ODB4
129
RB7
RB6
RB5
RB4
127
SLRB7
SLRB6
SLRB5
SLRB4
130
Name
ANSELB
INLVLB
PORTB
SLRCONB
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
130
WPUB
WPUB7
WPUB6
WPUB5
WPUB4
129
Legend:
x = unknown, u = unchanged, - = unimplemented locations read as 0. Shaded cells are not used by
PORTB.
DS40001729B-page 130
PIC16(L)F1705/9
11.5
11.5.1
PORTC Registers
DATA REGISTER
11.5.2
DIRECTION CONTROL
11.5.3
11.5.4
OPEN-DRAIN CONTROL
11.5.5
11.5.6
ANALOG CONTROL
11.5.7
DS40001729B-page 131
PIC16(L)F1705/9
11.6
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
RC7(2)
RC6(2)
RC5
RC4
RC3
RC2
RC1
RC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
RC<7:0>: PORTC General Purpose I/O Pin bits(1, 2)
1 = Port pin is > VIH
0 = Port pin is < VIL
bit 7-0
Note 1:
2:
Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is
return of actual I/O pin values.
RC<7:6> are available on PIC16(L)F1709 only.
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
TRISC7(1)
TRISC6(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
Note 1:
DS40001729B-page 132
PIC16(L)F1705/9
REGISTER 11-19: LATC: PORTC DATA LATCH REGISTER
R/W-x/u
R/W-x/u
(1)
(1)
LATC7
LATC6
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
LATC<7:0>: PORTC Output Latch Value bits(1)
bit 7-0
Note 1:
R/W-1/1
U-0
U-0
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
ANSC7(2)
ANSC6(2)
ANSC5(3)
ANSC4(3)
ANSC3
ANSC2
ANSC1
ANSC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
ANSC<7:0>: Analog Select between Analog or Digital Function on pins RC<7:0>, respectively(1)
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
bit 7-0
Note 1:
2:
3:
When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
ANSC<7:6> are available on PIC16(L)F1709 only.
ANSC<5:4> are available on PIC16(L)F1705 only.
DS40001729B-page 133
PIC16(L)F1705/9
REGISTER 11-21: WPUC: WEAK PULL-UP PORTC REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
WPUC7(3)
WPUC6(3)
WPUC5
WPUC4
WPUC3
WPUC2
WPUC1
WPUC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
WPUC<7:0>: Weak Pull-up Register bits(1),(2)
1 = Pull-up enabled
0 = Pull-up disabled
bit 7-0
Note 1:
2:
3:
Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
The weak pull-up device is automatically disabled if the pin is configured as an output.
WPUC<7:6> are available on PIC16(L)F1709 only.
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
ODC7(1)
ODC6(1)
ODC5
ODC4
ODC3
ODC2
ODC1
ODC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
Note 1:
DS40001729B-page 134
PIC16(L)F1705/9
REGISTER 11-23: SLRCONC: PORTC SLEW RATE CONTROL REGISTER
R/W-1/1
SLRC7
R/W-1/1
(1)
SLRC6
(1)
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
SLRC5
SLRC4
SLRC3
SLRC2
SLRC1
SLRC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
SLRC<7:0>: PORTC Slew Rate Enable bits(1)
For RC<7:0> pins, respectively
1 = Port pin slew rate is limited
0 = Port pin slews at maximum rate
bit 7-0
Note 1:
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
INLVLC7(1)
INLVLC6(1)
INLVLC5
INLVLC4
INLVLC3
INLVLC2
INLVLC1
INLVLC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
Note 1:
DS40001729B-page 135
PIC16(L)F1705/9
TABLE 11-5:
Name
ANSELC
ANSC6(1)
LATC7
(1)
SLRCONC
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSC5(2) ANSC4(2)
ANSC3
ANSC2
ANSC1
ANSC0
133
INLVLC1 INLVLC0
135
Bit 5
(1)
INLVLC6
Bit 4
INLVLC5
INLVLC4
INLVLC3
INLVLC2
(1)
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0
(1)
LATC6
ODC5
ODC4
ODC3
ODC2
ODC1
ODC0
134
RC6(1)
RC5
RC4
RC3
RC2
RC1
RC0
132
SLRC7(1)
SLRC6(1)
SLRC5
SLRC4
SLRC3
SLRC2
SLRC1
SLRC0
135
(1)
(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
132
(1)
WPUC5
WPUC4
WPUC3
WPUC2
WPUC1
WPUC0
134
TRISC7
(1)
WPUC7
ODC6
133
RC7(1)
ODC7
PORTC
Note 1:
2:
ANSC7(1)
(1)
ODCONC
Legend:
Bit 6
INLVLC7
LATC
WPUC
Bit 7
(1)
INLVLC
TRISC
TRISC6
WPUC6
x = unknown, u = unchanged, - = unimplemented locations read as 0. Shaded cells are not used by
PORTC.
PIC16(L)F1709 only.
PIC16(L)F1705 only.
DS40001729B-page 136
PIC16(L)F1705/9
12.0
12.1
PPS Inputs
Although every peripheral has its own PPS input selection register, the selections are identical for every
peripheral
as
shown
in
Register 12-1
for
PIC16(L)F1705 devices and Register 12-2 for
PIC16(L)F1709 devices.
Note:
12.2
PPS Outputs
Each I/O pin has a PPS register with which the pin
output source is selected. With few exceptions, the port
TRIS control associated with that pin retains control
over the pin output driver. Peripherals that control the
pin output driver as part of the peripheral operation will
override the TRIS control as needed. These
peripherals include:
EUSART (synchronous operation)
MSSP (I2C)
COG (auto-shutdown)
Although every pin has its own PPS peripheral
selection register, the selections are identical for every
pin as shown in Register 12-3.
Note:
FIGURE 12-1:
PPS Inputs
abcPPS
RA0
RA0
Peripheral abc
RxyPPS
Rxy
Peripheral xyz
RC7
xyzPPS
RC7PPS
RC7
DS40001729B-page 137
PIC16(L)F1705/9
12.3
Bidirectional Pins
Note:
12.4
12.6
PPS Lock
EXAMPLE 12-1:
12.5
12.7
Effects of a Reset
PPS LOCK/UNLOCK
SEQUENCE
; suspend interrupts
bcf
INTCON,GIE
;
BANKSEL PPSLOCK
; set bank
; required sequence, next 5 instructions
movlw
0x55
movwf
PPSLOCK
movlw
0xAA
movwf
PPSLOCK
; Set PPSLOCKED bit to disable writes or
; Clear PPSLOCKED bit to enable writes
bsf
PPSLOCK,PPSLOCKED
; restore interrupts
bsf
INTCON,GIE
DS40001729B-page 138
PIC16(L)F1705/9
12.8
REGISTER 12-1:
U-0
U-0
U-0
R/W-q/u
R/W-q/u
R/W-q/u
R/W-q/u
R/W-q/u
xxxPPS<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-5
Unimplemented: Read as 0
bit 4-0
DS40001729B-page 139
PIC16(L)F1705/9
REGISTER 12-2:
U-0
U-0
U-0
R/W-q/u
R/W-q/u
R/W-q/u
R/W-q/u
R/W-q/u
xxxPPS<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-5
Unimplemented: Read as 0
bit 4-0
DS40001729B-page 140
PIC16(L)F1705/9
REGISTER 12-3:
U-0
U-0
U-0
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
RxyPPS<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-5
Unimplemented: Read as 0
bit 4-0
Note 1:
DS40001729B-page 141
PIC16(L)F1705/9
REGISTER 12-4:
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0/0
PPSLOCKED
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-1
Unimplemented: Read as 0
bit 0
DS40001729B-page 142
PIC16(L)F1705/9
TABLE 12-1:
Name
Bit 1
Bit 0
Register
on page
PPSLOCKED
142
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
PPSLOCK
INTPPS
INTPPS<4:0>
140
T0CKIPPS
T0CKIPPS<4:0>
140
T1CKIPPS
T1CKIPPS<4:0>
140
T1GPPS
T1GPPS<4:0>
140
CCP1PPS
CCP1PPS<4:0>
140
CCP2PPS
CCP2PPS<4:0>
140
COGPPS
COGPPS<4:0>
140
SSPCLKPPS
SSPCLKPPS<4:0>
140
SSPDATPPS
SSPDATPPS<4:0>
140
SSPSSPPS
SSPSSPPS<4:0>
140
RXPPS
RXPPS<4:0>
140
CKPPS
CKPPS<4:0>
140
CLCIN0PPS
CLCIN0PPS<4:0>
140
CLCIN1PPS
CLCIN1PPS<4:0>
140
CLCIN2PPS
CLCIN2PPS<4:0>
140
CLCIN3PPS
CLCIN3PPS<4:0>
140
RA0PPS
RA0PPS<4:0>
141
RA1PPS
RA1PPS<4:0>
141
RA2PPS
RA2PPS<4:0>
141
RA4PPS
RA4PPS<4:0>
141
RA5PPS
RA5PPS<4:0>
141
RB4PPS(1)
RB4PPS<4:0>
141
RB5PPS(1)
RB5PPS<4:0>
141
RB6PPS(1)
RB6PPS<4:0>
141
(1)
RB7PPS
RB7PPS<4:0>
141
RC0PPS
RC0PPS<4:0>
141
RC1PPS
RC1PPS<4:0>
141
RC2PPS
RC2PPS<4:0>
141
RC3PPS
RC3PPS<4:0>
141
RC4PPS
RC4PPS<4:0>
141
RC5PPS
RC5PPS<4:0>
141
RC6PPS(1)
RC6PPS<4:0>
141
RC7PPS(1)
RC7PPS<4:0>
141
Legend:
Note 1:
DS40001729B-page 143
PIC16(L)F1705/9
13.0
INTERRUPT-ON-CHANGE
13.1
13.3
Interrupt Flags
13.4
13.2
EXAMPLE 13-1:
MOVLW
XORWF
ANDWF
13.5
CLEARING INTERRUPT
FLAGS
(PORTA EXAMPLE)
0xff
IOCAF, W
IOCAF, F
Operation in Sleep
DS40001729B-page 144
PIC16(L)F1705/9
FIGURE 13-1:
IOCANx
Q4Q1
edge
detect
RAx
IOCAPx
data bus =
0 or 1
to data bus
IOCAFx
write IOCAFx
IOCIE
Q2
IOC interrupt
to CPU core
from all other
IOCnFx individual
pin detectors
FOSC
Q1
Q1
Q1
Q3
Q3
Q4
Q4Q1
Q2
Q2
Q2
Q3
Q4
Q4Q1
Q4
Q4Q1
Q4Q1
DS40001729B-page 145
PIC16(L)F1705/9
13.6
REGISTER 13-1:
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
IOCAP5
IOCAP4
IOCAP3
IOCAP2
IOCAP1
IOCAP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
REGISTER 13-2:
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
IOCAN5
IOCAN4
IOCAN3
IOCAN2
IOCAN1
IOCAN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
DS40001729B-page 146
PIC16(L)F1705/9
REGISTER 13-3:
U-0
U-0
IOCAF4
IOCAF3
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
IOCAF2
IOCAF1
IOCAF0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
REGISTER 13-4:
R/W-0/0
R/W-0/0
IOCBP7
R/W-0/0
IOCBP6
IOCBP5
R/W-0/0
U-0
U-0
U-0
U-0
IOCBP4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
bit 3-0
Unimplemented: Read as 0
Note 1:
PIC16(L)F1709 only.
DS40001729B-page 147
PIC16(L)F1705/9
REGISTER 13-5:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
U-0
U-0
U-0
IOCBN7
IOCBN6
IOCBN5
IOCBN4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
bit 3-0
Unimplemented: Read as 0
Note 1:
PIC16(L)F1709 only.
REGISTER 13-6:
R/W/HS-0/0
R/W/HS-0/0
IOCBF7
IOCBF6
R/W/HS-0/0 R/W/HS-0/0
IOCBF5
IOCBF4
U-0
U-0
U-0
U-0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
bit 3-0
Unimplemented: Read as 0
Note 1:
PIC16(L)F1709 only.
DS40001729B-page 148
PIC16(L)F1705/9
REGISTER 13-7:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
IOCCP7(1)
IOCCP6(1)
IOCCP5
IOCCP4
IOCCP3
IOCCP2
IOCCP1
IOCCP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
Note 1:
REGISTER 13-8:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
IOCCN7(1)
IOCCN6(1)
IOCCN5
IOCCN4
IOCCN3
IOCCN2
IOCCN1
IOCCN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
Note 1:
REGISTER 13-9:
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
IOCCF7(1)
IOCCF6(1)
IOCCF5
IOCCF4
IOCCF3
IOCCF2
IOCCF1
IOCCF0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
Note 1:
PIC16(L)F1709 only.
DS40001729B-page 149
PIC16(L)F1705/9
TABLE 13-1:
Name
ANSELA
(1)
ANSELB
ANSELC
INTCON
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSA4
ANSA2
ANSA1
ANSA0
122
ANSB4
128
ANSC3
ANSC2
ANSC1
ANSC0
133
(1)
ANSC7
ANSB5
(1)
ANSC6
(2)
ANSC5
(2)
ANSC4
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
84
IOCAF
IOCAF5
IOCAF4
IOCAF3
IOCAF2
IOCAF1
IOCAF0
147
IOCAN
IOCAN5
IOCAN4
IOCAN3
IOCAN2
IOCAN1
IOCAN0
146
IOCAP
IOCAP5
IOCAP4
IOCAP3
IOCAP2
IOCAP1
IOCAP0
146
(1)
IOCBF
IOCBF7
IOCBF6
IOCBF5
IOCBF4
148
IOCBN(1)
IOCBN7
IOCBN6
IOCBN5
IOCBN4
148
IOCBP(1)
IOCBP7
IOCBP6
IOCBP5
IOCBP4
147
(1)
IOCCF6(1)
IOCCF5
IOCCF4
IOCCF3
IOCCF2
IOCCF1
IOCCF0
149
IOCCN
(1)
IOCCN7
IOCCN6(1)
IOCCN5
IOCCN4
IOCCN3
IOCCN2
IOCCN1
IOCCN0
149
IOCCP
IOCCP7(1) IOCCP6(1)
IOCCP5
IOCCP4
IOCCP3
IOCCP2
IOCCP1
IOCCP0
149
TRISA5
TRISA4
(3)
TRISA2
TRISA1
TRISA0
121
TRISB6
TRISB5
TRISB4
127
TRISC6(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
132
IOCCF
TRISA
(1)
TRISB
TRISC
Legend:
Note 1:
2:
3:
IOCCF7
TRISB7
TRISC7
(1)
DS40001729B-page 150
PIC16(L)F1705/9
14.0
14.1
14.2
14.3
DS40001729B-page 151
PIC16(L)F1705/9
FIGURE 14-1:
CDAFVR<1:0>
2
X1
X2
X4
FVR BUFFER1
(To ADC Module)
X1
X2
X4
FVR BUFFER2
(To Comparators, DAC)
HFINTOSC Enable
HFINTOSC
To BOR, LDO
FVREN
+
_
FVRRDY
TABLE 14-1:
Peripheral
HFINTOSC
Conditions
Description
BOREN<1:0> = 11
BOR
LDO
The device runs off of the ULP regulator when in Sleep mode
DS40001729B-page 152
PIC16(L)F1705/9
14.4
REGISTER 14-1:
R/W-0/0
R-q/q
FVREN
FVRRDY(1)
R/W-0/0
TSEN
(3)
R/W-0/0
TSRNG
R/W-0/0
(3)
R/W-0/0
R/W-0/0
CDAFVR<1:0>
R/W-0/0
ADFVR<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3-2
bit 1-0
Note 1:
2:
3:
TABLE 14-2:
Name
FVRCON
Legend:
Bit 6
Bit 5
Bit 4
FVREN
FVRRDY
TSEN
TSRNG
Bit 3
Bit 2
CDAFVR<1:0>
Bit 1
Bit 0
ADFVR<1:0>
Register
on page
153
Shaded cells are not used with the Fixed Voltage Reference.
DS40001729B-page 153
PIC16(L)F1705/9
15.0
TEMPERATURE INDICATOR
MODULE
FIGURE 15-1:
VDD
TSEN
TSRNG
15.1
Circuit Operation
EQUATION 15-1:
VOUT RANGES
TEMPERATURE CIRCUIT
DIAGRAM
VOUT
Temp. Indicator
15.2
To ADC
TABLE 15-1:
Low Range: VOUT = VDD - 2VT
3.6V
1.8V
15.3
Temperature Output
DS40001729B-page 154
PIC16(L)F1705/9
15.4
TABLE 15-2:
Name
FVRCON
Bit 6
Bit 5
Bit 4
FVREN
FVRRDY
TSEN
TSRNG
Bit 3
Bit 2
CDFVR<1:0>
Bit 1
Bit 0
ADFVR<1:0>
Register
on page
153
DS40001729B-page 155
PIC16(L)F1705/9
16.0
COMPARATOR MODULE
FIGURE 16-1:
16.1
Comparator Overview
SINGLE COMPARATOR
VIN+
VIN-
Output
VINVIN+
Output
Note:
TABLE 16-1:
AVAILABLE COMPARATORS
Device
PIC16(L)F1705/9
DS40001729B-page 156
C1
C2
PIC16(L)F1705/9
FIGURE 16-2:
CxNCH<2:0>
CxON(1)
CxINTP
Interrupt
det
CXIN0-
CXIN1-
CXIN2-
2 MUX
Set CxIF
CXIN3-
det
Reserved
Reserved
FVR Buffer2
CxINTN
Interrupt
(2)
CXPOL
CxVN
Cx
CxVP
ZLF
EN
Q1
7
CxHYS
AGND
CxSP
to CMXCON0 (CXOUT)
and CM2CON1 (MCXOUT)
CxZLF
async_CxOUT
CXSYNC
TRIS bit
CXOUT
CXIN+
Reserved
Reserved
Reserved
Reserved
DAC_Output
FVR Buffer2
D
From Timer1
tmr1_clk
MUX
sync_CxOUT
To Timer1
(2)
7
AGND
CxON
CXPCH<2:0>
3
Note 1:
2:
DS40001729B-page 157
PIC16(L)F1705/9
16.2
Comparator Control
Enable
Output
Output polarity
Zero latency filter
Speed/Power selection
Hysteresis enable
Output synchronization
Interrupt enable
Interrupt edge polarity
Positive input channel selection
Negative input channel selection
16.2.1
COMPARATOR ENABLE
16.2.2
COMPARATOR OUTPUT
SELECTION
16.2.3
TABLE 16-2:
COMPARATOR OUTPUT
STATE VS. INPUT
CONDITIONS
Input Condition
CxPOL
CxOUT
16.2.4
COMPARATOR SPEED/POWER
SELECTION
DS40001729B-page 158
PIC16(L)F1705/9
16.3
Comparator Hysteresis
16.4
16.4.1
COMPARATOR OUTPUT
SYNCHRONIZATION
16.5
Comparator Interrupt
16.6
16.7
Note:
DS40001729B-page 159
PIC16(L)F1705/9
16.8
16.9
FIGURE 16-3:
TZLF
DS40001729B-page 160
PIC16(L)F1705/9
16.10 Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 16-4. Since the analog input pins share their
connection with a digital input, they have reverse
biased ESD protection diodes to VDD and VSS. The
analog input, therefore, must be between VSS and VDD.
If the input voltage deviates from this range by more
than 0.6V in either direction, one of the diodes is
forward biased and a latch-up may occur.
A maximum source impedance of 10 k is recommended
for the analog sources. Also, any external component
connected to an analog input pin, such as a capacitor or
a Zener diode, should have very little leakage current to
minimize inaccuracies introduced.
Note 1: When reading a PORT register, all pins
configured as analog inputs will read as a
0. Pins configured as digital inputs will
convert as an analog input, according to
the input specification.
2: Analog levels on any pin defined as a
digital input, may cause the input buffer to
consume more current than is specified.
FIGURE 16-4:
Rs < 10K
Analog
Input
pin
VT 0.6V
RIC
To Comparator
VA
CPIN
5 pF
VT 0.6V
ILEAKAGE(1)
Vss
Legend: CPIN
= Input Capacitance
ILEAKAGE = Leakage Current at the pin due to various junctions
RIC
= Interconnect Resistance
= Source Impedance
RS
= Analog Voltage
VA
VT
= Threshold Voltage
Note 1: See I/O Ports in Table 32-4: I/O Ports.
DS40001729B-page 161
PIC16(L)F1705/9
16.11 Register Definitions: Comparator Control
REGISTER 16-1:
R/W-0/0
R-0/0
U-0
R/W-0/0
R/W-0/0
R/W-1/1
R/W-0/0
R/W-0/0
CxON
CxOUT
CxPOL
CxZLF
CxSP
CxHYS
CxSYNC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
bit 1
bit 0
DS40001729B-page 162
PIC16(L)F1705/9
REGISTER 16-2:
R/W-0/0
R/W-0/0
CxINTP
CxINTN
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
CxPCH<2:0>
R/W-0/0
R/W-0/0
CxNCH<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5-3
bit 2-0
DS40001729B-page 163
PIC16(L)F1705/9
REGISTER 16-3:
U-0
U-0
U-0
U-0
U-0
U-0
R-0/0
R-0/0
MC2OUT
MC1OUT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-2
Unimplemented: Read as 0
bit 1
bit 0
TABLE 16-3:
Name
ANSELA
ANSELB(1)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSA4
ANSA2
ANSA1
ANSA0
122
ANSB5
ANSB4
128
ANSC7(1)
ANSC6(1)
ANSC5(2)
ANSC4(2)
ANSC3
ANSC2
ANSC1
ANSC0
133
CM1CON0
C1ON
C1OUT
C1POL
C1ZLF
C1SP
C1HYS
C1SYNC
162
CM2CON0
C2ON
C2OUT
C2POL
C2ZLF
C2SP
C2HYS
C2SYNC
162
CM1CON1
C1INTP
C1INTN
C1PCH<2:0>
C1NCH<2:0>
CM2CON1
C2INTP
C2INTN
C2PCH<2:0>
C2NCH<2:0>
CMOUT
FVRCON
FVREN
FVRRDY
TSEN
TSRNG
CDAFVR<1:0>
DAC1EN
DAC1OE1
DAC1OE2
DAC1PSS<1:0>
ANSELC
DAC1CON0
DAC1CON1
MC2OUT
163
163
MC1OUT
ADFVR<1:0>
DAC1NSS
DAC1R<7:0>
164
153
238
238
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
84
PIE2
OSFIE
C2IE
C1IE
BCL1IE
TMR6IE
TMR4IE
CCP2IE
86
PIR2
OSFIF
C2IF
C1IF
BCL1IF
TMR6IF
TMR4IF
CCP2IF
89
TRISA5
TRISA4
(3)
TRISA2
TRISA1
TRISA0
121
INTCON
TRISA
TRISB(1)
TRISC
Legend:
Note 1:
2:
3:
TRISB7
TRISB6
TRISB5
TRISB4
127
TRISC7(1)
TRISC6(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
132
= unimplemented location, read as 0. Shaded cells are unused by the comparator module.
PIC16(L)F1709 only.
PIC16(L)F1705 only.
Unimplemented, read as 1.
DS40001729B-page 164
PIC16(L)F1705/9
17.0
PULSE-WIDTH MODULATION
(PWM)
PR2
T2CON
PWMxDCH
PWMxDCL
PWMxCON
FIGURE 17-1:
PWMxDCL<7:6>
PWMxDCH
Latched
(Not visible to user)
Comparator
PWMxOUT
to other peripherals: CLC and CWG
PWMx
TMR2 Module
TMR2
(1)
Comparator
PR2
Note
1:
Clear Timer,
PWMx pin and
latch Duty Cycle
8-bit timer is concatenated with the two Least Significant bits of 1/FOSC adjusted by the Timer2 prescaler to
create a 10-bit time base.
FIGURE 17-2:
PWM OUTPUT
Period
Pulse Width
TMR2 = 0
TMR2 = PR2
TMR2 =
PWMxDCH<7:0>:PWMxDCL<7:6>
DS40001729B-page 165
PIC16(L)F1705/9
17.1
FUNDAMENTAL OPERATION
17.1.3
PWM PERIOD
EQUATION 17-1:
PWM PERIOD
17.1.4
EQUATION 17-2:
PULSE WIDTH
EQUATION 17-3:
PWMxDCH:PWMxDCL<7:6>
Duty Cycle Ratio = ----------------------------------------------------------------------------------4 PR2 + 1
TOSC = 1/FOSC
DS40001729B-page 166
PIC16(L)F1705/9
17.1.5
PWM RESOLUTION
EQUATION 17-4:
PWM RESOLUTION
log 4 PR2 + 1
Resolution = ------------------------------------------ bits
log 2
Note:
TABLE 17-1:
PWM Frequency
0.31 kHz
Timer Prescale
PR2 Value
78.12 kHz
156.3 kHz
208.3 kHz
64
0xFF
0xFF
0x3F
0x1F
0x17
10
10
10
6.6
PWM Frequency
0.31 kHz
Timer Prescale
PR2 Value
4.90 kHz
19.61 kHz
76.92 kHz
153.85 kHz
200.0 kHz
64
0x65
0x65
0x65
0x19
0x0C
0x09
17.1.6
19.53 kHz
0xFF
TABLE 17-2:
4.88 kHz
17.1.7
17.1.8
EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
PWM registers to their Reset states.
DS40001729B-page 167
PIC16(L)F1705/9
17.1.9
17.1.10
5.
6.
7.
Note:
DS40001729B-page 168
PIC16(L)F1705/9
17.2
REGISTER 17-1:
R/W-0/0
U-0
R-0/0
R/W-0/0
U-0
U-0
U-0
U-0
PWMxEN
PWMxOUT
PWMxPOL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
Unimplemented: Read as 0
bit 5
bit 4
bit 3-0
Unimplemented: Read as 0
DS40001729B-page 169
PIC16(L)F1705/9
REGISTER 17-2:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
PWMxDCH<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
REGISTER 17-3:
R/W-x/u
R/W-x/u
PWMxDCL<7:6>
U-0
U-0
U-0
U-0
U-0
U-0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-0
Unimplemented: Read as 0
TABLE 17-3:
Name
CCPTMRS
Bit 6
P4TSEL<1:0>
Bit 5
P3TSEL<1:0>
PR2
PWM3CON
PWM4CON
Bit 3
Bit 2
Bit 1
C2TSEL<1:0>
Bit 0
Register
on Page
C1TSEL<1:0>
PWM3OUT PWM3POL
PWM3DCH
PWM3DCL
Bit 4
PWMxDCH<7:0>
PWMxDCL<7:6>
PWM4EN
PWM4OUT PWM4POL
PWM4DCH
PWMxDCL<7:6>
RxyPPS
T2CON
TMR2
169
170
170
169
PWMxDCH<7:0>
PWM4DCL
261
257
170
RxyPPS<4:0>
TMR2ON
170
141
T2CKPS1
T2CKPS0
259
257
Legend: - = Unimplemented locations, read as 0, u = unchanged, x = unknown. Shaded cells are not used by the PWM.
DS40001729B-page 170
PIC16(L)F1705/9
18.0
COMPLEMENTARY OUTPUT
GENERATOR (COG) MODULE
18.1
18.1.1
Fundamental Operation
STEERING (ALL MODES)
18.1.2
18.1.3
FULL-BRIDGE MODES
DS40001729B-page 171
V+
FET
Driver
QC
QA
FET
Driver
COGxA
Load
COGxB
FET
Driver
COGxC
FET
Driver
QD
QB
VCOGxD
PIC16(L)F1705/9
DS40001729B-page 172
FIGURE 18-1:
PIC16(L)F1705/9
18.1.4
HALF-BRIDGE MODE
18.1.5
PUSH-PULL MODE
18.1.6
DS40001729B-page 173
reserved
HFINTOSC
11
10
Fosc
Fosc/4
01
00
unimplemented
PWM3OUT
CCP2
CCP1
CLC1OUT
C2OUT
C1OUT
COGINPPS
COG_clock
1
0
src7
src6
src5
src4
src3
src2
src1
src0
src7
src6
src5
src4
src3
src2
src1
src0
GxSDATA
GxSTRA
GxASDBD<1:0>
clock
1
0
High-Z
Reset Dominates
rising_event
S Q
count_en
GxPOLB
GxSDATB
COGxB
0
GxASDAC<1:0>
GxSTRB
1
0
High-Z
clock
11
10
01
00
1
falling_event
COGxC
count_en
GxPOLC
GxSDATC
0
0
GxASDBD<1:0>
1
0
High-Z
GxEN
1
0
GxSTRC
COGINPPS
GxAS0E
C1OUT
GxAS1E
C2OUT
GxAS2E
CLC2OUT
GxAS3E
11
10
01
00
R Q
COGxA
1
GxPOLA
GxCS<1:0>
11
10
01
00
11
10
01
00
COGxD
1
GxPOLD
Auto-shutdown source
GxSDATD
0
0
GxSTRD
GxASE
S Q
GxARSEN
Write GxASE Low
R
Set Dominates
S
D Q
PIC16(L)F1705/9
DS40001729B-page 174
FIGURE 18-2:
FIGURE 18-3:
reserved
HFINTOSC
11
10
Fosc
Fosc/4
01
00
GxCS<1:0>
unimplemented
PWM3OUT
CCP2
CCP1
CLC1OUT
C2OUT
C1OUT
COGINPPS
COG_clock
1
0
GxPOLA
GxSTRA
src7
src6
src5
src4
src3
src2
src1
src0
GxSDATA
D Q
GxASDBD<1:0>
clock
1
0
High-Z
Reset Dominates
rising_event
S Q
count_en
GxPOLB
GxSTRB
GxSDATB
COGxB
0
0
D Q
GxASDAC<1:0>
1
0
High-Z
clock
11
10
01
00
1
falling_event
COGxC
count_en
GxPOLC
GxSDATC
0
0
D Q
GxASDBD<1:0>
11
10
01
00
COGxD
1
GxPOLD
GxSTRD
Auto-shutdown source
GxSDATD
0
0
D Q
DS40001729B-page 175
GxASE
S Q
GxARSEN
Write GxASE Low
R
Set Dominates
S
D Q
PIC16(L)F1705/9
1
0
High-Z
GxEN
11
10
01
00
R Q
GxSTRC
COGINPPS
GxAS0E
C1OUT
GxAS1E
C2OUT
GxAS2E
CLC2OUT
GxAS3E
COGxA
11
10
01
00
SIMPLIFIED COG BLOCK DIAGRAM (FULL-BRIDGE MODES, FORWARD: GXMD = 2, REVERSE: GXMD = 3)
GxASDAC<1:0>
1
0
High-Z
reserved
HFINTOSC
11
10
Fosc
Fosc/4
01
00
COG_clock
clock
clock
Reset Dominates
rising_event
GxASDBD<1:0>
GxPOLA
signal_out
signal_in
1
0
High-Z
S Q
11
10
01
00
R Q
GxPOLB
src7
src6
src5
src4
src3
src2
src1
src0
signal_out
signal_in
11
10
01
00
1
falling_event
COGxC
0
count_en
GxMD0
GxEN
1
0
High-Z
clock
Forward/Reverse
COGINPPS
GxAS0E
C1OUT
GxAS1E
C2OUT
GxAS2E
CLC2OUT
GxAS3E
COGxB
GxASDAC<1:0>
clock
1
0
count_en
COGxA
0
Rising Dead-Band Block
GxCS<1:0>
unimplemented
PWM3OUT
CCP2
CCP1
CLC1OUT
C2OUT
C1OUT
COGINPPS
11
10
01
00
GxPOLC
GxASDBD<1:0>
1
0
High-Z
D Q
Q
11
10
01
00
COGxD
0
Auto-shutdown source
GxPOLD
GxASE
S Q
GxARSEN
Write GxASE Low
R
Set Dominates
S
D Q
PIC16(L)F1705/9
DS40001729B-page 176
FIGURE 18-4:
FIGURE 18-5:
reserved
HFINTOSC
11
10
Fosc
Fosc/4
01
00
GxCS<1:0>
unimplemented
PWM3OUT
CCP2
CCP1
CLC1OUT
C2OUT
C1OUT
COGINPPS
COG_clock
GxPOLA
src7
src6
src5
src4
src3
src2
src1
src0
GxASDBD<1:0>
clock
Reset Dominates
rising_event
S Q
1
0
High-Z
clock
signal_out
signal_in
11
10
01
00
COGxB
count_en
Falling Dead-Band Block
GxASDAC<1:0>
GxPOLB
1
0
High-Z
clock
clock
signal_out
signal_in
11
10
01
00
1
falling_event
COGxC
0
count_en
GxASDBD<1:0>
11
10
01
00
COGxD
0
Auto-shutdown source
GxPOLD
DS40001729B-page 177
GxASE
S Q
GxARSEN
Write GxASE Low
R
Set Dominates
S
D Q
PIC16(L)F1705/9
1
0
High-Z
GxEN
R Q
GxPOLC
COGINPPS
GxAS0E
C1OUT
GxAS1E
C2OUT
GxAS2E
CLC2OUT
GxAS3E
COGxA
11
10
01
00
reserved
HFINTOSC
11
10
Fosc
Fosc/4
01
00
GxCS<1:0>
unimplemented
PWM3OUT
CCP2
CCP1
CLC1OUT
C2OUT
C1OUT
COGINPPS
COG_clock
GxPOLA
src7
src6
src5
src4
src3
src2
src1
src0
GxASDBD<1:0>
Push-Pull
clock
Reset Dominates
rising_event
S Q
1
0
High-Z
D Q
R
11
10
01
00
R Q
count_en
COGxB
GxASDAC<1:0>
GxPOLB
1
0
High-Z
clock
11
10
01
00
1
falling_event
COGxC
0
count_en
GxASDBD<1:0>
1
0
High-Z
GxEN
1
0
GxPOLC
COGINPPS
GxAS0E
C1OUT
GxAS1E
C2OUT
GxAS2E
CLC2OUT
GxAS3E
COGxA
11
10
01
00
11
10
01
00
COGxD
0
Auto-shutdown source
GxPOLD
GxASE
S Q
GxARSEN
Write GxASE Low
R
Set Dominates
S
D Q
PIC16(L)F1705/9
DS40001729B-page 178
FIGURE 18-6:
FIGURE 18-7:
GxPH(R/F)<3:0>
Blanking
=
Cnt/Clr
count_en
Phase
Delay
GxBLK(F/R)<3:0>
src7
Gx(R/F)IS7
src6
Gx(R/F)SIM7
Gx(R/F)IS6
src5
Gx(R/F)SIM6
Gx(R/F)IS5
src4
Gx(R/F)SIM5
Gx(R/F)IS4
src3
Gx(R/F)SIM4
Gx(R/F)IS3
Gx(R/F)IS2
src1
Gx(R/F)SIM2
Gx(R/F)IS1
DS40001729B-page 179
src0
Gx(R/F)SIM1
Gx(R/F)IS0
Gx(R/F)SIM0
LE
D Q
LE
D Q
LE
D Q
LE
D Q
LE
D Q
LE
D Q
LE
D Q
LE
(rising/falling)_event
PIC16(L)F1705/9
src2
Gx(R/F)SIM3
D Q
PIC16(L)F1705/9
FIGURE 18-8:
Gx(R/F)DBTS
Synchronous
Delay
=
Cnt/Clr
clock
0
1
GxDBR<3:0>
Asynchronous
Delay Chain
signal_in
DS40001729B-page 180
signal_out
PIC16(L)F1705/9
FIGURE 18-9:
COG_clock
Source
CCP1
COGxA
Rising_event Dead Band
Falling_event Dead Band
Falling_event Dead Band
COGxB
FIGURE 18-10:
COG_clock
Source
CCP1
COGxA
Phase Delay
Rising_event
Dead Band
COGxB
FIGURE 18-11:
Falling_event
Dead Band
CCP1
COGxA
COGxB
DS40001729B-page 181
PIC16(L)F1705/9
FIGURE 18-12:
CCP1
COGxA
COGxB
COGxC
COGxD
FIGURE 18-13:
CCP1
COGxA
Falling_event Dead Band
COGxB
COGxC
COGxD
CxMD0
DS40001729B-page 182
PIC16(L)F1705/9
18.2
Clock Sources
FIGURE 18-14:
Rising (CCP1)
Falling (C1OUT)
COGOUT
Edge Sensitive
Falling (C1OUT)
C1IN-
COGOUT
18.3.1
hyst
C1IN-
18.3
hyst
Level Sensitive
18.3.2
RISING EVENT
18.3.3
FALLING EVENT
DS40001729B-page 183
PIC16(L)F1705/9
18.4
Output Control
18.4.1
OUTPUT ENABLES
There are no output enable controls in the COG module. Instead, each device pin has an individual output
selection control called the PPS register. All four COG
outputs are available for selection in the PPS register
of every pin.
When a COG output is enabled by PPS selection, the
output on the pin has several possibilities, which
depend on the steering control, GxEN bit, and shutdown state as shown in Table 18-1
.
TABLE 18-1:
GxEN
GxSTR
Shutdown
bit
Output
Inactive
Active
Shutdown override
Inactive
Inactive state
Inactive
x
0
1
18.4.2
POLARITY CONTROL
18.5
Dead-Band Control
DS40001729B-page 184
18.5.1
18.5.2
SYNCHRONOUS COUNTER
DEAD-BAND DELAY
18.5.3
SYNCHRONOUS COUNTER
DEAD-BAND TIME UNCERTAINTY
PIC16(L)F1705/9
18.5.4
Rising event dead band delays the turn-on of the primary outputs from when complementary outputs are
turned off. The rising event dead-band time starts
when the rising_ event output goes true.
See Section 18.5.1 Asynchronous Delay Chain
Dead-Band Delay and Section 18.5.2 Synchronous Counter Dead-Band Delay for more information on setting the rising edge dead-band time.
18.5.5
Falling event dead band delays the turn-on of complementary outputs from when the primary outputs are
turned off. The falling event dead-band time starts
when the falling_ event output goes true.
See Section 18.5.1 Asynchronous Delay Chain
Dead-Band Delay and Section 18.5.2 Synchronous Counter Dead-Band Delay for more information on setting the rising edge dead-band time.
18.5.6
Rising-to-falling
Falling-to-rising
Rising-to-Falling Overlap
18.5.6.2
Falling-to-Rising Overlap
18.6
18.6.1
Blanking Control
18.6.2
DEAD-BAND OVERLAP
18.5.6.1
18.6.3
18.7
Phase Delay
DS40001729B-page 185
PIC16(L)F1705/9
18.7.1
CUMULATIVE UNCERTAINTY
EQUATION 18-1:
T min = Count
EXAMPLE 18-1:
Given:
Count = Ah = 10d
F COG_Clock = 8MHz
Therefore:
1
T uncertainty = -------------------------F COG_clock
1
= --------------- = 125ns
8MHz
Proof:
Count
T min = -------------------------F COG_clock
= 125ns 10d = 1.25s
F COG_clock
T max
Count + 1
= -------------------------F COG_clock
Count + 1
T max = -------------------------F COG_clock
= 125ns 10d + 1
Also:
1
T uncertainty = -------------------------F COG_clock
Where:
TIMER UNCERTAINTY
= 1.375s
Therefore:
Count
COGxPHR
COGxPHF
COGxDBR
COGxDBF
COGxBLKR
COGxBLKF
DS40001729B-page 186
= 1.375s 1.25s
= 125ns
PIC16(L)F1705/9
18.8
Auto-Shutdown Control
18.8.1
SHUTDOWN
18.8.1.1
The levels driven to the output pins, while the shutdown is active, are controlled by the GxASDAC<1:0>
and GxASDBC<1:0> bits of the COGxASD0 register
(Register 18-7). GxASDAC<1:0> controls the COGxA
and COGxC override levels and GxASDBC<1:0> controls the COGxB and COGxD override levels. There
are four override options for each output pair:
Forced low
Forced high
Tri-state
PWM inactive state (same state as that caused by
a falling event)
Note:
18.8.1.2
18.8.2
18.8.3
AUTO-SHUTDOWN RESTART
18.8.3.1
Software-Controlled Restart
18.8.3.2
Auto-Restart
Note:
DS40001729B-page 187
CCP1
GxARSEN
Next rising event
Shutdown input
Next rising event
GxASE
Cleared in hardware
Cleared in software
GxASDAC
2b00
2b00
2b00
GxASDBD
COGxA
COGxB
Operating State
NORMAL OUTPUT
SHUTDOWN
NORMAL OUTPUT
SHUTDOWN
NORMAL OUTPUT
AUTO-RESTART
PIC16(L)F1705/9
DS40001729B-page 188
FIGURE 18-15: AUTO-SHUTDOWN WAVEFORM CCP1 AS RISING AND FALLING EVENT INPUT SOURCE
PIC16(L)F1705/9
18.9
Buffer Updates
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
DS40001729B-page 189
PIC16(L)F1705/9
18.13 Register Definitions: COG Control
REGISTER 18-1:
R/W-0/0
R/W-0/0
U-0
GxEN
GxLD
R/W-0/0
R/W-0/0
R/W-0/0
GxCS<1:0>
R/W-0/0
R/W-0/0
GxMD<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
Unimplemented: Read as 0
bit 4-3
bit 2-0
DS40001729B-page 190
PIC16(L)F1705/9
REGISTER 18-2:
R/W-0/0
GxRDBS
R/W-0/0
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
GxFDBS
GxPOLD
GxPOLC
GxPOLB
GxPOLA
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5-4
Unimplemented: Read as 0.
bit 3
bit 2
bit 1
bit 0
DS40001729B-page 191
PIC16(L)F1705/9
REGISTER 18-3:
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
GxRIS6
GxRIS5
GxRIS4
GxRIS3
GxRIS2
GxRIS1
GxRIS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS40001729B-page 192
PIC16(L)F1705/9
REGISTER 18-4:
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
GxRSIM6
GxRSIM5
GxRSIM4
GxRSIM3
GxRSIM2
GxRSIM1
GxRSIM0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS40001729B-page 193
PIC16(L)F1705/9
REGISTER 18-5:
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
GxFIS6
GxFIS5
GxFIS4
GxFIS3
GxFIS2
GxFIS1
GxFIS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS40001729B-page 194
PIC16(L)F1705/9
REGISTER 18-6:
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
GxFSIM6
GxFSIM5
GxFSIM4
GxFSIM3
GxFSIM2
GxFSIM1
GxFSIM0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS40001729B-page 195
PIC16(L)F1705/9
REGISTER 18-7:
R/W-0/0
R/W-0/0
GxASE
GxARSEN
R/W-0/0
R/W-0/0
GxASDBD<1:0>
R/W-0/0
R/W-0/0
GxASDAC<1:0>
U-0
U-0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5-4
bit 3-2
bit 1-0
Unimplemented: Read as 0
DS40001729B-page 196
PIC16(L)F1705/9
REGISTER 18-8:
U-0
U-0
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
GxAS3E
GxAS2E
GxAS1E
GxAS0E
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
Unimplemented: Read as 0
bit 3
bit 2
bit 1
bit 0
DS40001729B-page 197
PIC16(L)F1705/9
REGISTER 18-9:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
GxSDATD
GxSDATC
GxSDATB
GxSDATA
GxSTRD
GxSTRC
GxSTRB
GxSTRA
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS40001729B-page 198
PIC16(L)F1705/9
REGISTER 18-10: COGxDBR: COG RISING EVENT DEAD-BAND COUNT REGISTER
U-0
U-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
GxDBR<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
U-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
GxDBF<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
DS40001729B-page 199
PIC16(L)F1705/9
REGISTER 18-12: COGxBLKR: COG RISING EVENT BLANKING COUNT REGISTER
U-0
U-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
GxBLKR<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
U-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
GxBLKF<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
DS40001729B-page 200
PIC16(L)F1705/9
REGISTER 18-14: COGxPHR: COG RISING EDGE PHASE DELAY COUNT REGISTER
U-0
U-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
GxPHR<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
REGISTER 18-15: COGxPHF: COG FALLING EDGE PHASE DELAY COUNT REGISTER
U-0
U-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
GxPHF<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
DS40001729B-page 201
PIC16(L)F1705/9
TABLE 18-2:
Name
Bit 6
ANSELA
ANSELB(1)
Register
on Page
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSA4
ANSA2
ANSA1
ANSA0
122
ANSB5
ANSB4
128
ANSC5(2)
ANSC4(2)
ANSC3
ANSC2
ANSC1
ANSC0
133
ANSC7(1)
ANSC6(1)
COG1PHR
G1PHR<5:0>
201
COG1PHF
G1PHF<5:0>
201
COG1BLKR
G1BLKR<5:0>
200
COG1BLKF
G1BLKF<5:0>
200
COG1DBR
G1DBR<5:0>
199
COG1DBF
G1DBF<5:0>
COG1RIS
G1RIS6
G1RIS5
G1RIS4
G1RIS3
G1RIS2
G1RIS1
G1RIS0
192
COG1RSIM
G1RSIM6
G1RSIM5
G1RSIM4
G1RSIM3
G1RSIM2
G1RSIM1
G1RSIM0
193
COG1FIS
G1FIS6
G1FIS5
G1FIS4
G1FIS3
G1FIS2
G1FIS1
G1FIS0
194
COG1FSIM
G1FSIM6
G1FSIM5
G1FSIM4
G1FSIM3
G1FSIM2
G1FSIM1
G1FSIM0
COG1CON0
G1EN
G1LD
COG1CON1
G1RDBS
G1FDBS
COG1ASD0
G1ASE
G1ARSEN
ANSELC
199
G1CS<1:0>
G1ASDBD<1:0>
G1MD<2:0>
G1POLD
G1POLC
G1ASDAC<1:0>
195
190
G1POLB
G1POLA
191
196
COG1ASD1
G1AS3E
G1AS2E
G1AS1E
G1AS0E
197
COG1STR
G1SDATD
G1SDATC
G1SDATB
G1SDATA
G1STRD
G1STRC
G1STRB
G1STRA
198
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
PIE2
OSFIE
C2IE
C1IE
BCL1IE
TMR6IE
TMR4IE
CCP2IE
86
PIR2
OSFIF
C2IF
C1IF
BCL1IF
TMR6IF
TMR4IF
CCP2IF
89
INTCON
COG1PPS
RxyPPS
Legend:
Note 1:
2:
COG1PPS<4:0>
84
140
RxyPPS<4:0>
141
x = unknown, u = unchanged, = unimplemented locations read as 0. Shaded cells are not used by COG.
PIC16(L)F1709 only.
PIC16(L)F1705 only.
DS40001729B-page 202
PIC16(L)F1705/9
19.0
The Configurable Logic Cell (CLCx) provides programmable logic that operates outside the speed limitations
of software execution. The logic cell takes up to 32
input signals and, through the use of configurable
gates, reduces the 32 inputs to four logic lines that drive
one of eight selectable single-output logic functions.
Input sources are a combination of the following:
I/O pins
Internal clocks
Peripherals
Register bits
FIGURE 19-1:
LCxOUT
MLCxOUT
Q1
.
.
.
LCx_in[29]
LCx_in[30]
LCx_in[31]
to Peripherals
Input Data Selection Gates(1)
LCx_in[0]
LCx_in[1]
LCx_in[2]
LCxEN
lcxg1
lcxg2
lcxg3
Logic
Function
LCx_out
lcxq
(2)
PPS
Module
CLCx
lcxg4
LCxPOL
LCxMODE<2:0>
Interrupt
det
LCXINTP
LCXINTN
set bit
CLCxIF
Interrupt
det
Note 1:
2:
DS40001729B-page 203
PIC16(L)F1705/9
19.1
CLCx Setup
Programming the CLCx module is performed by configuring the four stages in the logic signal flow. The four
stages are:
Data selection
Data gating
Logic function selection
Output polarity
Each stage is setup at run time by writing to the corresponding CLCx Special Function Registers. This has
the added advantage of permitting logic reconfiguration
on-the-fly during program execution.
19.1.1
DATA SELECTION
There are 32 signals available as inputs to the configurable logic. Four 32-input multiplexers are used to
select the inputs to pass on to the next stage.
TABLE 19-1:
Data Input
lcxdy
DxS
CLCx
Note:
DS40001729B-page 204
01001 C2OUT
LCx_in[8]
01000 C1OUT
LCx_in[7]
00111 Reserved
LCx_in[6]
LCx_in[5]
LCx_in[4]
LCx_in[3]
LCx_in[2]
LCx_in[1]
LCx_in[0]
PIC16(L)F1705/9
19.1.2
DATA GATING
TABLE 19-2:
CLCxGLS0
LCxG1POL
Gate Logic
0x55
AND
0x55
NAND
0xAA
NOR
0xAA
OR
0x00
Logic 0
0x00
Logic 1
19.1.3
LOGIC FUNCTION
AND-OR
OR-XOR
AND
S-R Latch
D Flip-Flop with Set and Reset
D Flip-Flop with Reset
J-K Flip-Flop with Reset
Transparent Latch with Set and Reset
19.1.4
OUTPUT POLARITY
DS40001729B-page 205
PIC16(L)F1705/9
19.1.5
19.2
CLCx Interrupts
19.3
19.4
Effects of a Reset
19.5
DS40001729B-page 206
PIC16(L)F1705/9
FIGURE 19-2:
LCx_in[0]
Data GATE 1
LCx_in[31]
lcxd1T
LCxD1G1T
lcxd1N
LCxD1G1N
11111
LCxD2G1T
LCxD1S<4:0>
LCxD2G1N
LCx_in[0]
lcxg1
00000
LCxD3G1T
lcxd2T
LCxG1POL
LCxD3G1N
lcxd2N
LCx_in[31]
LCxD4G1T
11111
LCxD2S<4:0>
LCx_in[0]
LCxD4G1N
00000
Data GATE 2
lcxg2
lcxd3T
lcxd3N
LCx_in[31]
Data GATE 3
11111
lcxg3
LCxD3S<4:0>
LCx_in[0]
00000
lcxg4
lcxd4T
lcxd4N
LCx_in[31]
11111
LCxD4S<4:0>
Note:
DS40001729B-page 207
PIC16(L)F1705/9
FIGURE 19-3:
OR - XOR
lcxg1
lcxg1
lcxg2
lcxq
lcxg3
lcxg4
lcxg2
lcxq
lcxg3
lcxg4
LCxMODE<2:0>= 000
LCxMODE<2:0>= 001
4-Input AND
S-R Latch
lcxg1
lcxg1
lcxg2
lcxg2
lcxq
lcxg3
lcxg3
lcxg4
lcxg4
LCxMODE<2:0>= 010
lcxq
LCxMODE<2:0>= 011
lcxg4
lcxg2
lcxg4
Q
lcxq
lcxg2
lcxg1
lcxg1
lcxq
R
lcxg3
lcxg3
LCxMODE<2:0>= 100
LCxMODE<2:0>= 101
lcxg2
lcxg1
lcxg4
lcxq
lcxg2
lcxg1
LE
lcxg3
lcxq
lcxg3
LCxMODE<2:0>= 110
DS40001729B-page 208
LCxMODE<2:0>= 111
PIC16(L)F1705/9
19.6
REGISTER 19-1:
R/W-0/0
U-0
R-0/0
R/W-0/0
R/W-0/0
LCxEN
LCxOUT
LCxINTP
LCxINTN
R/W-0/0
R/W-0/0
R/W-0/0
LCxMODE<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
Unimplemented: Read as 0
bit 5
bit 4
LCxINTP: Configurable Logic Cell Positive Edge Going Interrupt Enable bit
1 = CLCxIF will be set when a rising edge occurs on lcx_out
0 = CLCxIF will not be set
bit 3
LCxINTN: Configurable Logic Cell Negative Edge Going Interrupt Enable bit
1 = CLCxIF will be set when a falling edge occurs on lcx_out
0 = CLCxIF will not be set
bit 2-0
DS40001729B-page 209
PIC16(L)F1705/9
REGISTER 19-2:
R/W-0/0
U-0
U-0
U-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxPOL
LCxG4POL
LCxG3POL
LCxG2POL
LCxG1POL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-4
Unimplemented: Read as 0
bit 3
bit 2
bit 1
bit 0
DS40001729B-page 210
PIC16(L)F1705/9
REGISTER 19-3:
U-0
U-0
U-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxD1S<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-5
Unimplemented: Read as 0
bit 4-0
REGISTER 19-4:
U-0
U-0
U-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxD2S<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-5
Unimplemented: Read as 0
bit 4-0
REGISTER 19-5:
U-0
U-0
U-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxD3S<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-5
Unimplemented: Read as 0
bit 4-0
DS40001729B-page 211
PIC16(L)F1705/9
REGISTER 19-6:
U-0
U-0
U-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxD4S<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-5
Unimplemented: Read as 0
bit 4-0
REGISTER 19-7:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxG1D4T
LCxG1D4N
LCxG1D3T
LCxG1D3N
LCxG1D2T
LCxG1D2N
LCxG1D1T
LCxG1D1N
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS40001729B-page 212
PIC16(L)F1705/9
REGISTER 19-8:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxG2D4T
LCxG2D4N
LCxG2D3T
LCxG2D3N
LCxG2D2T
LCxG2D2N
LCxG2D1T
LCxG2D1N
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS40001729B-page 213
PIC16(L)F1705/9
REGISTER 19-9:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxG3D4T
LCxG3D4N
LCxG3D3T
LCxG3D3N
LCxG3D2T
LCxG3D2N
LCxG3D1T
LCxG3D1N
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS40001729B-page 214
PIC16(L)F1705/9
REGISTER 19-10: CLCxGLS3: GATE 4 LOGIC SELECT REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxG4D4T
LCxG4D4N
LCxG4D3T
LCxG4D3N
LCxG4D2T
LCxG4D2N
LCxG4D1T
LCxG4D1N
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS40001729B-page 215
PIC16(L)F1705/9
REGISTER 19-11: CLCDATA: CLC DATA OUTPUT
U-0
U-0
U-0
U-0
U-0
R-0
R-0
R-0
MLC3OUT
MLC2OUT
MLC1OUT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-3
Unimplemented: Read as 0
bit 2
bit 1
bit 0
DS40001729B-page 216
PIC16(L)F1705/9
TABLE 19-3:
Name
ANSELA
ANSELB(1)
ANSELC
Bit6
Bit4
BIt3
Bit2
Bit1
Bit0
Register
on Page
ANSA4
ANSA2
ANSA1
ANSA0
122
ANSB4
128
ANSC2
ANSC1
ANSC0
133
Bit5
ANSB5
ANSC7(1)
ANSC6(1)
ANSC5(2)
ANSC4(2)
ANSC3
CLC1CON
LC1EN
LC1OUT
LC1INTP
LC1INTN
LC1MODE<2:0>
209
CLC2CON
LC2EN
LC2OUT
LC2INTP
LC2INTN
LC2MODE<2:0>
209
CLC3CON
LC3EN
LC3OUT
LC3INTP
LC3INTN
CLCDATA
MLC3OUT
MLC2OUT
MLC1OUT
216
CLC1GLS0
LC1G1D4T
LC1G1D4N
LC1G1D3T
LC1G1D3N
LC1G1D2T
LC1G1D2N
LC1G1D1T
LC1G1D1N
212
CLC1GLS1
LC1G2D4T
LC1G2D4N
LC1G2D3T
LC1G2D3N
LC1G2D2T
LC1G2D2N
LC1G2D1T
LC1G2D1N
213
CLC1GLS2
LC1G3D4T
LC1G3D4N
LC1G3D3T
LC1G3D3N
LC1G3D2T
LC1G3D2N
LC1G3D1T
LC1G3D1N
214
CLC1GLS3
LC1G4D4T
LC1G4D4N
LC1G4D3T
LC1G4D3N
LC1G4D2T
LC1G4D2N
LC1G4D1T
LC1G4D1N
215
CLC1POL
LC1POL
LC1G4POL
LC1G3POL
LC1G2POL
LC1G1POL
210
LC3MODE<2:0>
209
CLC1SEL0
LC1D1S<4:0>
211
CLC1SEL1
LC1D2S<4:0>
211
CLC1SEL2
LC1D3S<4:0>
211
CLC1SEL3
LC1D4S<4:0>
212
CLC2GLS0
LC2G1D4T
LC2G1D4N
LC2G1D3T
LC2G1D3N
LC2G1D2T
LC2G1D2N
LC2G1D1T
LC2G1D1N
212
CLC2GLS1
LC2G2D4T
LC2G2D4N
LC2G2D3T
LC2G2D3N
LC2G2D2T
LC2G2D2N
LC2G2D1T
LC2G2D1N
213
CLC2GLS2
LC2G3D4T
LC2G3D4N
LC2G3D3T
LC2G3D3N
LC2G3D2T
LC2G3D2N
LC2G3D1T
LC2G3D1N
214
CLC2GLS3
LC2G4D4T
LC2G4D4N
LC2G4D3T
LC2G4D3N
LC2G4D2T
LC2G4D2N
LC2G4D1T
LC2G4D1N
215
CLC2POL
LC2POL
LC2G4POL
LC2G3POL
LC2G2POL
LC2G1POL
210
CLC2SEL0
LC2D1S<4:0>
211
CLC2SEL1
LC2D2S<4:0>
211
CLC2SEL2
LC2D3S<4:0>
211
CLC2SEL3
LC2D4S<4:0>
212
CLC3GLS0
LC3G1D4T
LC3G1D4N
LC3G1D3T
LC3G1D3N
LC3G1D2T
LC3G1D2N
LC3G1D1T
LC3G1D1N
212
CLC3GLS1
LC3G2D4T
LC3G2D4N
LC3G2D3T
LC3G2D3N
LC3G2D2T
LC3G2D2N
LC3G2D1T
LC3G2D1N
213
CLC3GLS2
LC3G3D4T
LC3G3D4N
LC3G3D3T
LC3G3D3N
LC3G3D2T
LC3G3D2N
LC3G3D1T
LC3G3D1N
214
CLC3GLS3
LC3G4D4T
LC3G4D4N
LC3G4D3T
LC3G4D3N
LC3G4D2T
LC3G4D2N
LC3G4D1T
LC3G4D1N
215
CLC3POL
LC3POL
LC3G4POL
LC3G3POL
LC3G2POL
LC3G1POL
210
CLC3SEL0
LC3D1S<4:0>
211
CLC3SEL1
LC3D2S<4:0>
211
CLC3SEL2
LC3D3S<4:0>
211
CLC3SEL3
LC3D4S<4:0>
212
CLCxPPS
CLCxPPS<4:0>
139, 140
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
84
PIE3
INTCON
COGIE
ZCDIE
CLC3IE
CLC2IE
CLC1IE
87
PIR3
COGIF
ZCDIF
CLC3IF
CLC2IF
CLC1IF
RxyPPS
TRISA
TRISA5
TRISA4
(3)
TRISA2
TRISA1
TRISA0
121
TRISB7
TRISB6
TRISB5
TRISB4
127
TRISC7(1)
TRISC6(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
132
TRISB(1)
TRISC
Legend:
Note 1:
2:
3:
RxyPPS<4:0>
90
141
= unimplemented read as 0. Shaded cells are not used for CLC module.
PIC16(L)F1709 only.
PIC16(L)F1705 only.
Unimplemented, read as 1.
DS40001729B-page 217
PIC16(L)F1705/9
20.0
ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
FIGURE 20-1:
VREF+
ADPREF = 11
FVR_Buffer1
ADPREF = 10
VREF- = VSS
AN0
00000
VREF+/AN1
00001
AN2
00010
AN3
00011
AN4
00100
AN5
00101
AN6
00110
AN7
00111
ADCREF+ ADCREF-
AN8
01000
ADC
AN9
01001
AN10
01010
AN11
01011
ADNREF = 0
ADNREF = 1
10
GO/DONE
ADFM
0 = Left Justify
1 = Right Justify
16
ADON
Reserved
11100
Temp Indicator
11101
DAC_output
11110
FVR_Buffer1
11111
VSS
ADRESH
ADRESL
CHS<4:0>
Note 1:
DS40001729B-page 218
PIC16(L)F1705/9
20.1
ADC Configuration
Port configuration
Channel selection
ADC voltage reference selection
ADC conversion clock source
Interrupt control
Result formatting
20.1.1
PORT CONFIGURATION
20.1.2
CHANNEL SELECTION
20.1.4
CONVERSION CLOCK
The source of the conversion clock is software selectable via the ADCS bits of the ADCON1 register. There
are seven possible clock options:
FOSC/2
FOSC/4
FOSC/8
FOSC/16
FOSC/32
FOSC/64
FRC (internal RC oscillator)
20.1.3
VREF+ pin
VDD
FVR 2.048V
FVR 4.096V (Not available on LF devices)
DS40001729B-page 219
PIC16(L)F1705/9
TABLE 20-1:
ADC
Clock Source
ADCS<2:0>
32 MHz
20 MHz
16 MHz
8 MHz
4 MHz
1 MHz
FOSC/2
000
62.5ns(2)
100 ns(2)
125 ns(2)
250 ns(2)
500 ns(2)
2.0 s
FOSC/4
100
125 ns
(2)
(2)
(2)
(2)
FOSC/8
001
0.5 s(2)
400 ns(2)
0.5 s(2)
FOSC/16
101
800 ns
800 ns
010
1.0 s
FOSC/64
110
FRC
x11
FOSC/32
Legend:
Note 1:
2:
3:
4:
1.0 s
4.0 s
1.0 s
2.0 s
8.0 s(3)
1.0 s
2.0 s
4.0 s
16.0 s(3)
1.6 s
2.0 s
4.0 s
2.0 s
3.2 s
4.0 s
1.0-6.0 s(1,4)
1.0-6.0 s(1,4)
1.0-6.0 s(1,4)
200 ns
250 ns
500 ns
8.0 s
32.0 s(2)
(3)
8.0 s
16.0 s
(3)
64.0 s(2)
(2)
1.0-6.0 s(1,4)
1.0-6.0 s(1,4)
1.0-6.0 s(1,4)
FIGURE 20-2:
TAD2
TAD3
TAD4
TAD5
TAD6
TAD7
TAD8
TAD9
TAD10
TAD11
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
THCD
Conversion Starts
TACQ
DS40001729B-page 220
PIC16(L)F1705/9
20.1.5
INTERRUPTS
20.1.6
RESULT FORMATTING
FIGURE 20-3:
(ADFM = 0)
ADRESL
MSB
LSB
bit 7
bit 0
bit 7
bit 0
Unimplemented: Read as 0
MSB
bit 7
Unimplemented: Read as 0
LSB
bit 0
bit 7
bit 0
10-bit ADC Result
DS40001729B-page 221
PIC16(L)F1705/9
20.2
20.2.1
ADC Operation
STARTING A CONVERSION
20.2.2
COMPLETION OF A CONVERSION
20.2.3
TERMINATING A CONVERSION
20.2.4
20.2.5
AUTO-CONVERSION TRIGGER
The Auto-conversion Trigger allows periodic ADC measurements without software intervention. When a rising
edge of the selected source occurs, the GO/DONE bit
is set by hardware.
The Auto-conversion Trigger source is selected with
the TRIGSEL<3:0> bits of the ADCON2 register.
Using the Auto-conversion Trigger does not assure
proper ADC timing. It is the users responsibility to
ensure that the ADC timing requirements are met.
See Table 20-2 for auto-conversion sources.
TABLE 20-2:
AUTO-CONVERSION
SOURCES
Source Peripheral
Signal Name
CCP1
CCP2
DS40001729B-page 222
Timer0
T0_overflow
Timer1
T1_overflow
Timer2
T2_match
Timer4
T4_match
Timer6
T6_match
Comparator C1
C1OUT_sync
Comparator C2
C2OUT_sync
CLC1
LC1_out
CLC2
LC2_out
CLC3
LC3_out
PIC16(L)F1705/9
20.2.6
2.
3.
4.
5.
6.
7.
8.
Configure Port:
Disable pin output driver (Refer to the TRIS
register)
Configure pin as analog (Refer to the ANSEL
register)
Configure the ADC module:
Select ADC conversion clock
Configure voltage reference
Select ADC input channel
Turn on ADC module
Configure ADC interrupt (optional):
Clear ADC interrupt flag
Enable ADC interrupt
Enable peripheral interrupt
Enable global interrupt(1)
Wait the required acquisition time(2).
Start conversion by setting the GO/DONE bit.
Wait for ADC conversion to complete by one of
the following:
Polling the GO/DONE bit
Waiting for the ADC interrupt (interrupts
enabled)
Read ADC Result.
Clear the ADC interrupt flag (required if interrupt
is enabled).
EXAMPLE 20-1:
ADC CONVERSION
DS40001729B-page 223
PIC16(L)F1705/9
20.3
REGISTER 20-1:
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
CHS<4:0>
R/W-0/0
R/W-0/0
R/W-0/0
GO/DONE
ADON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 0
bit 6-2
bit 1
bit 0
Note 1:
2:
3:
See Section 22.0 8-Bit Digital-to-Analog Converter (DAC1) Module for more information.
See Section 14.0 Fixed Voltage Reference (FVR) for more information.
See Section 15.0 Temperature Indicator Module for more information.
DS40001729B-page 224
PIC16(L)F1705/9
REGISTER 20-2:
R/W-0/0
R/W-0/0
ADFM
R/W-0/0
R/W-0/0
ADCS<2:0>
U-0
R/W-0/0
ADNREF
R/W-0/0
bit 7
R/W-0/0
ADPREF<1:0>
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-4
bit 3
Unimplemented: Read as 0
bit 2
bit 1-0
Note 1:
When selecting the VREF+ pin as the source of the positive reference, be aware that a minimum voltage
specification exists. See Table : for details.
DS40001729B-page 225
PIC16(L)F1705/9
REGISTER 20-3:
R/W-0/0
R/W-0/0
R/W-0/0
TRIGSEL<3:0>
R/W-0/0
(1)
U-0
U-0
U-0
U-0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
bit 3-0
Note 1:
2:
DS40001729B-page 226
PIC16(L)F1705/9
REGISTER 20-4:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
ADRES<9:2>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
REGISTER 20-5:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
ADRES<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-0
DS40001729B-page 227
PIC16(L)F1705/9
REGISTER 20-6:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
ADRES<9:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-2
bit 1-0
REGISTER 20-7:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
ADRES<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
DS40001729B-page 228
PIC16(L)F1705/9
20.4
EQUATION 20-1:
Assumptions:
T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= T AMP + T C + T COFF
= 2s + T C + Temperature - 25C 0.05s/C
The value for TC can be approximated with the following equations:
1
= V CHOLD
V AP P LI ED 1 -------------------------n+1
2
1
TC
----------
RC
V AP P LI ED 1 e = V CHOLD
Tc
---------
1
RC
;combining [1] and [2]
V AP P LI ED 1 e = V A PP LIE D 1 -------------------------n+1
2
1
T C = C HOLD R IC + R SS + R S ln(1/2047)
= 10pF 1k + 7k + 10k ln(0.0004885)
= 1.37 s
Therefore:
T A CQ = 2s + 892ns + 50C- 25C 0.05 s/C
= 4.62s
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
DS40001729B-page 229
PIC16(L)F1705/9
FIGURE 20-4:
Analog
Input
pin
Rs
VT 0.6V
CPIN
5 pF
VA
RIC 1k
Sampling
Switch
SS Rss
I LEAKAGE(1)
VT 0.6V
CHOLD = 10 pF
Ref-
6V
5V
VDD 4V
3V
2V
= Sample/Hold Capacitance
= Input Capacitance
Legend: CHOLD
CPIN
RSS
= Sampling Switch
VT
= Threshold Voltage
Note 1:
5 6 7 8 9 10 11
Sampling Switch
(k)
FIGURE 20-5:
Full-Scale Range
3FFh
3FEh
3FDh
3FCh
3FBh
03h
02h
01h
00h
Ref-
DS40001729B-page 230
Zero-Scale
Transition
1.5 LSB
Full-Scale
Transition
Ref+
PIC16(L)F1705/9
TABLE 20-3:
Name
ADCON0
ADCON1
ADFM
ADCON2
Bit 6
Bit 5
Bit 4
Bit 2
ADPREF<1:0>
225
226
CHS<4:0>
ADCS<2:0>
TRIGSEL<3:0>
ADRESH
ADRESL
Bit 1
Bit 0
GO/DONE
ADON
Register
on Page
Bit 3
224
227, 228
227, 228
ANSELA
ANSA4
ANSA2
ANSA1
ANSA0
122
ANSELB(1)
ANSB5
ANSB4
128
ANSELC
ANSC7(1)
ANSC6(1)
ANSC5(2)
ANSC4(2)
ANSC3
ANSC2
ANSC1
ANSC0
133
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
84
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
85
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
88
TRISA5
TRISA4
(3)
TRISA2
TRISA1
TRISA0
121
TRISB7
TRISB6
TRISB5
TRISB4
127
TRISC7(1)
TRISC6(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
132
FVREN
FVRRDY
TSEN
TSRNG
CDAFVR<1:0>
DAC1EN
DAC1OE1
DAC1OE2
DAC1PSS<1:0>
TRISA
TRISB(1)
TRISC
FVRCON
DAC1CON0
Legend:
Note 1:
2:
3:
ADFVR<1:0>
DAC1NSS
153
238
x = unknown, u = unchanged, = unimplemented read as 0, q = value depends on condition. Shaded cells are not
used for the ADC module.
PIC16(L)F1709 only.
PIC16(L)F1705 only.
Unimplemented, read as 1.
DS40001729B-page 231
PIC16(L)F1705/9
21.0
OPERATIONAL AMPLIFIER
(OPA) MODULES
FIGURE 21-1:
OPAxIN+
0x
DAC_output
10
FVR Buffer 2
11
OPAXEN
OPAXSP(1)
OPAxIN-
OPAXOUT
OPA
1
OPAxNCH<1:0>
OPAXUG
Note 1: The OPAxSP bit must be set. Low-Power mode is not supported.
DS40001729B-page 232
PIC16(L)F1705/9
21.1
21.1.1
21.1.2
21.2
Effects of Reset
DS40001729B-page 233
PIC16(L)F1705/9
21.3
REGISTER 21-1:
R/W-0/0
R/W-0/0
U-0
R/W-0/0
U-0
U-0
OPAxEN
OPAxSP
OPAxUG
R/W-0/0
R/W-0/0
OPAxCH<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
Unimplemented: Read as 0
bit 4
bit 3-2
Unimplemented: Read as 0
bit 1-0
TABLE 21-1:
Name
ANSELB(1)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSB5
ANSB4
128
ANSELC
ANSC7(1)
ANSC6(1)
ANSC5(2)
ANSC4(2)
ANSC3
ANSC2
ANSC1
ANSC0
128
DAC1CON0
DAC1EN
DAC1NSS
238
DAC1OE1 DAC1OE2
DAC1CON1
FVRCON
DAC1PSS<1:0>
DAC1R<7:0>
238
FVREN
FVRRDY
TSEN
TSRNG
ADFVR<1:0>
153
OPA1CON
OPA1EN
OPA1SP
OPA1UG
OPA1PCH<1:0>
234
OPA2CON
OPA2EN
OPA2SP
OPA2UG
OPA2PCH<1:0>
234
TRISB7
TRISB6
TRISB5
TRISB4
127
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
132
TRISB(1)
TRISC
Legend:
Note 1:
2:
3:
(1)
TRISC7
(1)
TRISC6
CDAFVR<1:0>
DS40001729B-page 234
PIC16(L)F1705/9
22.0
8-BIT DIGITAL-TO-ANALOG
CONVERTER (DAC1) MODULE
22.1
The DAC has 256 voltage level ranges. The 256 levels
are set with the DAC1R<7:0> bits of the DAC1CON1
register.
The DAC output voltage is determined by Equation 22-1:
EQUATION 22-1:
IF DAC1EN = 1
DAC1R 7:0
VOUT = VSOURCE+ VSOURCE- -------------------------------- + VSOURCE8
2
VSOURCE+ = VDD, VREF, or FVR BUFFER 2
VSOURCE- = VSS
22.2
22.3
DS40001729B-page 235
PIC16(L)F1705/9
FIGURE 22-1:
FVR Buffer2
VSOURCE+
VDD
VREF+
DAC1R<7:0>
R
R
DAC1PSS<1:0>
2
R
DAC1EN
R
256
Steps
R
256-to-1 MUX
R
DAC1_Output
DAC1OUT1
DAC1OE1
DAC1NSS
DAC1OUT2
VREF-
DAC1OE2
VSOURCE-
VSS
FIGURE 22-2:
DAC
Module
R
Voltage
Reference
Output
Impedance
DS40001729B-page 236
DAC1OUTX
PIC16(L)F1705/9
22.4
22.5
Effects of a Reset
DS40001729B-page 237
PIC16(L)F1705/9
22.6
REGISTER 22-1:
R/W-0/0
U-0
R/W-0/0
R/W-0/0
DAC1EN
DAC1OE1
DAC1OE2
R/W-0/0
R/W-0/0
U-0
R/W-0/0
DAC1NSS
DAC1PSS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
Unimplemented: Read as 0
bit 5
bit 4
bit 3-2
bit 1
Unimplemented: Read as 0
bit 0
REGISTER 22-2:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
DAC1R<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
TABLE 22-1:
Name
DAC1CON0
Bit 6
DAC1EN
DAC1CON1
Legend:
Bit 5
Bit 4
DAC1OE1 DAC1OE2
Bit 3
Bit 2
DAC1PSS<1:0>
Bit 1
Bit 0
Register
on page
DAC1NSS
238
DAC1R<7:0>
238
= Unimplemented location, read as 0. Shaded cells are not used with the DAC module.
DS40001729B-page 238
PIC16(L)F1705/9
23.0
ZERO-CROSS DETECTION
(ZCD) MODULE
23.1
EQUATION 23-1:
FIGURE 23-1:
EXTERNAL VOLTAGE
VMAXPEAK
VMINPEAK
VPEAK
FIGURE 23-2:
EXTERNAL RESISTOR
V PEAK
R SERIES = ---------------4
3 10
ZCPINV
VDD
RPULLUP
External current
limiting resistor
ZCPINV
RSERIES
ZCD pin
RPULLDOWN
optional
External
voltage
source
ZCDx_output
D
ZCDxPOL
Q1
ZCDxOUT
LE
Interrupt
det
ZCDxINTP
Sets
ZCDIF flag
ZCDxINTN
Interrupt
det
DS40001729B-page 239
PIC16(L)F1705/9
23.2
23.3
23.5
EQUATION 23-2:
23.4
ZCD Interrupts
T OFFSET
Z CPINV
asin ------------------
V PEAK
= ----------------------------------2 Freq
T OFFSET
V DD Z CPINV
asin ---------------------------------
V PEAK
= ------------------------------------------------2 Freq
EQUATION 23-3:
ZCD PULL-UP/DOWN
Z CPINV
R SERIES Z CPINV
R PULLDOWN = -------------------------------------------- V DD Z CPINV
DS40001729B-page 240
PIC16(L)F1705/9
The pull-up and pull-down resistor values are
significantly affected by small variations of ZCPINV.
Measuring ZCPINV can be difficult, especially when the
waveform is relative to VDD. However, by combining
Equations 23-2 and 23-3, the resistor value can be
determined from the time difference between the
ZCDx_output high and low periods. Note that the time
difference, T, is 4*TOFFSET. The equation for
determining the pull-up and pull-down resistor values
from the high and low ZCDx_output periods is shown in
Equation 23-4. The ZCDx_output signal can be directly
observed on a pin by routing the ZCDx_output signal
through one of the CLCs.
EQUATION 23-4:
V BI A S
R = R SERIES ---------------------------------------------------------------- 1
T
V PE AK sin Freq ----------
2
R is pull-up or pull-down resistor.
VBIAS is VPULLUP when R is pull-up or VDD when R
is pull-down.
T is the ZCDOUT high and low period difference.
23.6
EQUATION 23-5:
V MAXPEAK + V MINPEAK
R SERIES = --------------------------------------------------------4
7 10
23.7
23.8
Effects of a Reset
DS40001729B-page 241
PIC16(L)F1705/9
23.9
REGISTER 23-1:
R/W-0/0
U-0
R-x/x
R/W-0/0
U-0
U-0
R/W-0/0
R/W-0/0
ZCDxEN
ZCDxOUT
ZCDxPOL
ZCDxINTP
ZCDxINTN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
Unimplemented: Read as 0
bit 5
bit 4
bit 3-2
Unimplemented: Read as 0
bit 1
bit 0
Note 1:
The ZCDxEN bit has no effect when the ZCDDIS Configuration bit is cleared.
TABLE 23-1:
Name
Bit 7
Bit 6
PIE3
PIR3
ZCD1EN
ZCD1OUT
ZCD1CON
Legend:
CONFIG2
Legend:
Bit 4
Bit 3
COGIE
ZCDIE
CWGIF
ZCDIF
ZCD1POL
Bit 0
Register
on page
Bit 2
Bit 1
87
90
ZCD1INTP ZCD1INTN
242
TABLE 23-2:
Name
Bit 5
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
Bit 10/2
Bit 9/1
Bit 8/0
Register
on Page
13:8
LVP
DEBUG
LPBOR
BORV
STVREN
PLLEN
50
7:0
ZCDDIS
WRT<1:0>
= unimplemented location, read as 0. Shaded cells are not used by the ZCD module.
DS40001729B-page 242
PIC16(L)F1705/9
24.0
24.1.2
TIMER0 MODULE
24.1
Timer0 Operation
24.1.1
FIGURE 24-1:
FOSC/4
Data Bus
0
T0CKI
Sync
2 TCY
TMR0
TMR0SE TMR0CS
8-bit
Prescaler
PSA
PS<2:0>
DS40001729B-page 243
PIC16(L)F1705/9
24.1.3
SOFTWARE PROGRAMMABLE
PRESCALER
There are eight prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are
selectable via the PS<2:0> bits of the OPTION_REG
register. In order to have a 1:1 prescaler value for the
Timer0 module, the prescaler must be disabled by
setting the PSA bit of the OPTION_REG register.
The prescaler is not readable or writable. All instructions
writing to the TMR0 register will clear the prescaler.
24.1.4
TIMER0 INTERRUPT
24.1.5
24.1.6
DS40001729B-page 244
PIC16(L)F1705/9
24.2
REGISTER 24-1:
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
WPUEN
INTEDG
TMR0CS
TMR0SE
PSA
R/W-1/1
R/W-1/1
R/W-1/1
PS<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
TABLE 24-1:
Name
INTCON
TRISA
Timer0 Rate
000
001
010
011
100
101
110
111
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
OPTION_REG WPUEN
TMR0
Bit Value
Bit 6
PEIE
INTEDG
Bit 5
Bit 4
Bit 3
Bit 2
TMR0IE
INTE
IOCIE
TMR0IF
TMR0CS TMR0SE
PSA
Bit 1
Bit 0
INTF
IOCIF
PS<2:0>
TRISA5
84
245
Register
on Page
243*
TRISA4
(1)
TRISA2
TRISA1
TRISA0
121
Legend: = Unimplemented location, read as 0. Shaded cells are not used by the Timer0 module.
* Page provides register information.
Note 1: Unimplemented, read as 1.
DS40001729B-page 245
PIC16(L)F1705/9
25.0
FIGURE 25-1:
T1GSS<1:0>
T1G
T1GSPM
00
From Timer0
Overflow
01
sync_C1OUT
10
t1g_in
T1GVAL
sync_C2OUT
Single-Pulse
D
CK
R
11
TMR1ON
T1GPOL
T1GTM
Acq. Control
Q1
Data Bus
D
Q
RD
T1GCON
EN
Interrupt
T1GGO/DONE
Set
TMR1GIF
det
TMR1GE
TMR1ON
To Comparator Module
TMR1(2)
TMR1H
EN
TMR1L
T1CLK
Synchronized
clock input
1
TMR1CS<1:0>
SOSCO
LFINTOSC
SOSC
SOSCI
T1SYNC
OUT
11
Synchronize(3)
Prescaler
1, 2, 4, 8
det
10
EN
0
T1OSCEN
(1)
FOSC
Internal
Clock
01
FOSC/4
Internal
Clock
00
2
T1CKPS<1:0>
FOSC/2
Internal
Clock
Sleep input
T1CKI
To Clock Switching Modules
DS40001729B-page 246
PIC16(L)F1705/9
25.1
Timer1 Operation
25.2
TABLE 25-1:
TIMER1 ENABLE
SELECTIONS
25.2.1
Timer1
Operation
TMR1ON
TMR1GE
Off
Off
25.2.2
Always On
Count Enabled
TABLE 25-2:
TMR1CS<1:0>
Clock Source
11
LFINTOSC
10
01
00
DS40001729B-page 247
PIC16(L)F1705/9
25.3
Timer1 Prescaler
25.4
25.5.1
25.6
Note:
25.5
Timer1 Operation in
Asynchronous Counter Mode
DS40001729B-page 248
Timer1 Gate
25.6.1
TABLE 25-3:
T1CLK
T1GPOL
T1G
Timer1 Operation
Counts
Holds Count
Holds Count
Counts
PIC16(L)F1705/9
25.6.2
TABLE 25-4:
T1GSS
00
01
Overflow of Timer0
(TMR0 increments from FFh to 00h)
10
11
25.6.2.1
25.6.2.2
25.6.2.3
25.6.2.4
25.6.3
When Timer1 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a Timer1 gate
signal, as opposed to the duration of a single level
pulse.
25.6.4
25.6.5
25.6.6
DS40001729B-page 249
PIC16(L)F1705/9
25.7
Timer1 Interrupt
Note:
25.8
25.9
Section 27.0
FIGURE 25-2:
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1:
2:
DS40001729B-page 250
PIC16(L)F1705/9
FIGURE 25-3:
TMR1GE
T1GPOL
t1g_in
T1CKI
T1GVAL
Timer1
FIGURE 25-4:
N+1
N+2
N+3
N+4
TMR1GE
T1GPOL
T1GTM
t1g_in
T1CKI
T1GVAL
Timer1
N+4
N+8
DS40001729B-page 251
PIC16(L)F1705/9
FIGURE 25-5:
TMR1GE
T1GPOL
T1GSPM
T1GGO/
Cleared by hardware on
falling edge of T1GVAL
Set by software
DONE
Counting enabled on
rising edge of T1G
t1g_in
T1CKI
T1GVAL
Timer1
TMR1GIF
DS40001729B-page 252
Cleared by software
N+1
N+2
Set by hardware on
falling edge of T1GVAL
Cleared by
software
PIC16(L)F1705/9
FIGURE 25-6:
TMR1GE
T1GPOL
T1GSPM
T1GTM
T1GGO/
Cleared by hardware on
falling edge of T1GVAL
Set by software
DONE
Counting enabled on
rising edge of T1G
t1g_in
T1CKI
T1GVAL
Timer1
TMR1GIF
Cleared by software
N+1
N+2
N+3
N+4
Set by hardware on
falling edge of T1GVAL
Cleared by
software
DS40001729B-page 253
PIC16(L)F1705/9
25.11 Register Definitions: Timer1 Control
REGISTER 25-1:
R/W-0/u
R/W-0/u
TMR1CS<1:0>
R/W-0/u
R/W-0/u
T1CKPS<1:0>
R/W-0/u
R/W-0/u
U-0
R/W-0/u
T1OSCEN
T1SYNC
TMR1ON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-4
bit 3
bit 2
bit 1
Unimplemented: Read as 0
bit 0
DS40001729B-page 254
PIC16(L)F1705/9
REGISTER 25-2:
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
R/W/HC-0/u
R-x/x
TMR1GE
T1GPOL
T1GTM
T1GSPM
T1GGO/
DONE
T1GVAL
R/W-0/u
R/W-0/u
T1GSS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
DS40001729B-page 255
PIC16(L)F1705/9
TABLE 25-5:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSELA
ANSA4
ANSA2
ANSA1
ANSA0
122
CCP1CON
DC1B<1:0>
CCP1M<3:0>
CCP2CON
DC2B<1:0>
CCP2M<3:0>
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
84
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
85
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
Name
INTCON
PIE1
PIR1
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
TRISA
T1CON
T1GCON
Legend:
*
Note 1:
TMR1CS<1:0>
TMR1GE
T1GPOL
TRISA5
TRISA4
T1CKPS<1:0>
T1GTM
T1GSPM
269
269
88
246*
246*
(1)
TRISA2
TRISA1
TRISA0
121
T1OSCEN
T1SYNC
TMR1ON
254
T1GGO/
DONE
T1GVAL
T1GSS<1:0>
255
= unimplemented location, read as 0. Shaded cells are not used by the Timer1 module.
Page provides register information.
Unimplemented, read as 1.
DS40001729B-page 256
PIC16(L)F1705/9
26.0
TIMER2/4/6 MODULE
timers
that
FIGURE 26-1:
Fosc/4
Prescaler
1:1, 1:4, 1:16, 1:64
T2_match
TMR2
To Peripherals
2
T2CKPS<1:0>
Comparator
Postscaler
1:1 to 1:16
set bit
TMR2IF
4
PR2
T2OUTPS<3:0>
DS40001729B-page 257
PIC16(L)F1705/9
26.1
Timer2 Operation
26.3
Timer2 Output
26.4
26.2
Timer2 Interrupt
DS40001729B-page 258
PIC16(L)F1705/9
26.5
REGISTER 26-1:
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
T2OUTPS<3:0>
R/W-0/0
R/W-0/0
TMR2ON
bit 7
R/W-0/0
T2CKPS<1:0>
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 0
bit 6-3
bit 2
bit 1-0
DS40001729B-page 259
PIC16(L)F1705/9
TABLE 26-1:
Bit 6
CCP2CON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
84
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
85
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
88
PR2
INTCON
PIE1
T2CON
TMR2
Bit 5
Bit 4
Bit 3
DC2B<1:0>
T2OUTPS<3:0>
Bit 2
Bit 1
Bit 0
Register
on Page
Name
CCP2M<3:0>
269
257*
TMR2ON
T2CKPS<1:0>
259
257*
Legend: = unimplemented location, read as 0. Shaded cells are not used for Timer2 module.
* Page provides register information.
DS40001729B-page 260
PIC16(L)F1705/9
26.6
26.7
REGISTER 26-2:
R/W-0/0
R/W-0/0
R/W-0/0
P4TSEL<1:0>
R/W-0/0
P3TSEL<1:0>
R/W-0/0
R/W-0/0
R/W-0/0
C2TSEL<1:0>
bit 7
R/W-0/0
C1TSEL<1:0>
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-4
bit 3-2
bit 1-0
DS40001729B-page 261
PIC16(L)F1705/9
27.0
CAPTURE/COMPARE/PWM
MODULES
27.1
Capture Mode
27.1.1
FIGURE 27-1:
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
Prescaler
1, 4, 16
CCPx
pin
CCPRxH
and
Edge Detect
CCPRxL
Capture
Enable
TMR1H
TMR1L
CCPxM<3:0>
System Clock (FOSC)
DS40001729B-page 262
PIC16(L)F1705/9
27.1.2
27.1.5
27.1.3
27.1.4
CCP PRESCALER
EXAMPLE 27-1:
27.2
Compare Mode
FIGURE 27-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
CHANGING BETWEEN
CAPTURE PRESCALERS
BANKSEL CCPxCON
CLRF
MOVLW
MOVWF
CCPxM<3:0>
Mode Select
Set CCPxIF Interrupt Flag
(PIRx)
4
CCPRxH CCPRxL
CCPx
Pin
S
R
Output
Logic
Match
Comparator
TMR1H
TRIS
Output Enable
TMR1L
Auto-conversion Trigger
DS40001729B-page 263
PIC16(L)F1705/9
27.2.1
27.2.2
27.2.3
27.2.4
AUTO-CONVERSION TRIGGER
27.2.5
DS40001729B-page 264
PIC16(L)F1705/9
27.3
PWM Overview
FIGURE 27-3:
Period
Pulse Width
27.3.1
TMR2 = 0
FIGURE 27-4:
CCPR1H(2) (Slave)
CCP1
R
Comparator
(1)
TMR2
S
TRIS
Comparator
TMR2 = PR2
TMR2 = CCPRxH:CCPxCON<5:4>
PR2
Note
1:
2:
Clear Timer,
toggle CCP1 pin and
latch duty cycle
PR2 registers
T2CON registers
CCPRxL registers
CCPxCON registers
Note:
DS40001729B-page 265
PIC16(L)F1705/9
27.3.2
2.
3.
4.
5.
6.
27.3.3
TMR2 is cleared
The CCPx pin is set. (Exception: If the PWM duty
cycle = 0%, the pin will not be set.)
The PWM duty cycle is latched from CCPRxL into
CCPRxH.
Note:
27.3.5
EQUATION 27-2:
EQUATION 27-3:
27.3.4
PULSE WIDTH
CCPRxL:CCPxCON<5:4>
Duty Cycle Ratio = ----------------------------------------------------------------------4 PR2 + 1
PWM PERIOD
EQUATION 27-1:
PWM PERIOD
TOSC = 1/FOSC
DS40001729B-page 266
PIC16(L)F1705/9
27.3.6
PWM RESOLUTION
EQUATION 27-4:
TABLE 27-1:
1.22 kHz
Timer Prescale
PR2 Value
Note:
4.88 kHz
19.53 kHz
78.12 kHz
156.3 kHz
208.3 kHz
16
0xFF
0xFF
0xFF
0x3F
0x1F
0x17
10
10
10
6.6
PWM Frequency
1.22 kHz
4.90 kHz
19.61 kHz
76.92 kHz
153.85 kHz
200.0 kHz
16
0x65
0x65
0x65
0x19
0x0C
0x09
Timer Prescale
PR2 Value
Maximum Resolution (bits)
27.3.7
log 4 PR2 + 1
Resolution = ------------------------------------------ bits
log 2
PWM Frequency
TABLE 27-2:
PWM RESOLUTION
27.3.8
27.3.9
EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
DS40001729B-page 267
PIC16(L)F1705/9
TABLE 27-3:
Name
CCP1CON
CCPR1L
CCPTMRS
INTCON
Bit 6
Bit 5
Bit 4
Bit 3
DC1B<1:0>
Bit 2
Bit 1
Bit 0
CCP1M<3:0>
269
Register
on Page
266*
P3TSEL<1:0>
C2TSEL<1:0>
GIE
PEIE
TMR0IE
INTE
IOCIE
C1TSEL<1:0>
TMR0IF
INTF
IOCIF
261
84
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
85
PIE2
OSFIE
C2IE
C1IE
BCL1IE
TMR6IE
TMR4IE
CCP2IE
86
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
88
PIR2
OSFIF
C2IF
C1IF
BCL1IF
TMR6IF
TMR4IF
CCP2IF
89
PR2
RxyPPS
T2CON
TMR2
257*
T2OUTPS<3:0>
RxyPPS<4:0>
TMR2ON
141
T2CKPS<1:0>
259
257
Legend: = Unimplemented location, read as 0. Shaded cells are not used by the PWM.
* Page provides register information.
DS40001729B-page 268
PIC16(L)F1705/9
27.4
REGISTER 27-1:
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
DCxB<1:0>
R/W-0/0
R/W-0/0
R/W-0/0
CCPxM<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-4
bit 3-0
0011 =
0010 =
0001 =
0000 =
Reserved
Compare mode: toggle output on match
Reserved
Capture/Compare/PWM off (resets CCPx module)
DS40001729B-page 269
PIC16(L)F1705/9
28.0
MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
28.1
Master mode
Slave mode
Clock Parity
Slave Select Synchronization (Slave mode only)
Daisy-chain connection of slave devices
FIGURE 28-1:
Write
SSPxBUF Reg
SDI
SSPSR Reg
SDO
bit 0
SS
SS Control
Enable
Shift
Clock
2 (CKP, CKE)
Clock Select
Edge
Select
SSPM<3:0>
4
SCK
Edge
Select
TRIS bit
DS40001729B-page 270
T2_match
2
Prescaler TOSC
4, 16, 64
Baud Rate
Generator
(SSPxADD)
PIC16(L)F1705/9
The I2C interface supports the following modes and
features:
Master mode
Slave mode
Byte NACKing (Slave mode)
Limited multi-master support
7-bit and 10-bit addressing
Start and Stop interrupts
Interrupt masking
Clock stretching
Bus collision detection
General call address matching
Address masking
Address Hold and Data Hold modes
Selectable SDA hold times
[SSPM<3:0>]
Write
SSP1BUF
Shift
Clock
SDA in
SCL
SCL in
Bus Collision
LSb
Clock Cntl
SSPSR
MSb
SDA
Baud Rate
Generator
(SSPxADD)
FIGURE 28-2:
DS40001729B-page 271
PIC16(L)F1705/9
FIGURE 28-3:
Write
SSPxBUF Reg
SCL
Shift
Clock
SSPSR Reg
SDA
MSb
LSb
SSPMSK Reg
Match Detect
Addr Match
SSPxADD Reg
Start and
Stop bit Detect
DS40001729B-page 272
Set, Reset
S, P bits
(SSPxSTAT Reg)
PIC16(L)F1705/9
28.2
DS40001729B-page 273
PIC16(L)F1705/9
FIGURE 28-4:
SPI Master
SCK
SCK
SDO
SDI
SDI
SDO
General I/O
General I/O
SS
General I/O
SCK
SDI
SDO
SPI Slave
#1
SPI Slave
#2
SS
SCK
SDI
SDO
SPI Slave
#3
SS
28.2.1
28.2.2
and
The
The
The
DS40001729B-page 274
PIC16(L)F1705/9
The MSSP consists of a transmit/receive shift register
(SSPSR) and a buffer register (SSPxBUF). The
SSPSR shifts the data in and out of the device, MSb
first. The SSPxBUF holds the data that was written to
the SSPSR until the received data is ready. Once the
eight bits of data have been received, that byte is
moved to the SSPxBUF register. Then, the Buffer Full
Detect bit, BF of the SSPxSTAT register, and the
interrupt flag bit, SSPIF, are set. This double-buffering
of the received data (SSPxBUF) allows the next byte to
start reception before reading the data that was just
received. Any write to the SSPxBUF register during
transmission/reception of data will be ignored and the
write collision detect bit WCOL of the SSPxCON1
register, will be set. User software must clear the
WCOL bit to allow the following write(s) to the
SSPxBUF register to complete successfully.
FIGURE 28-5:
SDI
SDI
Shift Register
(SSPSR)
MSb
LSb
SCK
General I/O
Processor 1
SDO
Serial Clock
Slave Select
(optional)
Shift Register
(SSPSR)
MSb
LSb
SCK
SS
Processor 2
DS40001729B-page 275
PIC16(L)F1705/9
28.2.3
DS40001729B-page 276
PIC16(L)F1705/9
FIGURE 28-6:
Write to
SSPxBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
Modes
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
SDO
(CKE = 0)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDO
(CKE = 1)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
bit 0
bit 7
Input
Sample
(SMP = 1)
SSPIF
SSPSR to
SSPxBUF
28.2.4
28.2.4.1
Daisy-Chain Configuration
DS40001729B-page 277
PIC16(L)F1705/9
28.2.5
SLAVE SELECT
SYNCHRONIZATION
FIGURE 28-7:
SPI Master
SCK
SCK
SDO
SDI
SDI
General I/O
SDO
SPI Slave
#1
SS
SCK
SDI
SDO
SPI Slave
#2
SS
SCK
SDI
SDO
SPI Slave
#3
SS
DS40001729B-page 278
PIC16(L)F1705/9
FIGURE 28-8:
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPxBUF
SSPxBUF to
SSPSR
SDO
bit 7
bit 6
bit 7
SDI
bit 6
bit 0
bit 0
bit 7
bit 7
Input
Sample
SSPIF
Interrupt
Flag
SSPSR to
SSPxBUF
DS40001729B-page 279
PIC16(L)F1705/9
FIGURE 28-9:
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPxBUF
Valid
SDO
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDI
bit 0
bit 7
Input
Sample
SSPIF
Interrupt
Flag
SSPSR to
SSPxBUF
Write Collision
detection active
FIGURE 28-10:
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPxBUF
Valid
SDO
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDI
bit 7
bit 0
Input
Sample
SSPIF
Interrupt
Flag
SSPSR to
SSPxBUF
Write Collision
detection active
DS40001729B-page 280
PIC16(L)F1705/9
28.2.6
TABLE 28-1:
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSELA
ANSA4
ANSA2
ANSA1
ANSA0
122
ANSELC
ANSC7(2)
ANSC6(2)
ANSC5(3)
ANSC4(3)
ANSC3
ANSC2
ANSC1
ANSC0
133
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
84
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
85
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
88
RxyPPS
RxyPPS<4:0>
141
SSPCLKPPS
SSPCLKPPS<4:0>
139, 140
SSPDATPPS
SSPDATPPS<4:0>
139, 140
SSPSSPPS
SSPSSPPS<4:0>
139, 140
SSP1BUF
274*
SSP1CON1
WCOL
SSPOV
SSPEN
CKP
SSP1CON3
ACKTIM
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
318
SSP1STAT
SMP
CKE
D/A
R/W
UA
BF
318
121
TRISA
TRISB(2)
TRISC
Legend:
*
Note 1:
2:
3:
SSPM<3:0>
(1)
319
TRISA5
TRISA4
TRISA2
TRISA1
TRISA0
TRISB7
TRISB6
TRISB5
TRISB4
127
TRISC7(2)
TRISC6(2)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
132
= Unimplemented location, read as 0. Shaded cells are not used by the MSSP in SPI mode.
Page provides register information.
Unimplemented, read as 1.
PIC16(L)F1709 only.
PIC16(L)F1705 only.
DS40001729B-page 281
PIC16(L)F1705/9
28.3
VDD
SCL
DS40001729B-page 282
I2C MASTER/
SLAVE CONNECTION
FIGURE 28-11:
SCL
VDD
Master
Slave
SDA
SDA
PIC16(L)F1705/9
When one device is transmitting a logical one, or letting
the line float, and a second device is transmitting a
logical zero, or holding the line low, the first device can
detect that the line is not a logical one. This detection,
when used on the SCL line, is called clock stretching.
Clock stretching gives slave devices a mechanism to
control the flow of data. When this detection is used on
the SDA line, it is called arbitration. Arbitration ensures
that there is only one master device communicating at
any single time.
28.3.1
CLOCK STRETCHING
28.3.2
ARBITRATION
Each master device must monitor the bus for Start and
Stop bits. If the device detects that the bus is busy, it
cannot begin a new message until the bus returns to an
Idle state.
However, two master devices may try to initiate a
transmission on or about the same time. When this
occurs, the process of arbitration begins. Each
transmitter checks the level of the SDA data line and
compares it to the level that it expects to find. The first
transmitter to observe that the two levels do not match,
loses arbitration, and must stop transmitting on the
SDA line.
For example, if one transmitter holds the SDA line to a
logical one (lets it float) and a second transmitter holds
it to a logical zero (pulls it low), the result is that the
SDA line will be low. The first transmitter then observes
that the level of the line is different than expected and
concludes that another transmitter is communicating.
The first transmitter to notice this difference is the one
that loses arbitration and must stop driving the SDA
line. If this transmitter is also a master device, it also
must stop driving the SCL line. It then can monitor the
lines for a Stop condition before trying to reissue its
transmission. In the meantime, the other device that
has not noticed any difference between the expected
and actual levels on the SDA line continues with its
original transmission. It can do so without any
complications, because so far, the transmission
appears exactly as expected with no other transmitter
disturbing the message.
Slave Transmit mode can also be arbitrated, when a
master addresses multiple slaves, but this is less
common.
If two master devices are sending a message to two
different slave devices at the address stage, the master
sending the lower slave address always wins
arbitration. When two master devices send messages
to the same slave address, and addresses can
sometimes refer to multiple slaves, the arbitration
process must continue into the data stage.
Arbitration usually occurs very rarely, but it is a
necessary process for proper multi-master support.
DS40001729B-page 283
PIC16(L)F1705/9
28.4
28.4.1
BYTE FORMAT
28.4.2
28.4.3
28.4.4
TABLE 28-2:
TERM
Transmitter
DS40001729B-page 284
PIC16(L)F1705/9
28.4.5
START CONDITION
28.4.7
I2C
The
specification defines a Start condition as a
transition of SDA from a high to a low state while SCL
line is high. A Start condition is always generated by
the master and signifies the transition of the bus from
an Idle to an Active state. Figure 28-12 shows wave
forms for Start and Stop conditions.
28.4.6
RESTART CONDITION
STOP CONDITION
28.4.8
START/STOP CONDITION
INTERRUPT MASKING
FIGURE 28-12:
SDA
SCL
S
Start
P
Change of
Change of
Data Allowed
Data Allowed
Condition
FIGURE 28-13:
Stop
Condition
Sr
Change of
Change of
Data Allowed
Restart
Data Allowed
Condition
DS40001729B-page 285
PIC16(L)F1705/9
28.4.9
ACKNOWLEDGE SEQUENCE
28.5
28.5.1
28.5.1.1
28.5.1.2
DS40001729B-page 286
PIC16(L)F1705/9
28.5.2
SLAVE RECEPTION
28.5.2.1
28.5.2.2
DS40001729B-page 287
DS40001729B-page 288
SSPOV
BF
SSPIF
A7
A6
A5
A4
A3
A2
A1
ACK
D7
D6
D4
D3
D2
D1
SSPxBUF is read
Cleared by software
D5
Receiving Data
D6
First byte
of data is
available
in SSPxBUF
D0 ACK D7
D4
D3
D2
D1
Cleared by software
D5
Receiving Data
D0
ACK = 1
FIGURE 28-14:
SCL
SDA
Receiving Address
PIC16(L)F1705/9
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0)
CKP
SSPOV
BF
SSPIF
SCL
A7
A6
A5
A4
A3
A2
A1
R/W=0 ACK
SEN
2
D6
D5
D4
D3
D2
D1
D0
SSPxBUF is read
Cleared by software
D7
Receive Data
ACK
SEN
3
D5
D4
D3
First byte
of data is
available
in SSPxBUF
D2
D1
Cleared by software
D6
D7
Receive Data
D0
ACK
FIGURE 28-15:
SDA
Receive Address
PIC16(L)F1705/9
DS40001729B-page 289
DS40001729B-page 290
ACKTIM
CKP
ACKDT
BF
SSPIF
Receiving Address
Slave software
clears ACKDT to
Address is
read from
SSBUF
If AHEN = 1:
SSPIF is set
When AHEN=1:
CKP is cleared by hardware
and SCL is stretched
A7 A6 A5 A4 A3 A2 A1
Receiving Data
9
2
ACKTIM cleared by
hardware in 9th
rising edge of SCL
When DHEN=1:
CKP is cleared by
hardware on 8th falling
edge of SCL
SSPIF is set on
9th falling edge of
SCL, after ACK
ACK D7 D6 D5 D4 D3 D2 D1 D0
Received Data
Slave software
sets ACKDT to
not ACK
Cleared by software
D7 D6 D5 D4 D3 D2 D1 D0
ACK
No interrupt
after not ACK
from Slave
ACK=1
Master sends
Stop condition
FIGURE 28-16:
SCL
SDA
PIC16(L)F1705/9
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1)
ACKTIM
CKP
ACKDT
BF
SSPIF
Receiving Address
4
5
6 7
When AHEN = 1;
on the 8th falling edge
of SCL of an address
byte, CKP is cleared
Received
address is loaded into
SSPxBUF
2 3
A7 A6 A5 A4 A3 A2 A1
ACK
Receive Data
2 3
6 7
When DHEN = 1;
on the 8th falling edge
of SCL of a received
data byte, CKP is cleared
Received data is
available on SSPxBUF
Cleared by software
D7 D6 D5 D4 D3 D2 D1 D0
ACK
Receive Data
1
3 4
6 7
Set by software,
release SCL
Slave sends
not ACK
SSPxBUF can be
read any time before
next byte is loaded
D7 D6 D5 D4 D3 D2 D1 D0
ACK
No interrupt after
if not ACK
from Slave
Master sends
Stop condition
FIGURE 28-17:
SCL
SDA
R/W = 0
Master releases
SDA to slave for ACK sequence
PIC16(L)F1705/9
DS40001729B-page 291
PIC16(L)F1705/9
28.5.3
SLAVE TRANSMISSION
28.5.3.2
7-bit Transmission
1.
28.5.3.1
DS40001729B-page 292
D/A
R/W
ACKSTAT
CKP
BF
SSPIF
Receiving Address
Indicates an address
has been received
R/W = 1 Automatic
ACK
Received address
is read from SSPxBUF
A7 A6 A5 A4 A3 A2 A1
Transmitting Data
Automatic
Set by software
Data to transmit is
loaded into SSPxBUF
Cleared by software
D7 D6 D5 D4 D3 D2 D1 D0 ACK
Transmitting Data
CKP is not
held for not
ACK
BF is automatically
cleared after 8th falling
edge of SCL
D7 D6 D5 D4 D3 D2 D1 D0
9
ACK
FIGURE 28-18:
SCL
SDA
Master sends
Stop condition
PIC16(L)F1705/9
DS40001729B-page 293
PIC16(L)F1705/9
28.5.3.3
DS40001729B-page 294
D/A
R/W
ACKTIM
CKP
ACKSTAT
ACKDT
BF
SSPIF
Receiving Address
Slave clears
ACKDT to ACK
address
ACK
When R/W = 1;
CKP is always
cleared after ACK
R/W = 1
Received address
is read from SSPxBUF
When AHEN = 1;
CKP is cleared by hardware
after receiving matching
address.
A7 A6 A5 A4 A3 A2 A1
3
Cleared by software
Set by software,
releases SCL
Data to transmit is
loaded into SSPxBUF
Transmitting Data
Automatic
D7 D6 D5 D4 D3 D2 D1 D0 ACK
ACKTIM is cleared
on 9th rising edge of SCL
Automatic
Transmitting Data
Masters ACK
response is copied
to SSPxSTAT
BF is automatically
cleared after 8th falling
edge of SCL
D7 D6 D5 D4 D3 D2 D1 D0
9
ACK
Master sends
Stop condition
FIGURE 28-19:
SCL
SDA
PIC16(L)F1705/9
DS40001729B-page 295
PIC16(L)F1705/9
28.5.4
3.
4.
5.
6.
7.
8.
28.5.5
DS40001729B-page 296
CKP
UA
BF
SSPIF
0 A9 A8
Set by hardware
on 9th falling edge
When UA = 1;
SCL is held low
ACK
If address matches
SSPxADD it is loaded into
SSPxBUF
A7 A6 A5 A4 A3 A2 A1 A0 ACK
9
1
Data is read
from SSPxBUF
D7 D6 D5 D4 D3 D2 D1 D0 ACK
Receive Data
Set by software,
When SEN = 1;
releasing SCL
CKP is cleared after
9th falling edge of received byte
Receive address is
read from SSPxBUF
Cleared by software
D7 D6 D5 D4 D3 D2 D1 D0 ACK
Receive Data
FIGURE 28-20:
SCL
SDA
Master sends
Stop condition
PIC16(L)F1705/9
DS40001729B-page 297
DS40001729B-page 298
ACKTIM
CKP
UA
ACKDT
BF
A9
A8
Set by hardware
on 9th falling edge
If when AHEN = 1;
on the 8th falling edge
of SCL of an address
byte, CKP is cleared
R/W = 0
ACK
UA
A6
A5
A4
A3
A2
A1
Update to SSPxADD is
not allowed until 9th
falling edge of SCL
SSPxBUF can be
read anytime before
the next received byte
Cleared by software
A7
A0
ACK
UA
D6
D5
D4
D2
D1
Update of SSPxADD,
clears UA and releases
SCL
D3
Receive Data
Cleared by software
D7
Received data
is read from
SSPxBUF
D6 D5
Receive Data
D0 ACK D7
FIGURE 28-21:
SSPIF
SCL
SDA
PIC16(L)F1705/9
I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0)
D/A
R/W
ACKSTAT
CKP
UA
BF
SSPIF
Set by hardware
Indicates an address
has been received
UA indicates SSPxADD
must be updated
SSPxBUF loaded
with received address
SCL
1
3
7 8
After SSPxADD is
updated, UA is cleared
and SCL is released
Cleared by software
A7 A6 A5 A4 A3 A2 A1 A0 ACK
1
4
7 8
Set by hardware
2 3
When R/W = 1;
CKP is cleared on
9th falling edge of SCL
Received address is
read from SSPxBUF
Sr
1 1 1 1 0 A9 A8
ACK
Set by software
releases SCL
Data to transmit is
loaded into SSPxBUF
D7 D6 D5 D4 D3 D2 D1 D0
Master sends
Stop condition
ACK = 1
Master sends
not ACK
FIGURE 28-22:
SDA
Master sends
Restart event
PIC16(L)F1705/9
DS40001729B-page 299
PIC16(L)F1705/9
28.5.6
CLOCK STRETCHING
28.5.6.2
28.5.6.1
FIGURE 28-23:
28.5.6.3
28.5.6.4
Byte NACKing
Any time the CKP bit is cleared, the module will wait
for the SCL line to go low and then hold it. However,
clearing the CKP bit will not assert the SCL output low
until the SCL output is already sampled low.
Therefore, the CKP bit will not assert the SCL line until
an external I2C master device has already asserted
the SCL line. The SCL output will remain low until the
CKP bit is set and all other devices on the I2C bus
have released SCL. This ensures that a write to the
CKP bit will not violate the minimum high time
requirement for SCL (see Figure 28-23).
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA
DX 1
DX
SCL
CKP
Master device
asserts clock
Master device
releases clock
WR
SSPxCON1
DS40001729B-page 300
PIC16(L)F1705/9
28.5.7
respond.
reception
FIGURE 28-24:
and
call
SDA
SCL
S
Receiving Data
ACK
D6
D5
D4
D3
D2
D1
D0
SSPIF
BF (SSPxSTAT<0>)
Cleared by software
GCEN (SSPCON2<7>)
SSPxBUF is read
1
28.5.8
DS40001729B-page 301
PIC16(L)F1705/9
28.6
28.6.1
DS40001729B-page 302
PIC16(L)F1705/9
28.6.2
CLOCK ARBITRATION
FIGURE 28-25:
SDA
DX 1
DX
SCL deasserted but slave holds
SCL low (clock arbitration)
SCL
BRG decrements on
Q2 and Q4 cycles
BRG
Value
03h
02h
01h
03h
02h
28.6.3
DS40001729B-page 303
PIC16(L)F1705/9
28.6.4
FIGURE 28-26:
SDA = 1,
SCL = 1
TBRG
TBRG
SDA
2nd bit
1st bit
TBRG
SCL
S
DS40001729B-page 304
TBRG
PIC16(L)F1705/9
28.6.5
FIGURE 28-27:
Write to SSPCON2
occurs here
SDA = 1,
SCL (no change)
SDA = 1,
SCL = 1
TBRG
TBRG
TBRG
1st bit
SDA
Sr
TBRG
Repeated Start
DS40001729B-page 305
PIC16(L)F1705/9
28.6.6
28.6.6.1
BF Status Flag
28.6.6.3
28.6.6.4
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
28.6.6.2
DS40001729B-page 306
R/W
PEN
SEN
BF (SSPxSTAT<0>)
SSPIF
SCL
SDA
A6
A5
A4
A3
A2
A1
Cleared by software
SSPxBUF written
D7
1
SCL held low
while CPU
responds to SSPIF
ACK = 0
R/W = 0
A7
D5
D4
D3
D2
D1
D0
D6
Cleared by software
ACK
ACKSTAT in
SSPCON2 = 1
FIGURE 28-28:
SEN = 0
PIC16(L)F1705/9
DS40001729B-page 307
PIC16(L)F1705/9
28.6.7
28.6.7.1
BF Status Flag
28.6.7.2
28.6.7.4
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
28.6.7.3
15.
DS40001729B-page 308
RCEN
ACKEN
SSPOV
BF
(SSPxSTAT<0>)
SDA = 0, SCL = 1
while CPU
responds to SSPIF
SSPIF
SCL
SDA
A7
4
5
Cleared by software
A6 A5 A4 A3 A2
7
8
ACK
D0
ACK
RCEN cleared
automatically
5
6
Cleared by software
Cleared in
software
ACK
RCEN cleared
automatically
P
Set SSPIF interrupt
at end of Acknowledge sequence
Bus master
terminates
transfer
Set P bit
(SSPxSTAT<4>)
and SSPIF
PEN bit = 1
written here
D0
RCEN cleared
automatically
D7 D6 D5 D4 D3 D2 D1
Cleared by software
Cleared by software
D7 D6 D5 D4 D3 D2 D1
A1 R/W
RCEN = 1, start
next receive
FIGURE 28-29:
RCEN cleared
automatically
SEN = 0
Write to SSPxBUF occurs here,
ACK from Slave
start XMIT
Write to SSPCON2<4>
to start Acknowledge sequence
SDA = ACKDT (SSPCON2<5>) = 0
PIC16(L)F1705/9
DS40001729B-page 309
PIC16(L)F1705/9
28.6.8
ACKNOWLEDGE SEQUENCE
TIMING
28.6.9
28.6.8.1
28.6.9.1
FIGURE 28-30:
TBRG
SDA
ACK
D0
SCL
SSPIF
SSPIF set at
the end of receive
Cleared in
software
Cleared in
software
SSPIF set at the end
of Acknowledge sequence
FIGURE 28-31:
Write to SSPCON2,
set PEN
Falling edge of
9th clock
TBRG
SCL
SDA
ACK
P
TBRG
TBRG
TBRG
DS40001729B-page 310
PIC16(L)F1705/9
28.6.10
SLEEP OPERATION
28.6.13
28.6.11
EFFECTS OF A RESET
28.6.12
MULTI-MASTER MODE
Address Transfer
Data Transfer
A Start Condition
A Repeated Start Condition
An Acknowledge Condition
FIGURE 28-32:
SDA
SCL
BCLIF
DS40001729B-page 311
PIC16(L)F1705/9
28.6.13.1
FIGURE 28-33:
SDA
SCL
Set SEN, enable Start
condition if SDA = 1, SCL = 1
SEN
BCLIF
SSPIF
SSPIF and BCLIF are
cleared by software
DS40001729B-page 312
PIC16(L)F1705/9
FIGURE 28-34:
TBRG
SDA
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
SCL
SEN
SCL = 0 before BRG time-out,
bus collision occurs. Set BCLIF.
BCLIF
Interrupt cleared
by software
S
SSPIF
FIGURE 28-35:
SDA
Set SSPIF
TBRG
SCL
SEN
BCLIF
SSPIF
SDA = 0, SCL = 1,
set SSPIF
Interrupts cleared
by software
DS40001729B-page 313
PIC16(L)F1705/9
28.6.13.2
FIGURE 28-36:
If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is
complete.
SDA
SCL
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
RSEN
BCLIF
Cleared by software
S
SSPIF
FIGURE 28-37:
TBRG
SDA
SCL
BCLIF
RSEN
S
SSPIF
DS40001729B-page 314
PIC16(L)F1705/9
28.6.13.3
b)
FIGURE 28-38:
TBRG
TBRG
SDA
SDA sampled
low after TBRG,
set BCLIF
SSPIF
FIGURE 28-39:
TBRG
TBRG
SDA
Assert SDA
SCL
PEN
BCLIF
P
SSPIF
DS40001729B-page 315
PIC16(L)F1705/9
TABLE 28-3:
Name
Bit 6
ANSELA
ANSELB(1)
ANSELC
INTCON
Reset
Values on
Page:
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSA4
ANSA2
ANSA1
ANSA0
122
ANSB5
ANSB4
128
ANSC7(1)
ANSC6(1)
ANSC5(2)
ANSC4(2)
ANSC3
ANSC2
ANSC1
ANSC0
133
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
84
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
85
PIE2
OSFIE
C2IE
C1IE
BCL1IE
TMR6IE
TMR4IE
CCP2IE
86
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
88
PIR2
OSFIF
C2IF
C1IF
BCL1IF
TMR6IF
TMR4IF
CCP2IF
RxyPPS
89
RxyPPS<4:0>
141
SSPCLKPPS
SSPCLKPPS<4:0>
139, 140
SSPDATPPS
SSPDATPPS<4:0>
139, 140
SSPSSPPS
SSPSSPPS<4:0>
139, 140
SSP1ADD
ADD<7:0>
SSP1BUF
SSP1CON1
322
274*
WCOL
SSPOV
SSPEN
CKP
SSP1CON2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
320
SSP1CON3
ACKTIM
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
321
SMP
CKE
D/A
R/W
UA
BF
318
TRISA5
TRISA4
(3)
TRISA2
TRISA1
TRISA0
121
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
127
TRISC
TRISC7(1)
TRISC6(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
132
SSP1MSK
SSP1STAT
TRISA
(1)
Legend:
*
Note 1:
2:
3:
SSPM<3:0>
319
MSK<7:0>
322
= unimplemented location, read as 0. Shaded cells are not used by the MSSP module in I C mode.
Page provides register information.
PIC16(L)F1709 only.
PIC16(L)F1705 only.
Unimplemented, read as 1.
DS40001729B-page 316
PIC16(L)F1705/9
28.7
EQUATION 28-1:
FOSC
FCLOCK = ------------------------------------------------ SSPxADD + 1 4
FIGURE 28-40:
SSPM<3:0>
Reload
SSPxADD<7:0>
Reload
Control
SCL
SSPCLK
FOSC/2
TABLE 28-4:
Note:
FOSC
FCY
BRG Value
FCLOCK
(2 Rollovers of BRG)
32 MHz
8 MHz
13h
400 kHz
32 MHz
8 MHz
19h
308 kHz
32 MHz
8 MHz
4Fh
100 kHz
16 MHz
4 MHz
09h
400 kHz
16 MHz
4 MHz
0Ch
308 kHz
16 MHz
4 MHz
27h
100 kHz
4 MHz
1 MHz
09h
100 kHz
Refer to the I/O port electrical specifications in Table 32-4 to ensure the system is designed to support IOL
requirements.
DS40001729B-page 317
PIC16(L)F1705/9
28.8
REGISTER 28-1:
R/W-0/0
R/W-0/0
R-0/0
R-0/0
R-0/0
R-0/0
R-0/0
R-0/0
SMP
CKE
D/A
R/W
UA
BF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
P: Stop bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1 = Indicates that a Stop bit has been detected last (this bit is 0 on Reset)
0 = Stop bit was not detected last
bit 3
S: Start bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1 = Indicates that a Start bit has been detected last (this bit is 0 on Reset)
0 = Start bit was not detected last
bit 2
bit 1
bit 0
DS40001729B-page 318
PIC16(L)F1705/9
REGISTER 28-2:
R/C/HS-0/0
R/C/HS-0/0
R/W-0/0
R/W-0/0
WCOL
SSPOV(1)
SSPEN
CKP
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
SSPM<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
C = User cleared
bit 7
bit 6
bit 5
bit 4
bit 3-0
Note
1:
2:
3:
4:
5:
In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register.
When enabled, these pins must be properly configured as input or output. Use SSPSSPPS, SSPCLKPPS, SSPDATPPS, and RxyPPS
to select the pins.
When enabled, the SDA and SCL pins must be configured as inputs. Use SSPCLKPPS, SSPDATPPS, and RxyPPS to select the pins.
SSPxADD values of 0, 1 or 2 are not supported for I2C mode.
SSPxADD value of 0 is not supported. Use SSPM = 0000 instead.
DS40001729B-page 319
PIC16(L)F1705/9
SSP1CON2: SSP CONTROL REGISTER 2(1)
REGISTER 28-3:
R/W-0/0
R-0/0
R/W-0/0
R/S/HS-0/0
R/S/HS-0/0
R/S/HS-0/0
R/S/HS-0/0
R/W/HS-0/0
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
HC = Cleared by hardware
S = User set
bit 7
GCEN: General Call Enable bit (in I2C Slave mode only)
1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPSR
0 = General call address disabled
bit 6
bit 5
bit 4
ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only)
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence idle
bit 3
bit 2
PEN: Stop Condition Enable bit (in I2C Master mode only)
SCKMSSP Release Control:
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle
bit 1
RSEN: Repeated Start Condition Enable bit (in I2C Master mode only)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
bit 0
Note 1:
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be
set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled).
DS40001729B-page 320
PIC16(L)F1705/9
REGISTER 28-4:
R-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
ACKTIM(3)
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)
If, on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the
BCL1IF bit of the PIR2 register is set, and bus goes idle
1 = Enable slave bus collision interrupts
0 = Slave bus collision interrupts are disabled
bit 1
bit 0
Note 1:
2:
3:
For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set
when a new byte is received and BF = 1, but hardware continues to write the most recent byte to
SSPxBUF.
This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.
The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.
DS40001729B-page 321
PIC16(L)F1705/9
REGISTER 28-5:
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
MSK<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-1
bit 0
REGISTER 28-6:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
ADD<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
Master mode:
bit 7-0
Not used: Unused for Most Significant Address Byte. Bit state of this register is a dont care. Bit
pattern sent by master is fixed by I2C specification and must be equal to 11110. However, those bits
are compared by hardware and are not affected by the value in this register.
bit 2-1
bit 0
bit 0
DS40001729B-page 322
PIC16(L)F1705/9
29.0
ENHANCED UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
FIGURE 29-1:
TXIE
Interrupt
TXIF
TXREG Register
8
MSb
LSb
(8)
TX/CK pin
Pin Buffer
and Control
FOSC
+1
SPBRGH
TX9
BRG16
SPBRGL
Multiplier
x4
x16 x64
SYNC
1 X 0 0
BRGH
X 1 1 0
BRG16
X 1 0 1
TX9D
DS40001729B-page 323
PIC16(L)F1705/9
FIGURE 29-2:
CREN
RX/DT pin
Data
Recovery
FOSC
BRG16
SPBRGH
SPBRGL
Multiplier
x4
x16 x64
SYNC
1 X 0 0
BRGH
X 1 1 0
BRG16
X 1 0 1
Stop
RCIDL
RSR Register
MSb
Pin Buffer
and Control
+1
OERR
(8)
LSb
0 Start
RX9
FERR
RX9D
RCREG Register
8
FIFO
Data Bus
RCIF
RCIE
Interrupt
DS40001729B-page 324
PIC16(L)F1705/9
29.1
29.1.1.2
Transmitting Data
29.1.1.3
29.1.1
29.1.1.4
EUSART ASYNCHRONOUS
TRANSMITTER
29.1.1.1
DS40001729B-page 325
PIC16(L)F1705/9
29.1.1.5
TSR Status
29.1.1.7
29.1.1.6
1.
2.
3.
FIGURE 29-3:
Write to TXREG
BRG Output
(Shift Clock)
TX/CK
pin
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
DS40001729B-page 326
4.
5.
6.
7.
8.
ASYNCHRONOUS TRANSMISSION
Word 1
Start bit
bit 0
bit 1
bit 7/8
Stop bit
Word 1
1 TCY
Word 1
Transmit Shift Reg.
PIC16(L)F1705/9
FIGURE 29-4:
Write to TXREG
Word 2
Word 1
BRG Output
(Shift Clock)
TX/CK
pin
Start bit
bit 0
bit 1
Word 1
1 TCY
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
bit 7/8
Stop bit
Start bit
Word 2
bit 0
1 TCY
Word 1
Transmit Shift Reg.
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 2
Transmit Shift Reg.
Note:
TABLE 29-1:
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register on
Page
ANSA4
ANSA2
ANSA1
ANSA0
122
ANSB5
ANSB4
128
ANSC7(1)
ANSC6(1)
ANSC5(2)
ANSC4(2)
ANSC3
ANSC2
ANSC1
ANSC0
133
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
335
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
84
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
85
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
88
RC1STA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
334
RxyPPS
Name
Bit 7
Bit 6
ANSELA
ANSELB(1)
ANSELC
BAUD1CON
INTCON
RxyPPS<4:0>
141
SP1BRGL
BRG<7:0>
336*
SP1BRGH
BRG<15:8>
336*
TRISA5
TRISA4
(3)
TRISA2
TRISA1
TRISA0
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
127
TRISC
TRISC7(1)
TRISC6(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
132
SYNC
SENDB
BRGH
TRMT
TX9D
TRISA
(2)
TX1REG
TX1STA
Legend:
*
Note 1:
2:
3:
TX9
TXEN
121
325*
333
= unimplemented location, read as 0. Shaded cells are not used for asynchronous transmission.
Page provides register information.
PIC16(L)F1709 only.
PIC16(L)F1705 only.
Unimplemented, read as 1.
DS40001729B-page 327
PIC16(L)F1705/9
29.1.2
EUSART ASYNCHRONOUS
RECEIVER
29.1.2.1
29.1.2.2
Receiving Data
29.1.2.3
Receive Interrupts
DS40001729B-page 328
PIC16(L)F1705/9
29.1.2.4
29.1.2.5
29.1.2.7
Address Detection
29.1.2.6
DS40001729B-page 329
PIC16(L)F1705/9
29.1.2.8
29.1.2.9
1.
FIGURE 29-5:
Rcv Shift
Reg
Rcv Buffer Reg.
RCIDL
ASYNCHRONOUS RECEPTION
Start
bit
bit 0
RX/DT pin
bit 1
Start
bit
Word 1
RCREG
bit 0
Start
bit
bit 7/8
Stop
bit
Word 2
RCREG
Read Rcv
Buffer Reg.
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
DS40001729B-page 330
PIC16(L)F1705/9
TABLE 29-2:
Name
Bit 6
ANSELA
ANSELB(1)
ANSELC
BAUD1CON
Register
on Page
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSA4
ANSA2
ANSA1
ANSA0
122
ANSB5
ANSB4
128
ANSC7(1)
ANSC6(1)
ANSC5(2)
ANSC4(2)
ANSC3
ANSC2
ANSC1
ANSC0
133
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
335
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
84
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
85
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
88
RC1STA
SPEN
RX9
SREN
OERR
RX9D
RxyPPS
INTCON
RC1REG
SP1BRGL
TRISB(1)
TRISC
TX1STA
Legend:
*
Note 1:
2:
3:
ADDEN
328*
FERR
RxyPPS<4:0>
334
141
BRG<7:0>
SP1BRGH
TRISA
CREN
336
BRG<15:8>
336
TRISA5
TRISA4
(3)
TRISA2
TRISA1
TRISA0
121
TRISB7
TRISB6
TRISB5
TRISB4
127
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
132
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
333
(1)
TRISC7
CSRC
(1)
TRISC6
TX9
= unimplemented location, read as 0. Shaded cells are not used for asynchronous reception.
Page provides register information.
PIC16(L)F1709 only.
PIC16(L)F1705 only.
Unimplemented, read as 1.
DS40001729B-page 331
PIC16(L)F1705/9
29.2
DS40001729B-page 332
PIC16(L)F1705/9
29.3
REGISTER 29-1:
R/W-/0
R/W-0/0
CSRC
TX9
R/W-0/0
TXEN
(1)
R/W-0/0
R/W-0/0
R/W-0/0
R-1/1
R/W-0/0
SYNC
SENDB
BRGH
TRMT
TX9D
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
DS40001729B-page 333
PIC16(L)F1705/9
REGISTER 29-2:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R-0/0
R-0/0
R-0/0
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS40001729B-page 334
PIC16(L)F1705/9
REGISTER 29-3:
R-0/0
R-1/1
U-0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
R/W-0/0
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
Unimplemented: Read as 0
bit 1
bit 0
DS40001729B-page 335
PIC16(L)F1705/9
29.4
EXAMPLE 29-1:
CALCULATING BAUD
RATE ERROR
DS40001729B-page 336
PIC16(L)F1705/9
TABLE 29-3:
Configuration Bits
BRG/EUSART Mode
8-bit/Asynchronous
FOSC/[64 (n+1)]
8-bit/Asynchronous
16-bit/Asynchronous
16-bit/Asynchronous
8-bit/Synchronous
16-bit/Synchronous
SYNC
BRG16
BRGH
1
Legend:
FOSC/[16 (n+1)]
FOSC/[4 (n+1)]
TABLE 29-4:
Name
BAUD1CON ABDOVF
RC1STA
SPEN
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
RCIDL
SCKP
BRG16
WUE
ABDEN
335
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
334
SP1BRGL
BRG<7:0>
336
SP1BRGH
BRG<15:8>
336
TX1STA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
333
Legend: = unimplemented location, read as 0. Shaded cells are not used for the Baud Rate Generator.
* Page provides register information.
DS40001729B-page 337
PIC16(L)F1705/9
TABLE 29-5:
BAUD
RATE
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
300
1200
1221
1.73
255
1200
0.00
239
1200
0.00
143
2400
2404
0.16
207
2404
0.16
129
2400
0.00
119
2400
0.00
71
9600
9615
0.16
51
9470
-1.36
32
9600
0.00
29
9600
0.00
17
10417
10417
0.00
47
10417
0.00
29
10286
-1.26
27
10165
-2.42
16
19.2k
19.23k
0.16
25
19.53k
1.73
15
19.20k
0.00
14
19.20k
0.00
57.6k
55.55k
-3.55
57.60k
0.00
57.60k
0.00
115.2k
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
300
300
0.16
207
300
0.00
191
300
0.16
51
1200
1202
0.16
103
1202
0.16
51
1200
0.00
47
1202
0.16
12
2400
2404
0.16
51
2404
0.16
25
2400
0.00
23
9600
9615
0.16
12
9600
0.00
10417
10417
0.00
11
10417
0.00
19.2k
19.20k
0.00
57.6k
57.60k
0.00
115.2k
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
300
1200
2400
9600
9615
0.16
207
9615
0.16
129
9600
0.00
119
9600
0.00
71
10417
10417
0.00
191
10417
0.00
119
10378
-0.37
110
10473
0.53
65
19.2k
19.23k
0.16
103
19.23k
0.16
64
19.20k
0.00
59
19.20k
0.00
35
57.6k
57.14k
-0.79
34
56.82k
-1.36
21
57.60k
0.00
19
57.60k
0.00
11
115.2k
117.64k
2.12
16
113.64k
-1.36
10
115.2k
0.00
115.2k
0.00
DS40001729B-page 338
PIC16(L)F1705/9
TABLE 29-5:
BAUD
RATE
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
1200
1202
0.16
207
1200
0.00
191
300
1202
0.16
0.16
207
51
2400
2404
0.16
207
2404
0.16
103
2400
0.00
95
2404
0.16
25
9600
9615
0.16
51
9615
0.16
25
9600
0.00
23
10417
10417
0.00
47
10417
0.00
23
10473
0.53
21
10417
0.00
19.2k
19231
0.16
25
19.23k
0.16
12
19.2k
0.00
11
57.6k
55556
-3.55
57.60k
0.00
115.2k
115.2k
0.00
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
300.0
0.00
6666
300.0
-0.01
4166
300.0
0.00
3839
300.0
0.00
2303
1200
1200
-0.02
3332
1200
-0.03
1041
1200
0.00
959
1200
0.00
575
2400
2401
-0.04
832
2399
-0.03
520
2400
0.00
479
2400
0.00
287
9600
9615
0.16
207
9615
0.16
129
9600
0.00
119
9600
0.00
71
10417
10417
0.00
191
10417
0.00
119
10378
-0.37
110
10473
0.53
65
19.2k
19.23k
0.16
103
19.23k
0.16
64
19.20k
0.00
59
19.20k
0.00
35
57.6k
57.14k
-0.79
34
56.818
-1.36
21
57.60k
0.00
19
57.60k
0.00
11
115.2k
117.6k
2.12
16
113.636
-1.36
10
115.2k
0.00
115.2k
0.00
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
299.9
-0.02
1666
300.1
0.04
832
300.0
0.00
767
300.5
0.16
207
1200
1199
-0.08
416
1202
0.16
207
1200
0.00
191
1202
0.16
51
2400
2404
0.16
207
2404
0.16
103
2400
0.00
95
2404
0.16
25
9600
9615
0.16
51
9615
0.16
25
9600
0.00
23
10417
10417
0.00
47
10417
0.00
23
10473
0.53
21
10417
0.00
19.2k
19.23k
0.16
25
19.23k
0.16
12
19.20k
0.00
11
57.6k
55556
-3.55
57.60k
0.00
115.2k
115.2k
0.00
DS40001729B-page 339
PIC16(L)F1705/9
TABLE 29-5:
BAUD
RATE
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
1200
300.0
1200
0.00
0.00
26666
6666
300.0
1200
0.00
-0.01
16665
4166
300.0
1200
0.00
0.00
15359
3839
300.0
1200
0.00
0.00
9215
2303
2400
2400
0.01
3332
2400
0.02
2082
2400
0.00
1919
2400
0.00
1151
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
9600
9604
0.04
832
9597
-0.03
520
9600
0.00
479
9600
0.00
287
10417
10417
0.00
767
10417
0.00
479
10425
0.08
441
10433
0.16
264
19.2k
19.18k
-0.08
416
19.23k
0.16
259
19.20k
0.00
239
19.20k
0.00
143
57.6k
57.55k
-0.08
138
57.47k
-0.22
86
57.60k
0.00
79
57.60k
0.00
47
115.2k
115.9k
0.64
68
116.3k
0.94
42
115.2k
0.00
39
115.2k
0.00
23
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
832
300
300.0
0.00
6666
300.0
0.01
3332
300.0
0.00
3071
300.1
0.04
1200
1200
-0.02
1666
1200
0.04
832
1200
0.00
767
1202
0.16
207
2400
2401
0.04
832
2398
0.08
416
2400
0.00
383
2404
0.16
103
9600
9615
0.16
207
9615
0.16
103
9600
0.00
95
9615
0.16
25
10417
10417
191
10417
0.00
95
10473
0.53
87
10417
0.00
23
19.2k
19.23k
0.16
103
19.23k
0.16
51
19.20k
0.00
47
19.23k
0.16
12
57.6k
57.14k
-0.79
34
58.82k
2.12
16
57.60k
0.00
15
115.2k
117.6k
2.12
16
111.1k
-3.55
115.2k
0.00
DS40001729B-page 340
PIC16(L)F1705/9
29.4.1
AUTO-BAUD DETECT
TABLE 29-6:
FIGURE 29-6:
BRG16
BRGH
BRG Base
Clock
BRG ABD
Clock
FOSC/64
FOSC/512
FOSC/16
FOSC/128
FOSC/16
FOSC/128
FOSC/4
FOSC/32
Note:
BRG Value
0000h
RX pin
001Ch
Start
Edge #1
bit 1
bit 0
Edge #2
bit 3
bit 2
Edge #3
bit 5
bit 4
Edge #4
bit 7
bit 6
Edge #5
Stop bit
BRG Clock
Auto Cleared
Set by User
ABDEN bit
RCIDL
RCIF bit
(Interrupt)
Read
RCREG
SPBRGL
XXh
1Ch
SPBRGH
XXh
00h
Note 1:
The ABD sequence requires the EUSART module to be configured in Asynchronous mode.
DS40001729B-page 341
PIC16(L)F1705/9
29.4.2
AUTO-BAUD OVERFLOW
29.4.3.1
Special Considerations
Break Character
1.
2.
3.
29.4.3
AUTO-WAKE-UP ON BREAK
DS40001729B-page 342
PIC16(L)F1705/9
FIGURE 29-7:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Auto Cleared
WUE bit
RX/DT Line
RCIF
Note 1:
FIGURE 29-8:
Q1
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4
OSC1
Auto Cleared
Note 1
RCIF
Sleep Command Executed
Note 1:
2:
Sleep Ends
If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is
still active. This sequence should not depend on the presence of Q clocks.
The EUSART remains in Idle while the WUE bit is set.
DS40001729B-page 343
PIC16(L)F1705/9
29.4.4
29.4.4.1
29.4.5
FIGURE 29-9:
Write to TXREG
BRG Output
(Shift Clock)
TX (pin)
Start bit
bit 0
bit 1
bit 11
Stop bit
Break
TXIF bit
(Transmit
Interrupt Flag)
TRMT bit
(Transmit Shift
Empty Flag)
SENDB
(send Break
control bit)
DS40001729B-page 344
Auto Cleared
PIC16(L)F1705/9
29.5
29.5.1
Clearing the SCKP bit sets the Idle state as low. When
the SCKP bit is cleared, the data changes on the rising
edge of each clock.
29.5.1.3
29.5.1.4
SYNC = 1
CSRC = 1
SREN = 0 (for transmit); SREN = 1 (for receive)
CREN = 0 (for transmit); CREN = 1 (for receive)
SPEN = 1
29.5.1.1
29.5.1.2
1.
2.
3.
4.
5.
6.
Master Clock
7.
8.
Clock Polarity
DS40001729B-page 345
PIC16(L)F1705/9
FIGURE 29-10:
SYNCHRONOUS TRANSMISSION
RX/DT
pin
bit 0
bit 1
Word 1
bit 2
bit 7
bit 0
bit 1
Word 2
bit 7
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
TXREG Reg
Write Word 1
Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit
TXEN bit
Note:
1
Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words.
FIGURE 29-11:
bit 0
bit 1
bit 2
bit 6
bit 7
TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
DS40001729B-page 346
PIC16(L)F1705/9
TABLE 29-7:
Name
Bit 6
ANSELA
ANSELB(1)
ANSELC
BAUD1CON
Register
on Page
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSA4
ANSA2
ANSA1
ANSA0
122
ANSB5
ANSB4
128
ANSC7(1)
ANSC6(1)
ANSC5(2)
ANSC4(2)
ANSC3
ANSC2
ANSC1
ANSC0
133
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
335
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
84
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
85
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
88
RC1STA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
334
RxyPPS
INTCON
RxyPPS<4:0>
SP1BRGL
BRG<7:0>
SP1BRGH
BRG<15:8>
TRISA
TRISB(1)
TRISC
Legend:
*
Note 1:
2:
3:
TRISA4
336
336
(3)
TRISA2
TRISA1
TRISA0
121
TRISB7
TRISB6
TRISB5
TRISB4
127
TRISC7(1)
TRISC6(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
132
TRMT
TX9D
TX1REG
TX1STA
TRISA5
141
TX9
TXEN
SYNC
SENDB
325*
BRGH
333
= unimplemented location, read as 0. Shaded cells are not used for synchronous master transmission.
Page provides register information.
PIC16(L)F1709 only.
PIC16(L)F1705 only.
Unimplemented, read as 1.
DS40001729B-page 347
PIC16(L)F1705/9
29.5.1.5
29.5.1.6
Slave Clock
DS40001729B-page 348
29.5.1.7
29.5.1.8
29.5.1.9
1.
PIC16(L)F1705/9
FIGURE 29-12:
RX/DT
pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
bit SREN
SREN bit
CREN bit 0
RCIF bit
(Interrupt)
Read
RCREG
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
Note:
TABLE 29-8:
Name
Bit 6
ANSELA
ANSELB(1)
ANSELC
BAUD1CON
Register
on Page
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSA4
ANSA2
ANSA1
ANSA0
122
ANSB5
ANSB4
128
ANSC7(1)
ANSC6(1)
ANSC5(2)
ANSC4(2)
ANSC3
ANSC2
ANSC1
ANSC0
133
SCKP
BRG16
WUE
ABDEN
335
ABDOVF
RCIDL
CKPPS
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
84
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
85
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
88
RC1STA
SPEN
RX9
SREN
OERR
RX9D
RXPPS
RXPPS<4:0>
139, 140
RxyPPS
RxyPPS<4:0>
141
RC1REG
CKPPS<4:0>
ADDEN
SP1BRGL
BRG<7:0>
SP1BRGH
BRG<15:8>
TRISA
(1)
139, 140
TRISA5
TRISA4
328*
FERR
334
336*
336*
(3)
TRISA2
TRISA1
TRISA0
121
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
127
TRISC
TRISC7(1)
TRISC6(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
132
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
333
TX1STA
Legend:
*
Note 1:
2:
3:
= unimplemented location, read as 0. Shaded cells are not used for synchronous master reception.
Page provides register information.
PIC16(L)F1709 only.
PIC16(L)F1705 only.
Unimplemented, read as 1.
DS40001729B-page 349
PIC16(L)F1705/9
29.5.2
SYNC = 1
CSRC = 0
SREN = 0 (for transmit); SREN = 1 (for receive)
CREN = 0 (for transmit); CREN = 1 (for receive)
SPEN = 1
29.5.2.1
29.5.2.2
1.
2.
3.
4.
5.
6.
7.
8.
5.
DS40001729B-page 350
PIC16(L)F1705/9
TABLE 29-9:
Name
Bit 6
ANSELA
ANSELB(1)
ANSELC
BAUD1CON
CKPPS
INTCON
Register
on Page
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSA4
ANSA2
ANSA1
ANSA0
122
ANSB5
ANSB4
128
ANSC7(1)
ANSC6(1)
ANSC5(2)
ANSC4(2)
ANSC3
ANSC2
ANSC1
ANSC0
133
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
CKPPS<4:0>
335
139, 140
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
84
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
85
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
88
RC1STA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
334
RXPPS
RXPPS<4:0>
139, 140
RxyPPS
RxyPPS<4:0>
141
TRISA
TRISB(1)
TRISC
TRISA5
TRISA4
(3)
TRISA2
TRISA1
TRISA0
121
TRISB7
TRISB6
TRISB5
TRISB4
127
TRISC7(1)
TRISC6(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
132
TX1REG
TX1STA
Legend:
*
Note 1:
2:
3:
TX9
TXEN
SYNC
SENDB
325*
BRGH
TRMT
TX9D
333
= unimplemented location, read as 0. Shaded cells are not used for synchronous slave transmission.
Page provides register information.
PIC16(L)F1709 only.
PIC16(L)F1705 only.
Unimplemented, read as 1.
DS40001729B-page 351
PIC16(L)F1705/9
29.5.2.3
29.5.2.4
1.
2.
3.
4.
5.
6.
7.
8.
9.
ANSELA
(1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSA4
ANSA2
ANSA1
ANSA0
122
ANSELB
ANSB5
ANSB4
128
ANSELC
ANSC7(1)
ANSC6(1)
ANSC5(2)
ANSC4(2)
ANSC3
ANSC2
ANSC1
ANSC0
133
BAUD1CON
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
335
CKPPS
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
84
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
85
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
RC1REG
CKPPS<4:0>
RC1STA
SPEN
RX9
SREN
RXPPS
TRISA
TRISA5
TRISB(1)
TRISC
TX1STA
Legend:
*
Note 1:
2:
3:
139, 140
CREN
ADDEN
FERR
OERR
RX9D
RXPPS<4:0>
TRISA4
(3)
88
328*
TRISA2
334
139, 140
TRISA1
TRISA0
121
TRISB7
TRISB6
TRISB5
TRISB4
127
TRISC7(1)
TRISC6(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
132
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
333
= unimplemented location, read as 0. Shaded cells are not used for synchronous slave reception.
Page provides register information.
PIC16(L)F1709 only.
PIC16(L)F1705 only.
Unimplemented, read as 1.
DS40001729B-page 352
PIC16(L)F1705/9
29.6
29.6.1
29.6.2
SYNCHRONOUS TRANSMIT
DURING SLEEP
DS40001729B-page 353
PIC16(L)F1705/9
30.0
IN-CIRCUIT SERIAL
PROGRAMMING (ICSP)
30.1
30.2
30.3
FIGURE 30-1:
VDD
ICSPDAT
NC
2 4 6
ICSPCLK
1 3 5
Target
VPP/MCLR
VSS
PC Board
Bottom Side
Pin Description*
1 = VPP/MCLR
2 = VDD Target
3 = VSS (ground)
4 = ICSPDAT
5 = ICSPCLK
6 = No Connect
DS40001729B-page 354
PIC16(L)F1705/9
FIGURE 30-2:
Pin 1 Indicator
Pin Description*
1 = VPP/MCLR
1
2
3
4
5
6
2 = VDD Target
3 = VSS (ground)
4 = ICSPDAT
5 = ICSPCLK
6 = No Connect
FIGURE 30-3:
Device to be
Programmed
VDD
VDD
VDD
VPP
MCLR/VPP
VSS
VSS
Data
ICSPDAT
Clock
ICSPCLK
To Normal Connections
DS40001729B-page 355
PIC16(L)F1705/9
31.0
31.1
Read-Modify-Write Operations
Byte Oriented
Bit Oriented
Literal and Control
TABLE 31-1:
Each instruction is a 14-bit word containing the operation code (opcode) and all required operands. The
opcodes are broken into three broad categories.
OPCODE FIELD
DESCRIPTIONS
Field
f
Description
Register file address (0x00 to 0x7F)
mm
TABLE 31-2:
ABBREVIATION
DESCRIPTIONS
Field
Program Counter
TO
Time-Out bit
C
DC
Z
PD
DS40001729B-page 356
Description
PC
Carry bit
Digit Carry bit
Zero bit
Power-Down bit
PIC16(L)F1705/9
FIGURE 31-1:
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13
10 9
7 6
OPCODE
b (BIT #)
f (FILE #)
General
13
OPCODE
0
k (literal)
OPCODE
k (literal)
0
k (literal)
5 4
0
k (literal)
0
k (literal)
6
n
0
k (literal)
n = appropriate FSR
k = 6-bit immediate value
FSR Increment instructions
13
OPCODE
2 1
0
n m (mode)
n = appropriate FSR
m = 2-bit mode value
OPCODE only
13
0
OPCODE
DS40001729B-page 357
PIC16(L)F1705/9
TABLE 31-3:
Mnemonic,
Operands
Description
Cycles
MSb
LSb
Status
Affected
Notes
ADDWF
ADDWFC
ANDWF
ASRF
LSLF
LSRF
CLRF
CLRW
COMF
DECF
INCF
IORWF
MOVF
MOVWF
RLF
RRF
SUBWF
SUBWFB
SWAPF
XORWF
f, d
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
Add W and f
Add with Carry W and f
AND W with f
Arithmetic Right Shift
Logical Left Shift
Logical Right Shift
Clear f
Clear W
Complement f
Decrement f
Increment f
Inclusive OR W with f
Move f
Move W to f
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Subtract with Borrow W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
00
11
00
11
11
11
00
00
00
00
00
00
00
00
00
00
00
11
00
00
0111
1101
0101
0111
0101
0110
0001
0001
1001
0011
1010
0100
1000
0000
1101
1100
0010
1011
1110
0110
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0000
dfff
dfff
dfff
dfff
dfff
1fff
dfff
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
00xx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
C, DC, Z
C, DC, Z
Z
C, Z
C, Z
C, Z
Z
Z
Z
Z
Z
Z
Z
C
C
C, DC, Z
C, DC, Z
Z
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
DECFSZ
INCFSZ
f, d
f, d
Decrement f, Skip if 0
Increment f, Skip if 0
BCF
BSF
f, b
f, b
Bit Clear f
Bit Set f
1(2)
1(2)
00
00
1, 2
1, 2
1
1
01
01
2
2
1, 2
1, 2
BTFSC
BTFSS
f, b
f, b
1 (2)
1 (2)
01
01
1
1
1
1
1
1
1
1
11
11
11
00
11
11
11
11
1110
1001
1000
0000
0001
0000
1100
1010
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
MOVLB
MOVLP
MOVLW
SUBLW
XORLW
k
k
k
k
k
k
k
k
Note 1:
If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
2:
DS40001729B-page 358
kkkk
kkkk
kkkk
001k
1kkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
C, DC, Z
Z
Z
C, DC, Z
Z
PIC16(L)F1705/9
TABLE 31-3:
Mnemonic,
Operands
Description
Cycles
MSb
LSb
Status
Affected
Notes
CONTROL OPERATIONS
BRA
BRW
CALL
CALLW
GOTO
RETFIE
RETLW
RETURN
k
k
k
Relative Branch
Relative Branch with W
Call Subroutine
Call Subroutine with W
Go to address
Return from interrupt
Return with literal in W
Return from Subroutine
2
2
2
2
2
2
2
2
CLRWDT
NOP
OPTION
RESET
SLEEP
TRIS
ADDFSR
MOVIW
n, k
n mm
MOVWI
k[n]
n mm
11
00
10
00
10
00
11
00
001k
0000
0kkk
0000
1kkk
0000
0100
0000
kkkk
0000
kkkk
0000
kkkk
0000
kkkk
0000
kkkk
1011
kkkk
1010
kkkk
1001
kkkk
1000
00
00
00
00
00
00
0000
0000
0000
0000
0000
0000
0110
0000
0110
0000
0110
0110
0100 TO, PD
0000
0010
0001
0011 TO, PD
0fff
INHERENT OPERATIONS
1
1
1
1
1
1
C-COMPILER OPTIMIZED
k[n]
Note 1:
2:
3:
1
1
11
00
2, 3
1
1
11
00
2
2, 3
11
If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
See Table in the MOVIW and MOVWI instruction descriptions.
DS40001729B-page 359
PIC16(L)F1705/9
31.2
Instruction Descriptions
ADDFSR
ANDLW
Syntax:
Syntax:
[ label ] ANDLW
Operands:
-32 k 31
n [ 0, 1]
Operands:
0 k 255
Operation:
FSR(n) + k FSR(n)
Status Affected:
None
Description:
Operation:
Status Affected:
Description:
ANDWF
AND W with f
ADDLW
Syntax:
[ label ] ADDLW
Operands:
0 k 255
Operation:
Status Affected:
Syntax:
[ label ] ANDWF
Operands:
0 f 127
d 0,1
(W) + k (W)
Operation:
C, DC, Z
Status Affected:
Description:
Description:
ASRF
ADDWF
Add W and f
Syntax:
[ label ] ADDWF
Operands:
0 f 127
d 0,1
Operation:
Status Affected:
C, DC, Z
Description:
ADDWFC
f,d
Syntax:
[ label ] ADDWFC
Operands:
0 f 127
d [0,1]
Operation:
Syntax:
[ label ] ASRF
Operands:
0 f 127
d [0,1]
f {,d}
Operation:
(f<7>) dest<7>
(f<7:1>) dest<6:0>,
(f<0>) C,
Status Affected:
C, Z
Description:
f {,d}
Status Affected:
C, DC, Z
Description:
Add W, the Carry flag and data memory location f. If d is 0, the result is
placed in W. If d is 1, the result is
placed in data memory location f.
DS40001729B-page 360
f,d
PIC16(L)F1705/9
BCF
Bit Clear f
Syntax:
[ label ] BCF
BTFSC
f,b
Syntax:
Operands:
0 f 127
0b7
Operands:
Operation:
0 (f<b>)
Operation:
skip if (f<b>) = 0
Status Affected:
None
Status Affected:
None
Description:
Description:
BRA
Relative Branch
BTFSS
Syntax:
Syntax:
Operands:
0 f 127
0b<7
Operands:
Operation:
skip if (f<b>) = 1
Operation:
(PC) + 1 + k PC
Status Affected:
None
Status Affected:
None
Description:
Description:
BRW
Syntax:
[ label ] BRW
Operands:
None
Operation:
(PC) + (W) PC
Status Affected:
None
Description:
BSF
Bit Set f
Syntax:
[ label ] BSF
Operands:
0 f 127
0b7
f,b
Operation:
1 (f<b>)
Status Affected:
None
Description:
DS40001729B-page 361
PIC16(L)F1705/9
CALL
Call Subroutine
CLRWDT
Syntax:
[ label ] CALL k
Syntax:
[ label ] CLRWDT
Operands:
0 k 2047
Operands:
None
Operation:
(PC)+ 1 TOS,
k PC<10:0>,
(PCLATH<6:3>) PC<14:11>
Operation:
Status Affected:
None
00h WDT
0 WDT prescaler,
1 TO
1 PD
Description:
Status Affected:
TO, PD
Description:
CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler
of the WDT. Status bits TO and PD
are set.
CALLW
COMF
Complement f
Syntax:
[ label ] CALLW
Syntax:
[ label ] COMF
Operands:
None
Operands:
Operation:
(PC) +1 TOS,
(W) PC<7:0>,
(PCLATH<6:0>) PC<14:8>
0 f 127
d [0,1]
Operation:
(f) (destination)
Status Affected:
Description:
DECF
Decrement f
Syntax:
Status Affected:
None
Description:
CLRF
Clear f
Syntax:
[ label ] CLRF
f,d
Operands:
0 f 127
Operands:
Operation:
00h (f)
1Z
0 f 127
d [0,1]
Operation:
(f) - 1 (destination)
Status Affected:
Status Affected:
Description:
Description:
CLRW
Clear W
Syntax:
[ label ] CLRW
Operands:
None
Operation:
00h (W)
1Z
Status Affected:
Description:
DS40001729B-page 362
PIC16(L)F1705/9
DECFSZ
Decrement f, Skip if 0
INCFSZ
Increment f, Skip if 0
Syntax:
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f) - 1 (destination);
skip if result = 0
Operation:
(f) + 1 (destination),
skip if result = 0
Status Affected:
None
Status Affected:
None
Description:
Description:
GOTO
Unconditional Branch
IORLW
Syntax:
[ label ]
Syntax:
[ label ]
GOTO k
INCFSZ f,d
IORLW k
Operands:
0 k 2047
Operands:
0 k 255
Operation:
k PC<10:0>
PCLATH<6:3> PC<14:11>
Operation:
Status Affected:
Status Affected:
None
Description:
Description:
INCF
Increment f
IORWF
Inclusive OR W with f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
INCF f,d
Operands:
0 f 127
d [0,1]
Operation:
(f) + 1 (destination)
Operation:
Status Affected:
Status Affected:
Description:
Description:
IORWF
f,d
DS40001729B-page 363
PIC16(L)F1705/9
LSLF
MOVF
f {,d}
Move f
Syntax:
[ label ] LSLF
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f<7>) C
(f<6:0>) dest<7:1>
0 dest<0>
Operation:
(f) (dest)
Status Affected:
C, Z
Description:
register f
Status Affected:
Description:
Words:
Cycles:
Example:
Syntax:
[ label ] LSRF
Operands:
0 f 127
d [0,1]
Operation:
0 dest<7>
(f<7:1>) dest<6:0>,
(f<0>) C,
Status Affected:
C, Z
Description:
DS40001729B-page 364
f {,d}
register f
MOVF
FSR, 0
After Instruction
W = value in FSR register
Z = 1
LSRF
MOVF f,d
PIC16(L)F1705/9
MOVIW
Move INDFn to W
Syntax:
Operands:
n [0,1]
mm [00,01, 10, 11]
-32 k 31
Operation:
INDFn W
Effective address is determined by
FSR + 1 (preincrement)
FSR - 1 (predecrement)
FSR + k (relative offset)
After the Move, the FSR value will be
either:
FSR + 1 (all increments)
FSR - 1 (all decrements)
Unchanged
Status Affected:
MOVLP
Syntax:
[ label ] MOVLP k
Operands:
0 k 127
Operation:
k PCLATH
Status Affected:
None
Description:
MOVLW
Move literal to W
Syntax:
[ label ]
0 k 255
Operation:
k (W)
Status Affected:
None
Description:
The 8-bit literal k is loaded into W register. The dont cares will assemble as
0s.
Words:
1
1
Mode
Syntax
mm
Cycles:
Preincrement
++FSRn
00
Example:
--FSRn
01
Postincrement
FSRn++
10
Postdecrement
FSRn--
11
Description:
MOVLB
Syntax:
[ label ] MOVLB k
Operands:
0 k 31
Operation:
k BSR
Status Affected:
None
Description:
MOVLW k
Operands:
Predecrement
MOVLW
0x5A
After Instruction
W =
MOVWF
Move W to f
Syntax:
[ label ]
MOVWF
Operands:
0 f 127
Operation:
(W) (f)
0x5A
Status Affected:
None
Description:
Words:
Cycles:
Example:
MOVWF
OPTION_REG
Before Instruction
OPTION_REG = 0xFF
W = 0x4F
After Instruction
OPTION_REG = 0x4F
W = 0x4F
DS40001729B-page 365
PIC16(L)F1705/9
MOVWI
Move W to INDFn
Syntax:
Operands:
Operation:
Status Affected:
n [0,1]
mm [00,01, 10, 11]
-32 k 31
W INDFn
Effective address is determined by
FSR + 1 (preincrement)
FSR - 1 (predecrement)
FSR + k (relative offset)
After the Move, the FSR value will be
either:
FSR + 1 (all increments)
FSR - 1 (all decrements)
Unchanged
None
No Operation
Syntax:
[ label ]
Operands:
None
Operation:
No operation
Status Affected:
None
Description:
No operation.
Words:
Cycles:
Example:
OPTION
Syntax:
[ label ] OPTION
Operands:
None
Operation:
(W) OPTION_REG
Status Affected:
None
Description:
Syntax
Preincrement
++FSRn
00
Predecrement
--FSRn
01
Postincrement
FSRn++
10
Words:
Postdecrement
FSRn--
11
Cycles:
Example:
OPTION
Before Instruction
OPTION_REG = 0xFF
W = 0x4F
After Instruction
OPTION_REG = 0x4F
W = 0x4F
DS40001729B-page 366
NOP
NOP
Mode
Description:
mm
NOP
RESET
Software Reset
Syntax:
[ label ] RESET
Operands:
None
Operation:
Status Affected:
None
Description:
PIC16(L)F1705/9
RETFIE
RETURN
Syntax:
[ label ]
Syntax:
[ label ]
None
RETFIE k
RETURN
Operands:
None
Operands:
Operation:
TOS PC,
1 GIE
Operation:
TOS PC
Status Affected:
None
Status Affected:
None
Description:
Description:
Words:
Cycles:
Example:
RETFIE
After Interrupt
PC =
GIE =
TOS
1
RETLW
Syntax:
[ label ]
Operands:
0 k 255
Operation:
k (W);
TOS PC
Status Affected:
None
Description:
Words:
Cycles:
Example:
TABLE
RETLW k
RLF
Syntax:
[ label ]
Operands:
0 f 127
d [ 0, 1]
Operation:
Status Affected:
Description:
RLF
C
CALL TABLE;W contains table
;offset value
ADDWF PC ;W = offset
RETLW k1 ;Begin table
RETLW k2 ;
Before Instruction
W =
After Instruction
W =
Words:
Cycles:
Example:
RLF
f,d
Register f
REG1,0
Before Instruction
REG1
C
After Instruction
REG1
W
C
=
=
1110 0110
0
=
=
=
1110 0110
1100 1100
1
0x07
value of k8
DS40001729B-page 367
PIC16(L)F1705/9
SUBLW
Syntax:
[ label ]
RRF
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 k 255
Operation:
k - (W) W)
Operation:
Status Affected:
C, DC, Z
Status Affected:
Description:
Description:
RRF f,d
Register f
SUBLW k
C=0
Wk
C=1
Wk
DC = 0
W<3:0> k<3:0>
DC = 1
W<3:0> k<3:0>
SLEEP
SUBWF
Subtract W from f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operation:
Status Affected:
C, DC, Z
Description:
SLEEP
Operands:
None
Operation:
00h WDT,
0 WDT prescaler,
1 TO,
0 PD
Status Affected:
TO, PD
Description:
DS40001729B-page 368
SUBWF f,d
C=0
Wf
C=1
Wf
DC = 0
W<3:0> f<3:0>
DC = 1
W<3:0> f<3:0>
SUBWFB
Syntax:
SUBWFB
Operands:
0 f 127
d [0,1]
Operation:
f {,d}
Status Affected:
C, DC, Z
Description:
PIC16(L)F1705/9
SWAPF
Swap Nibbles in f
XORLW
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operation:
SWAPF f,d
(f<3:0>) (destination<7:4>),
(f<7:4>) (destination<3:0>)
Status Affected:
None
Description:
Operands:
0 k 255
Operation:
(W) .XOR. k W)
Status Affected:
Description:
XORWF
TRIS
XORLW k
Exclusive OR W with f
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
XORWF
f,d
Syntax:
[ label ] TRIS f
Operands:
5f7
Operation:
Operation:
Status Affected:
Status Affected:
None
Description:
Description:
DS40001729B-page 369
PIC16(L)F1705/9
32.0
ELECTRICAL SPECIFICATIONS
32.1
2:
Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be
limited by the device package power dissipation characterizations, see Table 32-3 to calculate device
specifications.
Power dissipation is calculated as follows:
PDIS = VDD x {IDD IOH} + {VDD VOH) x IOH} + (VOL x IOI).
NOTICE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.
DS40001729B-page 370
PIC16(L)F1705/9
32.2
The standard operating conditions for any device are defined as:
Operating Voltage:
Operating Temperature:
DS40001729B-page 371
PIC16(L)F1705/9
VOLTAGE FREQUENCY GRAPH, -40C TA +125C, PIC16F1705/9 ONLY
FIGURE 32-1:
VDD (V)
5.5
2.5
2.3
0
10
16
32
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table for each Oscillator modes supported frequencies.
VDD (V)
FIGURE 32-2:
3.6
2.5
1.8
0
10
16
32
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table for each Oscillator modes supported frequencies.
DS40001729B-page 372
PIC16(L)F1705/9
32.3
DC Characteristics
TABLE 32-1:
SUPPLY VOLTAGE
PIC16LF1705/9
PIC16F1705/9
Param.
No.
D001
Sym.
VDD
Characteristic
Min.
Typ.
Max.
Units
PIC16LF1705/9
1.8
2.5
3.6
3.6
V
V
FOSC 16 MHz
FOSC 32 MHz (Note 2)
PIC16F1705/9
2.3
2.5
5.5
5.5
V
V
FOSC 16 MHz:
FOSC 32 MHz (Note 2)
Supply Voltage
D001
D002*
VDR
1.5
PIC16F1705/9
1.7
PIC16LF1705/9
1.6
PIC16F1705/9
1.6
PIC16LF1705/9
0.8
PIC16F1705/9
1.5
1x gain, 1.024
-4
+4
2x gain, 2.048
-4
+4
-5
+5
0.05
V/ms
D002*
D002A* VPOR
Conditions
D002A*
VFVR
4x gain, 4.096
D004*
SVDD
Note
DS40001729B-page 373
PIC16(L)F1705/9
FIGURE 32-3:
VDD
VPOR
VPORR
SVDD
VSS
NPOR(1)
POR REARM
VSS
TVLOW(2)
Note 1:
2:
3:
DS40001729B-page 374
TPOR(3)
PIC16(L)F1705/9
TABLE 32-2:
PIC16LF1705/9
PIC16F1705/9
Param.
No.
Device
Characteristics
LDO Regulator
Conditions
Min.
Typ.
Max.
Units
Note
VDD
75
15
Sleep, VREGCON<1> = 0
0.3
Sleep, VREGCON<1> = 1
D010
5.0
12
1.8
8.0
18
3.0
D010
16
26
2.3
18
32
3.0
22
35
5.0
D009
D012
D012
D014
D014
D015
D015
D017
D017
D019
D019
Note 1:
2:
3:
4:
5:
160
240
1.8
280
380
3.0
250
320
2.3
320
420
3.0
400
500
5.0
140
180
1.8
240
300
3.0
210
280
2.3
280
350
3.0
360
420
5.0
1.9
2.6
mA
3.0
2.4
3.0
mA
3.6
2.6
mA
3.0
2.2
2.8
mA
5.0
115
170
1.8
135
200
3.0
150
200
2.3
170
220
3.0
215
280
5.0
0.7
1.1
mA
1.8
1.2
1.8
mA
3.0
0.9
1.5
mA
2.3
1.3
1.8
mA
3.0
1.4
2.0
mA
5.0
FOSC = 4 MHz,
External Clock (ECM),
Medium-Power mode
FOSC = 4 MHz,
External Clock (ECM),
Medium-Power mode
FOSC = 32 MHz,
External Clock (ECH),
High-Power mode (Note 5)
FOSC = 32 MHz,
External Clock (ECH),
High-Power mode (Note 5)
FOSC = 500 kHz,
MFINTOSC mode
FOSC = 500 kHz,
MFINTOSC mode
FOSC = 16 MHz,
HFINTOSC mode
FOSC = 16 MHz,
HFINTOSC mode
Data in Typ column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are
not tested.
The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended
by the formula IR = VDD/2REXT (mA) with REXT in k
FVR and BOR are disabled.
8 MHz clock with 4x PLL enabled.
DS40001729B-page 375
PIC16(L)F1705/9
TABLE 32-2:
PIC16LF1705/9
PIC16F1705/9
Param.
No.
Device
Characteristics
D020
D020
D022
D022
Note 1:
2:
3:
4:
5:
Conditions
Min.
Typ.
Max.
Units
VDD
2.3
3.0
mA
3.0
2.8
3.5
mA
3.6
2.4
3.1
mA
3.0
2.6
3.4
mA
5.0
3.0
mA
3.0
2.6
3.5
mA
3.6
2.1
3.0
mA
3.0
3.5
mA
5.0
Note
FOSC = 32 MHz,
HFINTOSC mode (Note 5)
FOSC = 32 MHz,
HFINTOSC mode (Note 5)
FOSC = 32 MHz,
HS Oscillator mode (Note 5)
FOSC = 32 MHz,
HS Oscillator mode (Note 5)
Data in Typ column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are
not tested.
The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended
by the formula IR = VDD/2REXT (mA) with REXT in k
FVR and BOR are disabled.
8 MHz clock with 4x PLL enabled.
DS40001729B-page 376
PIC16(L)F1705/9
TABLE 32-3:
PIC16LF1705/9
PIC16F1705/9
Param.
No.
Device Characteristics
D023
Base IPD
D023
Base IPD
D023A
Base IPD
D024
D024
D025
D025
Conditions
Min.
Typ.
Max.
+85C
Max.
+125C
Units
0.05
1.0
8.0
1.8
0.08
2.0
9.0
3.0
0.3
3.0
10
2.3
0.4
4.0
12
3.0
0.5
6.0
15
5.0
9.8
16
18
2.3
10.3
18
20
3.0
11.5
21
26
5.0
0.5
14
1.8
WDT Current
0.8
17
3.0
0.8
15
2.3
0.9
20
3.0
1.0
22
5.0
15
28
30
1.8
18
30
33
3.0
18
33
35
2.3
19
35
37
3.0
Note
VDD
WDT Current
FVR Current
FVR Current
20
37
39
5.0
D026
7.5
25
28
3.0
BOR Current
D026
10
25
28
3.0
BOR Current
12
28
31
5.0
D027
0.5
10
3.0
LPBOR Current
D027
0.8
14
3.0
LPBOR Current
17
5.0
0.5
1.8
0.8
8.5
12
3.0
1.1
10
2.3
1.3
8.5
20
3.0
1.4
10
25
5.0
0.05
1.8
0.08
10
3.0
0.3
12
2.3
0.4
13
3.0
0.5
16
5.0
D028
D028
D029
D029
Note 1:
2:
3:
SOSC Current
SOSC Current
DS40001729B-page 377
PIC16(L)F1705/9
TABLE 32-3:
PIC16LF1705/9
PIC16F1705/9
Param.
No.
Device Characteristics
D030
D030
Min.
Typ.
Conditions
Max.
+85C
Max.
+125C
Units
VDD
250
1.8
250
3.0
280
2.3
280
3.0
Note
280
5.0
D031
250
650
3.0
Op Amp (High-power)
D031
250
650
3.0
Op Amp (High-power)
350
850
5.0
D032
D032
Note 1:
2:
3:
250
600
1.8
300
650
3.0
280
600
2.3
300
650
3.0
310
650
5.0
Comparator, CxSP = 1
Comparator, CxSP = 1
VREGPM = 0
DS40001729B-page 378
PIC16(L)F1705/9
TABLE 32-4:
I/O PORTS
Sym.
VIL
Characteristic
Min.
Typ.
Max.
Units
Conditions
0.8
0.15 VDD
0.2 VDD
I/O PORT:
D034
D034A
D035
with I C levels
0.3 VDD
0.8
D036
0.2 VDD
(Note 1)
D036A
0.3 VDD
VIH
I/O ports:
D040
2.0
0.25 VDD +
0.8
0.8 VDD
0.7 VDD
D040A
D041
2.1
D042
MCLR
0.8 VDD
D043A
0.7 VDD
D043B
0.9 VDD
125
nA
1000
nA
200
nA
25
100
200
0.6
VDD 0.7
IIL
D060
I/O Ports
MCLR(3)
D061
IPUR
D070*
VOL
D080
(2)
(4)
I/O ports
VOH
D090
I/O ports
Note 1:
2:
3:
4:
DS40001729B-page 379
PIC16(L)F1705/9
TABLE 32-4:
Sym.
Characteristic
Min.
Typ.
Max.
Units
15
pF
50
pF
Conditions
D101*
D101A* CIO
*
Note 1:
2:
3:
4:
DS40001729B-page 380
PIC16(L)F1705/9
TABLE 32-5:
Sym.
Characteristic
Min.
Typ.
Max.
Units
Conditions
Program Memory
Programming Specifications
D110
VIHH
8.0
9.0
D111
IDDP
10
mA
D112
VBE
D113
VPEW
D114
IPPGM
D115
D121
EP
Cell Endurance
D122
VPR
D123
TIW
D124
TRETD
Characteristic Retention
D125
EHEFC
(Note 1, Note 2)
2.7
VDDMAX
VDDMIN
VDDMAX
1.0
mA
5.0
mA
10K
E/W
VDDMIN
VDDMAX
2.5
ms
40
Year
Provided no other
specifications are violated
100K
E/W
0C TA +60C, Lower
byte last 128 addresses
Data in Typ. column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Required only if single-supply programming is disabled.
2: The MPLAB ICD2 does not support variable VPP output. Circuitry to limit the ICD2 VPP voltage must be
placed between the ICD2 and target system when programming or debugging with the ICD2.
3: Self-write and Block Erase.
DS40001729B-page 381
PIC16(L)F1705/9
TABLE 32-6:
THERMAL CHARACTERISTICS
TH01
TH02
TH03
TH04
TH05
Sym.
Characteristic
Typ.
Units
JA
70.0
C/W
JC
TJMAX
PD
Conditions
95.3
C/W
100.0
C/W
51.5
C/W
62.2
C/W
87.3
C/W
77.7
C/W
43.0
C/W
32.75
C/W
31.0
C/W
24.4
C/W
5.4
C/W
27.5
C/W
31.1
C/W
23.1
C/W
5.3
C/W
150
PD = PINTERNAL + PI/O
TH06
PI/O
TH07
PDER
Derated Power
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient Temperature, TJ = Junction Temperature
DS40001729B-page 382
PIC16(L)F1705/9
32.4
AC Characteristics
Timing Parameter Symbology has been created with one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
ck
CLKOUT
cs
CS
di
SDI
do
SDO
dt
Data in
io
I/O PORT
mc
MCLR
Uppercase letters and their meanings:
S
F
Fall
H
High
I
Invalid (High-impedance)
L
Low
FIGURE 32-4:
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCK
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
High-impedance
LOAD CONDITIONS
Load Condition
Pin
CL
VSS
DS40001729B-page 383
PIC16(L)F1705/9
FIGURE 32-5:
CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
CLKIN
OS12
OS02
OS11
OS03
CLKOUT
(CLKOUT Mode)
Note
1:
See Table .
TABLE 32-7:
Sym.
OS01
FOSC
Characteristic
External CLKIN Frequency(1)
Oscillator Frequency
OS02
TOSC
(1)
Oscillator Period(1)
OS03
TCY
OS04*
OS05*
Min.
Typ
Max.
Units
Conditions
DC
0.5
MHz
DC
MHz
DC
32
MHz
32.768
kHz
LP Oscillator mode
0.1
MHz
XT Oscillator mode
MHz
HS Oscillator mode
20
MHz
DC
MHz
27
250
ns
XT Oscillator mode
50
ns
HS Oscillator mode
EC Oscillator mode
LP Oscillator mode
31.25
ns
30.5
LP Oscillator mode
250
10,000
ns
XT Oscillator mode
50
1,000
ns
HS Oscillator mode
250
ns
RC Oscillator mode
125
TCY
DC
ns
TCY = 4/FOSC
LP Oscillator mode
100
ns
XT Oscillator mode
20
ns
HS Oscillator mode
ns
LP Oscillator mode
ns
XT Oscillator mode
ns
HS Oscillator mode
DS40001729B-page 384
PIC16(L)F1705/9
TABLE 32-8:
OSCILLATOR PARAMETERS
Sym.
Characteristic
Freq.
Tolerance
Min.
Typ.
Max.
Units
Conditions
OS08
HFOSC
2%
16.0
MHz
3.2V, TA = 25C
OS08A
MFOSC
2%
500
kHz
3.2V, TA = 25C
OS09
LFOSC
31
kHz
-40C TA +125C
OS10*
TIOSC ST
HFINTOSC
Wake-up from Sleep Start-up Time
3.2
MFINTOSC
Wake-up from Sleep Start-up Time
24
35
FIGURE 32-6:
125
5%
85
Temperature (C)
3%
60
2%
25
0
-20
-40
1.8
5%
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS40001729B-page 385
PIC16(L)F1705/9
TABLE 32-9:
Min.
Typ.
Max.
Units
3.5
MHz
F11
FSYS
16
32
MHz
F12
TRC
ms
CLK
-0.25%
+0.25%
F10
F13*
Characteristic
Conditions
FIGURE 32-7:
Cycle
Write
Fetch
Q1
Q4
Read
Execute
Q2
Q3
FOSC
OS12
OS11
OS20
OS21
CLKOUT
OS19
OS16
OS13
OS18
OS17
I/O pin
(Input)
OS14
OS15
I/O pin
(Output)
New Value
Old Value
OS18, OS19
DS40001729B-page 386
PIC16(L)F1705/9
TABLE 32-10: CLKOUT AND I/O TIMING PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Sym.
Characteristic
Min.
Typ.
Max.
Units
Conditions
TOSH2CKL
70
ns
OS12
TOSH2CKH
FOSC to CLKOUT
72
ns
OS13
TCKL2IOV
20
ns
OS14
TIOV2CKH
TOSC + 200 ns
ns
OS15
TOSH2IOV
50
70*
ns
OS16
TOSH2IOI
50
ns
OS17
TIOV2OSH
20
ns
OS18*
TIOR
40
15
72
32
ns
VDD = 1.8V
3.3V VDD 5.0V
OS19*
TIOF
28
15
55
30
ns
VDD = 1.8V
3.3V VDD 5.0V
OS20*
TINP
25
ns
OS21*
TIOC
25
ns
OS11
(1)
FIGURE 32-8:
VDD
MCLR
30
Internal
POR
PWRT
Time-out
33
32
OSC
Start-up Time
Internal Reset(1)
Watchdog Timer
Reset(1)
34
31
34
I/O pins
Note 1: Asserted low.
DS40001729B-page 387
PIC16(L)F1705/9
TABLE 32-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Sym.
Characteristic
Min.
Conditions
10
16
27
ms
1024
TOSC
TPWRT
40
65
140
ms
34*
TIOZ
2.0
35
VBOR
2.55
2.70
2.85
BORV = 0
2.30
1.80
2.45
1.90
2.60
2.10
V
V
BORV = 1 (PIC16F1705/9)
BORV = 1 (PIC16LF1705/9)
1.80
2.1
2.5
LPBOR = 1
25
75
mV
-40C TA +85C
35
VDD VBOR
30
TMCL
31
32
TOST
33*
35A
36*
VHYST
37*
DS40001729B-page 388
PIC16(L)F1705/9
FIGURE 32-9:
T0CKI
40
41
42
T1CKI
45
46
49
47
TMR0 or
TMR1
FIGURE 32-10:
VDD
VBOR and VHYST
VBOR
37
Reset
(due to BOR)
33(1)
DS40001729B-page 389
PIC16(L)F1705/9
TABLE 32-12: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
40*
Sym.
TT0H
Characteristic
No Prescaler
With Prescaler
41*
TT0L
No Prescaler
With Prescaler
42*
TT0P
T0CKI Period
45*
TT1H
46*
TT1L
47*
TT1P
T1CKI Low
Time
Typ.
Max.
Units
0.5 TCY + 20
ns
10
ns
0.5 TCY + 20
ns
10
ns
Greater of:
20 or TCY + 40
N
ns
0.5 TCY + 20
ns
15
ns
30
ns
Synchronous, No Prescaler
0.5 TCY + 20
ns
15
ns
Asynchronous
30
ns
Greater of:
30 or TCY + 40
N
ns
60
ns
32.4
32.76
8
33.1
kHz
2 TOSC
7 TOSC
48
FT1
49*
Min.
Conditions
N = prescale value
(2, 4, ..., 256)
Timers in Sync
mode
DS40001729B-page 390
PIC16(L)F1705/9
FIGURE 32-11:
CCPx
(Capture mode)
CC01
CC02
CC03
Note:
CC01*
TccL
Characteristic
No Prescaler
With Prescaler
CC02*
TccH
No Prescaler
With Prescaler
CC03*
*
TccP
Min.
Typ.
Max.
Units
0.5 TCY + 20
ns
20
ns
0.5 TCY + 20
ns
20
ns
3 TCY + 40
N
ns
Conditions
N = prescale value
(1, 4 or 16)
DS40001729B-page 391
PIC16(L)F1705/9
FIGURE 32-12:
CLCxINn
CLC
Input time
CLCxINn
CLC
Input time
LCx_in[n](1)
LCx_in[n](1)
CLC01
Note 1:
CLC
Module
LCx_out(1)
CLC
Output time
CLCx
CLC
Module
LCx_out(1)
CLC
Output time
CLCx
CLC02
CLC03
Sym.
Characteristic
Min.
Typ.
Max.
Units
CLC01* TCLCIN
OS17
ns
(Note 1)
CLC02* TCLC
24
12
ns
ns
VDD = 1.8V
VDD > 3.6V
Rise Time
OS18
(Note 2)
Fall Time
OS19
(Note 2)
45
MHz
Conditions
DS40001729B-page 392
PIC16(L)F1705/9
TABLE 32-15: ANALOG-TO-DIGITAL CONVERTER (ADC) CHARACTERISTICS(1,2)
Standard Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = 25C, Single-ended, 2 s TAD, VREF+ = 3V, VREF- = VSS
Param.
Sym.
No.
Characteristic
Min.
Typ.
Max.
Units
Conditions
AD01
NR
Resolution
10
bit
AD02
EIL
Integral Error
1.7
LSb
VREF = 3.0V
AD03
EDL
Differential Error
LSb
AD04
AD05
EGN
AD06
AD07
VAIN
Full-Scale Range
AD08
ZAIN
Recommended Impedance of
Analog Voltage Source
Gain Error
2.5
LSb
VREF = 3.0V
2.0
LSb
VREF = 3.0V
1.8
VDD
VSS
VREF
10
Characteristic
Min.
Typ.
Max.
Units
AD130* TAD
1.0
9.0
1.0
6.0
AD131
11
TAD
TCNV
Conditions
FOSC-based
5.0
0.5 TAD
DS40001729B-page 393
PIC16(L)F1705/9
FIGURE 32-13:
BSF ADCON0, GO
AD133
1 TCY
AD131
Q4
AD130
ADC_clk
9
ADC Data
0
NEW_DATA
OLD_DATA
ADRES
1 TCY
ADIF
GO
Sample
DONE
Sampling Stopped
AD132
FIGURE 32-14:
BSF ADCON0, GO
AD133
1 TCY
AD131
Q4
AD130
ADC_clk
9
ADC Data
OLD_DATA
ADRES
0
NEW_DATA
1 TCY
ADIF
GO
Sample
DONE
AD132
Sampling Stopped
Note 1: If the ADC clock source is selected as FRC, a time of TCY is added before the ADC clock starts. This allows the
SLEEP instruction to be executed.
DS40001729B-page 394
PIC16(L)F1705/9
TABLE 32-17: OPERATIONAL AMPLIFIER (OPA)
Standard Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = 25C, OPAxSP = 1 (High GBWP mode)
Param.
Symbol
No.
Parameters
Min.
Typ.
Max.
Units
MHz
OPA01* GBWP
3.5
OPA02* TON
Turn on Time
10
OPA03* PM
Phase Margin
40
degrees
OPA04* SR
Slew Rate
V/s
OPA05
OFF
Offset
mV
OPA06
CMRR
52
70
dB
OPA07* AOL
90
dB
OPA08
VDD
80
dB
VICM
OPA09* PSRR
*
Conditions
Sym.
Characteristics
Min.
Typ.
Max.
Units
2.5
mV
Comments
CM01
VIOFF
CM02
VICM
VDD
CM03
CMRR
40
50
dB
60
125
ns
Normal-Power mode
measured at VDD/2 (Note 1)
60
110
ns
Normal-Power mode
measured at VDD/2 (Note 1)
85
ns
85
ns
CM04A
CM04B
CM04C
TRESP(1)
CM04D
Normal-Power mode
measured at VDD/2
CM05*
TMC2OV
10
CM06
CHYSTER
Comparator Hysteresis
20
45
75
mV
*
Note 1:
2:
Hysteresis ON High-Power
mode measured at VDD/2
(Note 2)
DS40001729B-page 395
PIC16(L)F1705/9
TABLE 32-19: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = 25C
See Section 33.0 DC and AC Characteristics Graphs and Charts for operating characterization.
Param.
No.
Sym.
Characteristics
Min.
Typ.
Max.
Units
VDD/256
V
LSb
DAC01*
CLSB
Step Size(1)
DAC02*
CACC
Absolute Accuracy
1.5
DAC03*
CR
600
DAC04*
CST
Settling Time(2)
10
*
Note 1:
2:
Comments
Sym.
Characteristics
ZCPINV
ZC02
ZCSRC
Source current
ZC03
ZCSNK
Sink current
ZC04*
ZCISW
ZC05*
ZCOUT
*
Min.
Typ.
Max.
Units
0.75
-600
ZCPINV = VSS
600
ZCPINV = VDD
Comments
DS40001729B-page 396
PIC16(L)F1705/9
FIGURE 32-15:
CK
US121
US121
DT
US122
US120
Note:
Symbol
US120
TCKH2DTV
US121
US122
TCKRF
TDTRF
FIGURE 32-16:
Characteristic
Min.
Max.
Units
Conditions
80
ns
100
ns
45
ns
50
ns
45
ns
50
ns
US125
DT
US126
Note: Refer to Figure 32-4 for load conditions.
Symbol
Characteristic
Min.
Max.
Units
10
ns
15
ns
Conditions
DS40001729B-page 397
PIC16(L)F1705/9
FIGURE 32-17:
SS
SP81
SCK
(CKP = 0)
SP71
SP72
SP78
SP79
SP79
SP78
SCK
(CKP = 1)
SP80
bit 6 - - - - - -1
MSb
SDO
LSb
SP75, SP76
SDI
MSb In
bit 6 - - - -1
LSb In
SP74
SP73
Note: Refer to Figure 32-4 for load conditions.
FIGURE 32-18:
SS
SP81
SCK
(CKP = 0)
SP71
SP72
SP79
SP73
SCK
(CKP = 1)
SP80
SDO
MSb
bit 6 - - - - - -1
SP78
LSb
SP75, SP76
SDI
MSb In
bit 6 - - - -1
LSb In
SP74
Note: Refer to Figure 32-4 for load conditions.
DS40001729B-page 398
PIC16(L)F1705/9
FIGURE 32-19:
SS
SP70
SCK
(CKP = 0)
SP83
SP71
SP72
SP78
SP79
SP79
SP78
SCK
(CKP = 1)
SP80
MSb
SDO
LSb
bit 6 - - - - - -1
SP77
SP75, SP76
SDI
MSb In
bit 6 - - - -1
LSb In
SP74
SP73
Note: Refer to Figure 32-4 for load conditions.
FIGURE 32-20:
SS
SCK
(CKP = 0)
SP71
SP72
SCK
(CKP = 1)
SP80
SDO
MSb
bit 6 - - - - - -1
LSb
SP77
SP75, SP76
SDI
MSb In
bit 6 - - - -1
LSb In
SP74
Note: Refer to Figure 32-4 for load conditions.
DS40001729B-page 399
PIC16(L)F1705/9
TABLE 32-23: SPI MODE REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Symbol
Characteristic
Min.
Typ. Max.
Unit
s
SP70* TSSL2SCH,
TSSL2SCL
2.25 TCY
ns
SP71* TSCH
TCY + 20
ns
TCY + 20
ns
SP72*
TSCL
Conditions
SP73* TDIV2SCH,
TDIV2SCL
100
ns
SP74* TSCH2DIL,
TSCL2DIL
100
ns
SP75* TDOR
10
25
ns
25
50
ns
SP76* TDOF
10
25
ns
SP77* TSSH2DOZ
10
50
ns
SP78* TSCR
10
25
ns
25
50
ns
SP79* TSCF
10
25
ns
SP80* TSCH2DOV,
TSCL2DOV
50
ns
SP83* TSCH2SSH,
TSCL2SSH
145
ns
TCY
ns
50
ns
1.5 TCY + 40
ns
DS40001729B-page 400
PIC16(L)F1705/9
FIGURE 32-21:
SCL
SP93
SP91
SP90
SP92
SDA
Stop
Condition
Start
Condition
Note: Refer to Figure 32-4 for load conditions.
Symbol
SP90*
TSU:STA
SP91*
THD:STA
SP92*
TSU:STO
SP93
Characteristic
Start condition
4700
Setup time
600
Start condition
4000
Hold time
600
Stop condition
4700
Setup time
Hold time
*
Min.
600
4000
600
Conditions
ns
ns
ns
ns
FIGURE 32-22:
SCL
SP100
SP90
SP102
SP101
SP106
SP107
SP91
SDA
In
SP92
SP110
SP109
SP109
SDA
Out
Note: Refer to Figure 32-4 for load conditions.
DS40001729B-page 401
PIC16(L)F1705/9
TABLE 32-25: I2C BUS DATA REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Symbol
SP100*
THIGH
Characteristic
Clock high time
Min.
Max.
Units
Conditions
4.0
0.6
1.5 TCY
4.7
1.3
1.5 TCY
SSP module
SP101*
TLOW
SSP module
SP102*
SP103*
TR
TF
1000
ns
20 +
0.1CB
300
ns
250
ns
20 +
0.1CB
250
ns
ns
SP106*
THD:DAT
0.9
SP107*
TSU:DAT
250
ns
100
ns
SP109*
TAA
3500
ns
ns
SP110*
TBUF
4.7
1.3
400
pF
SP111
*
Note 1:
2:
CB
CB is specified to be from
10-400 pF
CB is specified to be from
10-400 pF
(Note 2)
(Note 1)
Time the bus must be free
before a new transmission can start
DS40001729B-page 402
PIC16(L)F1705/9
33.0
DC AND AC
CHARACTERISTICS GRAPHS
AND CHARTS
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are ensured to operate properly only within the specified range.
Unless otherwise noted, all graphs apply to both the L and LF devices.
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
Typical represents the mean of the distribution at 25C. Maximum, Max., Minimum or Min.
represents (mean + 3) or (mean - 3) respectively, where is a standard deviation, over each
temperature range.
DS40001729B-page 403
PIC16(L)F1705/9
Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 F, TA = 25C.
28
10
Max: 85C + 3
Typical: 25C
Max.
24
Max.
Typical
22
Typical
IDD (A)
7
IDD (A)
Max: 85C + 3
Typical: 25C
26
20
18
5
16
4
14
12
10
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
2.0
2.5
3.0
3.5
VDD (V)
FIGURE 33-1:
IDD, LP Oscillator Mode,
Fosc = 32 kHz, PIC16LF1705/9 Only.
4.5
5.0
5.5
6.0
FIGURE 33-2:
IDD, LP Oscillator Mode,
Fosc = 32 kHz, PIC16F1705/9 Only.
400
400
Typical: 25C
350
4 MHz XT
4 MHz XT
Max: 85C + 3
350
300
300
250
250
IDD (A)
IDD (A)
4.0
VDD (V)
200
150
200
150
1 MHz XT
1 MHz XT
100
100
50
50
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
1.6
1.8
2.0
2.2
2.4
VDD (V)
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 33-3:
IDD Typical, XT and EXTRC
Oscillator, PIC16LF1705/9 Only.
FIGURE 33-4:
IDD Maximum, XT and
EXTRC Oscillator, PIC16LF1705/9 Only.
500
450
4 MHz XT
4 MHz XT
Max: 85C + 3
450
Typical: 25C
400
400
350
350
300
IDD (A)
IDD (A)
300
250
1 MHz XT
200
150
1 MHz XT
250
200
150
100
100
50
50
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 33-5:
IDD Typical, XT and EXTRC
Oscillator, PIC16F1705/9 Only.
DS40001729B-page 404
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 33-6:
IDD Maximum, XT and
EXTRC Oscillator, PIC16F1705/9 Only.
PIC16(L)F1705/9
Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 F, TA = 25C.
12
24
Max: 85C + 3
Typical: 25C
10
Max.
Max: 85C + 3
Typical: 25C
22
Max.
20
Typical
IDD (A)
IDD (A)
8
Typical
6
18
16
4
14
2
12
10
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
2.0
3.8
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
VDD (V)
FIGURE 33-7:
IDD, EC Oscillator LP Mode,
Fosc = 32 MHz, PIC16LF1705/9 Only.
FIGURE 33-8:
IDD, EC Oscillator LP Mode,
Fosc = 32 MHz, PIC16F1705/9 Only.
50
60
45
Max.
40
50
35
45
Max.
Max: 85C + 3
Typical: 25C
55
Max: 85C + 3
Typical: 25C
IDD (A)
IDD (A)
Typical
Typical
30
40
25
35
20
30
15
25
20
10
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
2.0
3.8
2.5
3.0
3.5
4.0
4.5
FIGURE 33-9:
IDD, EC Oscillator LP Mode,
Fosc = 500 kHz, PIC16LF1705/9 Only.
5.5
6.0
FIGURE 33-10:
IDD, EC Oscillator LP Mode,
Fosc = 500 kHz, PIC16F1705/9 Only.
350
350
Typical: 25C
300
4 MHz
Max: 85C + 3
300
4 MHz
250
250
200
IDD (A)
IDD (A)
5.0
VDD (V)
VDD (V)
150
200
150
100
1 MHz
1 MHz
100
50
50
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VDD (V)
FIGURE 33-11:
IDD Typical, EC Oscillator
MP Mode, PIC16LF1705/9 Only.
3.8
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 33-12:
IDD Maximum, EC Oscillator
MP Mode, PIC16LF1705/9 Only.
DS40001729B-page 405
PIC16(L)F1705/9
Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 F, TA = 25C.
450
400
350
400
Typical: 25C
Max: 85C + 3
4 MHz
350
300
4 MHz
250
IDD (A)
IDD (A)
300
200
1 MHz
250
200
1 MHz
150
150
100
100
50
50
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
2.0
2.5
3.0
3.5
4.0
VDD (V)
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 33-13:
IDD Typical, EC Oscillator
MP Mode, PIC16F1705/9 Only.
FIGURE 33-14:
IDD Maximum, EC Oscillator
MP Mode, PIC16F1705/9 Only.
2.5
3.0
32 MHz
Typical: 25C
Max: 85C + 3
2.5
2.0
32 MHz
IDD (mA)
IDD (mA)
2.0
1.5
16 MHz
1.5
1.0
16 MHz
1.0
8 MHz
0.5
8 MHz
0.5
0.0
0.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
1.6
1.8
2.0
2.2
2.4
VDD (V)
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD ((V))
FIGURE 33-15:
IDD Typical, EC Oscillator
HP Mode, PIC16LF1705/9 Only.
FIGURE 33-16:
IDD Maximum, EC Oscillator
HP Mode, PIC16LF1705/9 Only.
2.5
2.5
32 MHz
Max: 85C + 3
Typical: 25C
2.0
32 MHz
2.0
IDD (mA)
IDD (mA)
1.5
16 MHz
1.0
1.5
16 MHz
1.0
8 MHz
8 MHz
0.5
0.5
0.0
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 33-17:
IDD Typical, EC Oscillator
HP Mode, PIC16F1705/9 Only.
DS40001729B-page 406
6.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 33-18:
IDD Maximum, EC Oscillator
HP Mode, PIC16F1705/9 Only.
PIC16(L)F1705/9
Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 F, TA = 25C.
9
24
Max.
Max.
Max: 85C + 3
Typical: 25C
22
IDD (A)
IDD (A)
20
Typical
6
5
4
Typical
18
16
3
14
2
12
1
0
Max: 85C + 3
Typical: 25C
10
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
2.0
2.5
3.0
3.5
VDD (V)
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 33-19:
IDD, LFINTOSC Mode,
Fosc = 31 kHz, PIC16LF1705/9 Only.
FIGURE 33-20:
IDD, LFINTOSC Mode,
Fosc = 31 kHz, PIC16F1705/9 Only.
260
180
Max.
Max: 85C + 3
Typical: 25C
170
Typical
220
Max.
160
200
IDD (A)
150
IDD (A)
Max: 85C + 3
Typical: 25C
240
Typical
140
180
130
160
120
140
110
120
100
100
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
2.0
3.8
2.5
3.0
3.5
FIGURE 33-21:
IDD, MFINTOSC Mode,
Fosc = 500 kHz, PIC16LF1705/9 Only.
4.5
5.0
5.5
6.0
FIGURE 33-22:
IDD, MFINTOSC Mode,
Fosc = 500 kHz, PIC16F1705/9 Only.
1.6
1.6
16 MHz
16 MHz
Typical: 25C
1.4
Max: 85C + 3
1.4
1.2
1.0
IDD (mA)
1.2
IDD (mA)
4.0
VDD (V)
VDD (V)
8 MHz
8 MHz
1.0
0.8
0.8
4 MHz
4 MHz
0.6
0.6
2 MHz
0.4
2 MHz
0.4
1 MHz
1 MHz
0.2
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VDD (V)
FIGURE 33-23:
IDD Typical, HFINTOSC
Mode, PIC16LF1705/9 Only.
3.8
0.2
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 33-24:
IDD Maximum, HFINTOSC
Mode, PIC16LF1705/9 Only.
DS40001729B-page 407
PIC16(L)F1705/9
Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 F, TA = 25C.
1.6
1.6
16 MHz
16 MHz
Typical: 25C
1.4
1.2
1.2
1.0
8 MHz
0.8
IDD (mA)
IDD (mA)
Max: 85C + 3
1.4
4 MHz
2 MHz
0.6
0.8
4 MHz
2 MHz
0.6
1 MHz
0.4
8 MHz
1.0
1 MHz
0.4
0.2
0.2
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
2.0
2.5
3.0
3.5
4.0
VDD (V)
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 33-25:
IDD Typical, HFINTOSC
Mode, PIC16F1705/9 Only.
FIGURE 33-26:
IDD Maximum, HFINTOSC
Mode, PIC16F1705/9 Only.
2.0
2.0
Max: 85C + 3
1.8
Typical: 25C
1.8
20 MHz
1.6
1.6
20 MHz
1.4
1.4
16 MHz
IDD (mA)
IDD (mA)
1.2
16 MHz
1.2
1.0
0.8
0.8
8 MHz
0.6
8 MHz
0.6
1.0
0.4
0.4
4 MHz
4 MHz
0.2
0.2
0.0
0.0
2.4
2.6
2.8
3.0
3.2
3.4
3.6
2.4
3.8
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
VDD (V)
FIGURE 33-27:
IDD Typical, HS Oscillator,
25C, PIC16LF1705/9 Only.
FIGURE 33-28:
IDD Maximum, HS Oscillator,
PIC16LF1705/9 Only.
2.0
2.2
Typical: 25C
1.8
20 MHz
Max: 85C + 3
2.0
20 MHz
1.6
1.8
16 MHz
1.4
1.6
1.2
1.4
IDD (mA)
IDD (mA)
16 MHz
1.0
8 MHz
0.8
0.6
1.2
1.0
8 MHz
0.8
4 MHz
0.4
0.6
0.2
0.4
0.0
0.2
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 33-29:
IDD Typical, HS Oscillator,
25C, PIC16F1705/9 Only.
DS40001729B-page 408
4 MHz
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 33-30:
IDD Maximum, HS Oscillator,
PIC16F1705/9 Only.
PIC16(L)F1705/9
Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 F, TA = 25C.
3.0
3.5
Max.
2.5
3.0
Max.
Typical
2.5
IDD (mA)
IDD (mA)
2.0
1.5
1.0
Typical
2.0
1.5
Typical: 25C
Max: 85C + 3
Typical: 25C
Max: 85C + 3
0.5
1.0
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
2.0
2.5
3.0
3.5
4.0
VDD (V)
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 33-31:
IDD, HS Oscillator, 32 MHz
(8 MHz + 4x PLL), PIC16LF1705/9 Only.
FIGURE 33-32:
IDD, HS Oscillator, 32 MHz
(8 MHz + 4x PLL), PIC16F1705/9 Only.
450
1.2
Max.
400
Max.
1.0
350
0.8
IPD (A)
IDD (nA)
300
250
Max: 85C + 3
Typical: 25C
200
150
Max: 85C + 3
T i l 25C
Typical:
0.6
0.4
Typical
00
100
0.2
50
Typical
0.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
2.0
2.5
3.0
3.5
FIGURE 33-33:
IPD Base, LP Sleep Mode,
PIC16LF1705/9 Only.
4.5
5.0
5.5
6.0
FIGURE 33-34:
IPD Base, LP Sleep Mode
(VREGPM = 1), PIC16F1705/9 Only.
3.0
2.5
Max: 85C + 3
Typical: 25C
Max: 85C + 3
Typical: 25C
2.5
2.0
Max.
Max.
IPD (A)
2.0
IPD (A)
A)
4.0
VDD (V)
VDD (V)
1.5
15
1.5
1.0
1.0
Typical
Typical
0.5
0.5
0.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
0.0
1.5
VDD (V)
FIGURE 33-35:
IPD, Watchdog Timer (WDT),
PIC16LF1705/9 Only.
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 33-36:
IPD, Watchdog Timer (WDT),
PIC16F1705/9 Only.
DS40001729B-page 409
PIC16(L)F1705/9
Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 F, TA = 25C.
35
35
Max: 85C + 3
M
3
Typical: 25C
30
Max.
30
Max.
IDD (nA)
IDD (nA)
25
20
25
Typical
20
Typical
15
15
Max: 85C + 3
Typical: 25C
10
10
5
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
1.5
3.6
2.0
2.5
3.0
3.5
VDD (V)
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 33-37:
IPD, Fixed Voltage Reference
(FVR), PIC16LF1705/9 Only.
FIGURE 33-38:
IPD, Fixed Voltage Reference
(FVR), PIC16F1705/9 Only.
11
13
Max: 85C + 3
M
3
Typical: 25C
10
Max: 85C + 3
Typical: 25C
12
Max.
Max.
11
Typical
IDD (nA)
nA)
IDD (nA)
10
8
Typical
8
7
6
6
5
4
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
2.8
3.0
3.2
3.4
3.6
3.8
4.0
VDD (V)
FIGURE 33-39:
IPD, Brown-Out Reset
(BOR), BORV = 1, PIC16LF1705/9 Only.
4.4
4.6
4.8
5.0
5.2
5.4
5.6
5.4
5.6
FIGURE 33-40:
IPD, Brown-Out Reset
(BOR), BORV = 1, PIC16F1705/9 Only.
1.8
1.8
Max.
1.6
Max: 85C + 3
Typical: 25C
1.6
1.4
Max.
1.4
1.2
1.2
Max: 85C + 3
Typical: 25C
1.0
IDD (A)
IDD (nA)
4.2
VDD (V)
0.8
0.6
1.0
0.8
0.6
Typical
0.4
0.4
0.2
02
0.2
0.0
Typical
0.0
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
VDD (V)
FIGURE 33-41:
IPD, LP Brown-Out Reset
(LPBOR = 0), PIC16LF1705/9 Only.
DS40001729B-page 410
3.7
2.8
3.0
3.2
3.4
3.6
3.8
4.0
4.2
4.4
4.6
4.8
5.0
5.2
VDD (V)
FIGURE 33-42:
IPD, LP Brown-Out Reset
(LPBOR = 0), PIC16F1705/9 Only.
PIC16(L)F1705/9
Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 F, TA = 25C.
7
12
Max: 85C + 3
M
3
Typical: 25C
Max: 85C + 3
Typical: 25C
10
Max.
5
Max.
IDD (A)
A)
IDD (A)
8
4
3
Typical
6
Typical
4
2
2
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
1.5
2.0
2.5
3.0
3.5
4.0
VDD (V)
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 33-43:
IPD, Timer1 Oscillator,
FOSC = 32 kHz, PIC16LF1705/9 Only.
FIGURE 33-44:
IPD, Timer1 Oscillator,
FOSC = 32 kHz, PIC16F1705/9 Only.
900
700
Max: 85C + 3
Typical: 25C
600
Max: 8
M
85C
C + 3
3
Typical: 25C
800
Max.
700
Max.
500
IDD (A)
IDD (A)
A)
600
400
Typical
300
500
Typical
400
300
200
200
100
100
0
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
1.5
3.8
2.0
2.5
3.0
FIGURE 33-45:
IPD, Op Amp, High GBWP
Mode (OPAxSP = 1), PIC16LF1705/9 Only.
4.0
4.5
5.0
5.5
6.0
FIGURE 33-46:
IPD, Op Amp, High GBWP
Mode (OPAxSP = 1), PIC16F1705/9 Only.
1.4
500
Max: 85C + 3
Typical: 25C
450
Max: 85C + 3
Typical: 25C
1.2
Max.
400
Max.
1.0
350
IDD (A)
A)
300
IDD (A)
A)
3.5
VDD (V)
VDD (V)
250
200
150
0.8
0.6
0.4
Typical
100
0.2
50
Typical
0.0
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 33-47:
IPD, ADC Non-Converting,
PIC16LF1705/9 Only.
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 33-48:
IPD, ADC Non-Converting,
PIC16F1705/9 Only.
DS40001729B-page 411
PIC16(L)F1705/9
Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 F, TA = 25C.
800
800
Max: -40C + 3
Typical: 25C
Max: -40C + 3
Typical: 25C
700
Max.
600
600
Typical
IDD (A)
IDD
D (A)
Max.
700
500
Typical
500
400
400
300
300
200
200
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
2.0
2.5
3.0
3.5
VDD (V)
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 33-49:
IPD, Comparator, NP Mode
(CxSP = 1), PIC16LF1705/9 Only.
FIGURE 33-50:
IPD, Comparator, NP Mode
(CxSP = 1), PIC16F1705/9 Only.
5
Graph represents 3 Limits
5
4
-40C
VOL (V)
VOH (V)
3
125C
2
-40C
2
Typical
Typical
125C
1
0
-30
-25
-20
-15
-10
-5
10
20
30
IOH (mA)
FIGURE 33-51:
VOH vs. IOH Over
Temperature, VDD = 5.0V, PIC16F1705/9 Only.
40
IOL (mA)
50
60
70
80
FIGURE 33-52:
VOL vs. IOL Over
Temperature, VDD = 5.0V, PIC16F1705/9 Only.
3.0
3.5
2.5
2.5
VOL (V)
VOH (V)
2.0
2.0
1.5
-40C
Typical
1.5
125C
125C
1.0
Typical
1.0
-40C
0.5
0.5
0.0
0.0
-14
-12
-10
-8
-6
-4
IOH (mA)
FIGURE 33-53:
VOH vs. IOH Over
Temperature, VDD = 3.0V.
DS40001729B-page 412
-2
10
15
20
25
30
IOL (mA)
FIGURE 33-54:
VOL vs. IOL Over
Temperature, VDD = 3.0V.
PIC16(L)F1705/9
Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 F, TA = 25C.
2.0
1.8
Graph represents 3 Limits
1.8
1.6
1.6
1.4
1.4
Vol (V)
VOH (V)
1.2
1.2
125C
1.0
0.8
1.0
125C
Typical
0.8
-40C
Typical
0.6
-40C
0.6
0.4
0.4
0.2
0.2
0.0
-4.0
-3.5
-3.0
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
0.0
FIGURE 33-55:
VOH vs. IOH Over
Temperature, VDD = 1.8V, PIC16LF1705/9 Only.
10
40,000
38,000
38,000
Max.
Max.
36,000
36,000
34,000
34,000
Frequency (Hz)
Typical
Frequency (Hz)
FIGURE 33-56:
VOL vs. IOL Over
Temperature, VDD = 1.8V, PIC16LF1705/9 Only.
40,000
32,000
30,000
Min.
28,000
Typical
32,000
30,000
Min.
28,000
26,000
26,000
24,000
24,000
22,000
22,000
20,000
20,000
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
2.0
3.8
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
VDD (V)
FIGURE 33-57:
LFINTOSC Frequency,
PIC16LF1705/9 Only.
FIGURE 33-58:
LFINTOSC Frequency,
PIC16F1705/9 Only.
24
24
22
22
Max.
Max.
20
20
18
Time (ms)
Time (ms)
5
IOL (mA)
IOH (mA)
Typical
16
18
Typical
16
Min.
Min.
14
14
Max: Typical + 3 (-40C to +125C)
Typical; statistical mean @ 25C
Min: Typical - 3 (-40C to +125C)
12
12
10
10
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
1.6
1.8
2.0
2.2
2.4
2.6
VDD (V)
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 33-59:
WDT Time-Out Period,
PIC16F1705/9 Only.
FIGURE 33-60:
WDT Time-Out Period,
PIC16LF1705/9 Only.
DS40001729B-page 413
PIC16(L)F1705/9
Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 F, TA = 25C.
70
2.00
Max: Typical + 3
Typical: statistical mean
Min: Typical - 3
60
Max.
1.95
Max.
50
Voltage (mV)
Voltage (V)
Typical
1.90
Min.
40
30
Typical
20
1.85
Max: Typical + 3
Typical: statistical mean
Min: Typical - 3
Min.
10
1.80
-60
-40
-20
20
40
60
80
100
120
-60
140
-40
-20
Temperature (C)
( C)
20
40
60
80
100
120
140
Temperature (C)
FIGURE 33-61:
Brown-Out Reset Voltage,
Low Trip Point (BORV = 1), PIC16LF1705/9 Only.
FIGURE 33-62:
Brown-Out Reset Hysteresis,
Low Trip Point (BORV = 1), PIC16LF1705/9 Only.
2.60
70.0
2.55
60.0
Max: Typical + 3
Typical: statistical mean
Min: Typical - 3
Max.
Max.
Typical
50.0
Voltage (mV)
Voltage (V)
2.50
Min.
2.45
40.0
Typical
30.0
2.40
20.0
Max: Typical + 3
Typical: statistical mean
Min: Typical - 3
2.35
Min.
10.0
2.30
-60
-40
-20
20
40
60
80
100
120
0.0
140
-60
-40
-20
Temperature (C)
40
60
80
100
120
140
Temperature (C)
FIGURE 33-63:
Brown-Out Reset Voltage,
High Trip Point (BORV = 1), PIC16F1705/9 Only.
FIGURE 33-64:
Brown-Out Reset Hysteresis,
Low Trip Point (BORV = 1), PIC16F1705/9 Only.
80
2.85
Max: Typical + 3
Typical: statistical mean
Min: Typical - 3
2.80
Max.
60
Voltage (mV)
2.75
Typical
Min.
2.70
Max: Typical + 3
Typical: statistical mean
Min: Typical - 3
70
Max.
Voltage (V)
20
50
Typical
40
30
20
Min.
2.65
10
0
2.60
-60
-40
-20
20
40
60
80
100
120
140
Temperature (C)
FIGURE 33-65:
Brown-Out Reset Voltage,
High Trip Point (BORV = 0).
DS40001729B-page 414
-60
-40
-20
20
40
60
80
100
120
140
Temperature (C)
( C)
FIGURE 33-66:
Brown-Out Reset Hysteresis,
High Trip Point (BORV = 0).
PIC16(L)F1705/9
Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 F, TA = 25C.
2.7
50
Max: Typical + 3
Typical: statistical mean
Min: Typical - 3
2.6
2.5
Max.
40
2.4
35
2.3
Voltage (mV)
Voltage (V)
Max: Typical + 3
Typical: statistical mean
45
Max.
2.2
Typical
2.1
30
25
20
Typical
2.0
15
1.9
10
Min.
1.8
1.7
-60
-40
-20
20
40
60
80
100
120
140
-60
-40
-20
20
Temperature (C)
FIGURE 33-67:
40
FIGURE 33-68:
90
100
120
140
90
Max.
Max.
80
Time (ms)
80
Time (ms)
80
100
100
Typical
70
Min.
Typical
70
60
60
50
50
Min.
40
40
2
2.5
3.5
4.5
5.5
1.6
1.8
2.2
2.4
2.6
2.8
3.2
3.4
3.6
3.8
VDD (V)
VDD (V)
FIGURE 33-69:
PWRT Period,
PIC16F1705/9 Only.
FIGURE 33-70:
PWRT Period,
PIC16LF1705/9 Only.
1.58
1.58
1.70
Max: Typical + 3
Typical: 25C
Min: Typical - 3
1.56
1.56
1.68
Max.
Voltage
Voltage
(V) (V)
Max.
1.66
1.64
Typical
Voltage (V)
60
Temperature (C)
1.62
1.60
Min.
1.58
1.54
1.54
Typical
1.52
1.52
1.5
1.50
Min.
1.48
1.48
1.56
1.54
1.46
Max: Typical + 3 0
1.46 -40 Typical:-20
statistical mean
Max: Typical + 3
Typical: statistical mean
Min: Typical - 3
1.52
20
40
60
80
100
120
75
100
125
150
Temperature (C)
Min: Typical - 3
1.44
1.50
-50
-25
25
50
75
100
125
150
Temperature (C)
FIGURE 33-71:
devices.
-50
-25
25
50
Temperature (C)
FIGURE 33-72:
POR Rearm Voltage,
NP Mode (VREGPM 1 = 0), PIC16F1705/9 Only.
DS40001729B-page 415
PIC16(L)F1705/9
Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 F, TA = 25C.
12
1.4
1.3
10
Max.
1.2
Time (s)
Voltage (V)
8
1.1
Typical
1.0
Max.
6
Typical
0.9
Min.
0.8
Max: Typical + 3
Typical: statistical mean
Min: Typical - 3
0.7
0.6
-50
-25
25
50
75
100
125
1.5
150
2.0
2.5
3.0
3.5
Temperature (C)
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 33-73:
POR Rearm Voltage,
NP Mode, PIC16LF1705/9 Only.
FIGURE 33-74:
VREGPM = 0.
40
50
Max: Typical + 3
Typical: statistical mean @ 25C
45
35
40
Max.
Max.
30
Time (s)
Time (s)
35
30
Typical
25
Typical
25
20
20
15
10
Note:
The FVR Stabiliztion Period applies when coming out of RESET
or exiting sleep mode.
15
10
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
1.6
6.0
1.8
2.0
2.2
2.4
FIGURE 33-75:
VREGPM = 1.
2.8
3.0
3.2
3.4
3.6
3.8
FIGURE 33-76:
FVR Stabilization Period.
PIC16LF1705/9 Only.
1.0
1.0
0.5
DNL (LSb)
0.5
DNL (LSb)
2.6
VDD (V)
VDD (V)
0.0
0.0
-0.5
-0.5
-1.0
-1.0
0
128
256
384
512
640
768
896
1024
Output Code
FIGURE 33-77:
ADC 10-Bit Mode,
Single-Ended DNL, VDD = 3.0V, TAD = 1 S, 25C.
DS40001729B-page 416
128
256
384
512
640
768
896
1024
Output Code
FIGURE 33-78:
ADC 10-Bit Mode,
Single-Ended DNL, VDD = 3.0V, TAD = 4 S, 25C.
PIC16(L)F1705/9
Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 F, TA = 25C.
2.0
1.0
1.0
1.5
1.0
0.5
0.5
INL DNL
(LSb)(LSb)
INL (LSb)
0.5
0.0
0.0
-0.5
0.0
-1.0
-1.5
-0.5
-2.0
-0.5
512
1024
1536
2048
2560
3072
3584
4096
640
768
896
1024
Output Code
-1.0
-1.0
0
128
256
384
512
640
768
896
1024
128
256
384
512
Output Code
Output Code
FIGURE 33-79:
ADC 10-Bit Mode,
Single-Ended INL, VDD = 3.0V, TAD = 1 S, 25C.
FIGURE 33-80:
ADC 10-Bit Mode,
Single-Ended INL, VDD = 3.0V, TAD = 4 S, 25C.
2.5
2
2
1.5
1.5
Min 125C
Max -40C
Min -40C
0.5
Min 25C
-0.5
Min 25C
Min 125C
-1
Max 125C
Max 25C
0.5
INL (LSB)
DNL (LSB)
0
Min 25C
Min -40C
-0.5
Min -40C
-1.5
Min 125C
-1
-2
-1.5
-2.5
5.00E-07
1.00E-06
2.00E-06
4.00E-06
-2
8.00E-06
5.00E-07
1.00E-06
2.00E-06
4.00E-06
8.00E-06
TADs
TADs
FIGURE 33-81:
ADC 10-Bit Mode,
Single-Ended DNL, VDD = 3.0V, VREF = 3.0V.
FIGURE 33-82:
ADC 10-Bit Mode,
Single-Ended INL, VDD = 3.0V, VREF = 3.0V.
2.0
2.0
1.5
Max. 125C
1.5
Max. -40C
Max. 125C
1.0
1.0
Max. -40C
Max. 25C
0.5
0.0
Min. -40C
-0.5
Min. 25C
-1.0
Min. 125C
-1.5
INL (LSB)
DNL (LSB)
Max. 25C
0.5
0.0
Min. -40C
-0.5
Min. 25C
-1.0
Min. 125C
-1.5
-2.0
-2.5
-3.0
-2.0
1.8
2.3
VREF
3.0
FIGURE 33-83:
ADC 10-Bit Mode,
Single-Ended DNL, VDD = 3.0V, TAD = 1 S.
1.8
2.3
VREF
3.0
FIGURE 33-84:
ADC 10-Bit Mode,
Single-Ended INL, VDD = 3.0V, TAD = 1 S.
DS40001729B-page 417
PIC16(L)F1705/9
Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 F, TA = 25C.
900
800
700
Max.
Max.
800
Typical
600
Min.
700
ADC Output Codes
Typical
500
Min.
400
300
200
500
Max: Typical + 3
Typical; statistical mean
Min: Typical - 3
400
Max: Typical + 3
Typical; statistical mean
Min: Typical - 3
100
600
300
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.0
6.0
2.5
3.0
FIGURE 33-85:
Temperature Indicator Initial
Offset, High Range, Temp. = 20C,
PIC16F1705/9 Only.
4.0
4.5
5.0
5.5
6.0
FIGURE 33-86:
Temperature Indicator Initial
Offset, Low Range, Temp. = 20C, PIC16F1705/9
Only.
150
800
ADC VREF+ SET TO VDD
ADC VREF- SET TO GND
100
Typical
600
Max.
Typical
125
Max.
700
Min.
Min.
75
ADC Output Codes
3.5
VDD (V)
VDD (V)
500
400
300
50
25
0
-25
Max: Typical + 3
Typical; statistical mean
Min: Typical - 3
200
100
1.5
1.8
2.1
2.4
2.7
3.0
3.3
Max: Typical + 3
Typical; statistical mean
Min: Typical - 3
-50
3.6
-75
3.9
-50
-25
25
50
75
100
125
150
Temperature (C)
( C)
VDD (V)
FIGURE 33-87:
Temperature Indicator Initial
Offset, Low Range, Temp. = 20C, PIC16F1705/9
Only.
FIGURE 33-88:
Temperature Indicator Slope
Normalized to 20C, High Range, VDD = 5.5V,
PIC16LF1705/9 Only.
250
150
ADC VREF+ SET TO VDD
ADC VREF- SET TO GND
200
Max.
150
Max.
125
Typical
Typical
100
Min.
Min.
ADC Output Codes
75
100
50
0
-50
50
25
0
-25
Max: Typical + 3
Typical; statistical mean
Min: Typical - 3
-100
Max: Typical + 3
Typical; statistical mean
Min: Typical - 3
-50
-150
-75
-50
-25
25
50
75
100
125
150
Temperature (C)
( C)
FIGURE 33-89:
Temperature Indicator Slope
Normalized to 20C, High Range, VDD = 3V,
PIC16F1705/9 Only.
DS40001729B-page 418
-50
-25
25
50
75
100
125
150
Temperature (C)
( C)
FIGURE 33-90:
Temperature Indicator Slope
Normalized to 20C, Low Range, VDD = 3.0V,
PIC16F1705/9 Only.
PIC16(L)F1705/9
Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 F, TA = 25C.
150
250
200
Max.
Max.
Typical
Typical
100
Min.
150
Min.
ADC Output Codes
100
50
0
50
-50
-50
Max: Typical + 3
Typical; statistical mean
Min: Typical - 3
Max: Typical + 3
Typical; statistical mean
Min: Typical - 3
-100
-100
-150
-50
-25
25
50
75
100
125
-50
150
-25
25
50
75
100
125
FIGURE 33-91:
Temperature Indicator Slope
Normalized to 20C, Low Range, VDD = 1.8V,
PIC16LF1705/9 Only.
FIGURE 33-92:
Temperature Indicator Slope
Normalized to 20C, Low Range, VDD = 3.0V,
PIC16LF1705/9 Only.
250
80
ADC VREF+ SET TO VDD
ADC VREF- SET TO GND
200
Max.
75
Typical
Max.
70
Min.
CMRR (dB)
150
100
50
65
Typical
60
55
-50
50
Max: Typical + 3
Typical; statistical mean
Min: Typical - 3
-100
-50
-25
25
50
75
100
125
Min.
Max: Typical + 3
Typical; statistical mean
Min: Typical - 3
45
-150
40
150
-50
-25
25
50
Temperature (C)
Temperature (C)
FIGURE 33-93:
Temperature Indicator Slope
Normalized to 20C, High Range, VDD = 3.6V,
PIC16LF1705/9 Only.
75
100
125
150
FIGURE 33-94:
Op Amp, Common Mode
Rejection Ratio (CMRR), VDD = 3.0V.
35%
80
-40C
75
25C
30%
Max.
85C
70
125C
25%
65
Percent of Units
CMRR (dB)
150
Temperature (C)
( C)
Temperature (C)
( C)
Typical
60
55
Min.
20%
15%
10%
50
Max: Typical + 3
Typical; statistical mean
Min: Typical - 3
45
5%
40
-50
-25
25
50
Temperature (C)
75
100
125
FIGURE 33-95:
Op Amp, Common Mode
Rejection Ratio (CMRR), VDD = 3.0V.
150
0%
-7
-5
-4
-3
-2
-1
0
1
2
Offset Voltage (mV)
FIGURE 33-96:
Op Amp, Offset Voltage
Histogram, VDD = 3.0V, VCM = VDD/2.
DS40001729B-page 419
PIC16(L)F1705/9
Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 F, TA = 25C.
3.8
8
Max.
VDD = 3.6V
3.7
3.6
Slew Rate (V/s)
4
Typical
2
0
-2
VDD = 5.5V
3.5
3.4
VDD = 2.3V
3.3
VDD = 3V
3.2
-4
Min.
Max: Typical + 3
Typical; statistical mean
Min: Typical - 3
-6
3.1
3.0
-8
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
-60
5.5
-40
-20
FIGURE 33-97:
Op Amp, Offset over
Common Mode Voltage, VDD = 5.0V, Temp =
25C PIC16F1705/9 Only.
40
60
80
100
120
140
FIGURE 33-98:
Op Amp, Output Slew Rate,
Rising Edge, PIC16F1705/9 Only.
5.4
45
5.2
43
-40C
41
5.0
VDD = 2.3V
Hysteresis (mV)
20
Temperature (C)
4.8
4.6
4.4
VDD = 3.6V
4.2
VDD = 5.5V
39
25C
37
85C
35
125C
33
31
4.0
29
3.8
27
VDD = 3V
25
3.6
-60
-40
-20
20
40
60
80
100
120
0.0
140
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Temperature (C)
FIGURE 33-99:
Op Amp, Output Slew Rate,
Falling Edge, PIC16F1705/9 Only.
FIGURE 33-100:
Comparator Hysteresis,
Normal-Power Mode (CxSP = 1), VDD = 3.0V,
Typical Measured Values.
30
30
25
25
Max.
20
20
15
Max.
10
5
0
Min.
15
10
5
0
Min.
-5
-5
-10
-10
-15
-15
-20
-20
0.0
0.5
1.0
1.5
2.0
2.5
3.0
FIGURE 33-101:
Comparator Offset,
Normal-Power Mode (CxSP = 1), VDD = 3.0V,
Typical Measured Values at 25C.
DS40001729B-page 420
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
FIGURE 33-102:
Comparator Offset,
Normal-Power Mode (CxSP = 1), VDD = 3.0V,
Typical Measured Values from -40C to 125C.
PIC16(L)F1705/9
Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 F, TA = 25C.
30
50
25
45
Hysteresis (mV)
Hysteresis (mV)
40
25C
85C
35
Max.
20
-40C
125C
30
15
10
5
0
Min.
-5
-10
25
-15
-20
20
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0.0
6.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
FIGURE 33-103:
Comparator Hysteresis,
Normal-Power Mode (CxSP = 1), VDD = 5.5V,
Typical Measured Values, PIC16F1705/9.
FIGURE 33-104:
Comparator Offset,
Normal-Power Mode (CxSP = 1), VDD = 5.0V,
Typical Measured Values at 25C, PIC16F1705/9
Only.
140
40
120
30
Max.
Time (ns)
100
20
10
80
60
Max.
0
Typical
40
Min.
Min.
-10
20
-20
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
1.5
2.0
2.5
3.0
3.5
4.0
VDD (V)
FIGURE 33-105:
Comparator Offset,
Normal-Power Mode (CxSP = 1), VDD = 5.5V,
Typical Measured Values from -40C to 125C,
PIC16F1705/9 Only.
FIGURE 33-106:
Comparator Response Time
over Voltage, Normal-Power Mode (CxSP = 1),
Typical Measured Values, PIC16LF1705/9 Only.
1,400
Max: Typical + 3 (-40C to +125C)
Typical; statistical mean @ 25C
Min: Typical - 3 (-40C to +125C)
80
1,200
70
1,000
Time (ns)
Time (ns)
60
50
Max.
40
Typical
800
600
30
Min.
400
Max.
20
Typical
200
10
Min.
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 33-107:
Comparator Response Time
over Voltage, Normal-Power Mode (CxSP = 1),
Typical Measured Values, PIC16F1705/9 Only.
1.5
2.0
2.5
3.0
3.5
4.0
VDD (V)
FIGURE 33-108:
Comparator Output Filter
Delay Time over Temperature, Normal-Power
Mode, Typical Measured Values,
PIC16LF1705/9 Only.
DS40001729B-page 421
PIC16(L)F1705/9
Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 F, TA = 25C.
TYPICAL MEASURED VALUES
0.025
800
-40C
0.020
700
25C
85C
0.015
125C
600
500
DNL (LSb)
Time (ns)
0.010
400
300
0.005
0.000
-0.005
Max.
200
-0.010
Typical
100
-0.015
Min.
-0.020
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
16
32
48
64
80
96
VDD (V)
FIGURE 33-109:
Comparator Output Filter
Delay Time over Temperature, Normal-Power
Mode, Typical Measured Values, PIC16F1705/9
Only.
FIGURE 33-110:
Typical DAC DNL Error,
VDD = 3.0V, VREF = External 3V.
0.00
0.020
-0.05
0.015
-40C
25C
85C
-0.10
125C
0.010
DNL (LSb)
INL (LSb)
-0.15
-0.20
-0.25
-0.30
0.000
-0.005
-40C
-0.35
0.005
25C
-0.010
85C
-0.40
125C
-0.015
-0.45
0
16
32
48
64
80
96
FIGURE 33-111:
Typical DAC INL Error,
VDD = 3.0V, VREF = External 3V.
16
32
48
64
80
96
FIGURE 33-112:
Typical DAC INL Error,
VDD = 5.0V, VREF = External 5V, PIC16F1705/9
Only.
0.00
24
-0.05
Max.
22
-0.10
20
DNL (LSb)
INL (LSb)
-0.15
-0.20
-0.25
18
Typical
16
-0.30
14
-40C
-0.35
Min.
25C
12
85C
-0.40
125C
10
-0.45
0
16
32
48
64
80
96
FIGURE 33-113:
Typical DAC INL Error,
VDD = 5.0V, VREF = External 5V, PIC16F1705/9
Only.
DS40001729B-page 422
1.6
1.8
2.2
2.4
2.6
2.8
3.2
3.4
3.6
3.8
Output Code
FIGURE 33-114:
DAC INL Error, VDD = 3.0V,
PIC16LF1705/9 Only.
PIC16(L)F1705/9
Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 F, TA = 25C.
0.4
0.45
0.2
0.15
0.2
0.1
0.05
0
50
Temperature (C)
100
Absolute
Absolute
INL (LSb)
INL (LSb)
0.25
-50
-40
-20
20
40
60
Temperature (C)
( C)
80
0.86
-2.7
-40
25
-2.9
0.84
-3.1
85
125
-3.3
0.82
-3.5
0.0
0.80
150
0.0
-60
-2.3
0.88
0.10
0.35
Absolute
Absolute
DNL (LSb)
DNL (LSb)
0.90
-2.1
0.4
100
120
2.0
3.0
Temperature (C)
4.0
5.0
0.78
140
FIGURE 33-115:
Absolute Value of DAC DNL
Error, VDD = 3.0V, VREF = VDD.
1.0
-60
-40
-20
20
40
60
Temperature (C)
( C)
80
100
120
140
FIGURE 33-116:
Absolute Value of DAC INL
Error, VDD = 3.0V, VREF = VDD.
0.30
0.3
0.85
VREF = INT. VDD
0.25
0.80
-40C
-40
25
85
0.1
125
0.18
0.05
Absolute
Absolute
DNL (LSb)
DNL (LSb)
0
0.14 0.0
1.0
2.0
3.0
4.0
Temperature (C)
5.0
0.75
25C
0.70
85C
125C
0.65
6.0
0.60
2.0
0.10
-60
-40
-20
20
40
60
Temperature (C)
( C)
80
100
120
2.5
3.0
3.5
140
FIGURE 33-117:
Absolute Value of DAC DNL
Error, VDD = 5.0V, VREF = VDD, PIC16F1705/9
Only.
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 33-118:
Measured Values.
8.0
1.4
5.5V
1.2
Fall-3.0V
Fall-5.5V
Time (s)
1.0
0.8
0.6
0.4
Rise-2.3V
Rise-3.0V
Rise-5.5V
0.2
0.0
-50
-25
25
50
75
Temperature (C)
100
125
150
FIGURE 33-119:
ZCD Response Time over
Voltage, Typical Measured Values.
Fall-2.3V
3.0V
6.0
2.3V
4.0
1.8V
2.0
0.0
-2.0
-4.0
-0.20
0.00
0.20
0.40
0.60
0.80
1.00
1.20
1.40
1.60
1.80
2.00
2.20
FIGURE 33-120:
ZCD Pin Current over ZCD
Pin Voltage, Typical Measured Values from
-40C to 125C.
DS40001729B-page 423
PIC16(L)F1705/9
Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 F, TA = 25C.
0.28
1.00
0.26
0.90
0.80
Time (s)
0.24
Time (s)
0.70
0.60
0.22
0.20
0.50
0.18
0.40
0.30
1.8V
0.20
3.0V
125C
85C
25C
-40C
0.16
2.3V
0.14
5.5V
1.5
0.10
0
100
200
300
400
2.0
2.5
3.0
500
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 33-122:
COG Dead-Band Delay,
DBR/DBF = 32, Typical Measured Values.
9.0
0.45
8.5
0.40
8.0
0.35
7.5
0.30
7.0
0.25
Max: Typical + 3
Typical; statistical mean
Min: Typical - 3
Max.
Typical
Min.
Time (s)
Time (ns)
FIGURE 33-121:
ZCD Pin Response Time
Over Current, Typical Measured Values from
-40C to 125C.
6.5
6.0
0.20
0.15
5.5
0.10
125C
85C
25C
-40C
5.0
0.05
4.5
0.00
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
10
20
30
40
50
60
70
DBR/DBF Value
VDD (V)
FIGURE 33-123:
COG Dead-Band DBR/DBF
Delay Per Step, Typical Measured Values.
FIGURE 33-124:
COG Dead-Band Delay per
Step, Typical Measured Values.
0.07
Max.
Max: Typical + 3
Typical; statistical mean
Min: Typical - 3
0.06
Typical
0.05
Min.
Time (s)
0.04
0.03
0.02
0.01
0.00
0
10
11
DBR/DBF Value
FIGURE 33-125:
COG Dead-Band Delay per
Step, Zoomed to First 10 Codes, Typical
Measured Values.
DS40001729B-page 424
PIC16(L)F1705/9
34.0
DEVELOPMENT SUPPORT
34.1
Multiple projects
Multiple tools
Multiple configurations
Simultaneous debugging sessions
DS40001729B-page 425
PIC16(L)F1705/9
34.2
MPLAB XC Compilers
34.3
MPASM Assembler
34.4
34.5
DS40001729B-page 426
PIC16(L)F1705/9
34.6
34.7
34.8
34.9
The MPLAB PICkit 3 allows debugging and programming of PIC and dsPIC Flash microcontrollers at a most
affordable price point using the powerful graphical user
interface of the MPLAB IDE. The MPLAB PICkit 3 is
connected to the design engineers PC using a fullspeed USB interface and can be connected to the target via a Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The
connector uses two device I/O pins and the Reset line
to implement in-circuit debugging and In-Circuit Serial
Programming (ICSP).
DS40001729B-page 427
PIC16(L)F1705/9
34.11 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully
functional systems. Most boards include prototyping
areas for adding custom circuitry and provide application firmware and source code for examination and
modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
DS40001729B-page 428
PIC16(L)F1705/9
35.0
PACKAGING INFORMATION
35.1
Example
PIC16F1705
P e3
1304017
28-Lead SOIC (7.50 mm)
14-Lead SOIC (3.90 mm)
Example
Example
PIC16F1705
SO e3
1304017
Example
XXXXXXXX
YYWW
NNN
Legend: XX...X
Y
YY
WW
NNN
e3
Note:
16F1705
1304
017
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week 01)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator e( 3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
DS40001729B-page 429
PIC16(L)F1705/9
Package Marking Information (Continued)
16-Lead QFN (4x4x0.9 mm)
PIN 1
Example
PIN 1
PIC16
F1705
MV
130417
e3
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
Example
PIC16F1709
ML e3
130417
Example
PIC16F1709
PT e3
130417
Legend: XX...X
Y
YY
WW
NNN
e3
Note:
DS40001729B-page 430
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week 01)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator e( 3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
PIC16(L)F1705/9
Package Marking Information (Continued)
20-Lead SOIC (7.50 mm)
Example
PIC16F1709
PT e3
130417
PIN 1
Example
PIN 1
PIC16
F1709
MV
130417
e3
Legend: XX...X
Y
YY
WW
NNN
e3
Note:
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week 01)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator e( 3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
DS40001729B-page 431
PIC16(L)F1705/9
35.2
Package Details
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PIC16(L)F1705/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001729B-page 433
PIC16(L)F1705/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001729B-page 434
PIC16(L)F1705/9
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PIC16(L)F1705/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001729B-page 436
PIC16(L)F1705/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001729B-page 437
PIC16(L)F1705/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001729B-page 438
PIC16(L)F1705/9
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PIC16(L)F1705/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001729B-page 440
PIC16(L)F1705/9
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DS40001729B-page 441
PIC16(L)F1705/9
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DS40001729B-page 442
PIC16(L)F1705/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001729B-page 443
PIC16(L)F1705/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001729B-page 444
PIC16(L)F1705/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001729B-page 445
PIC16(L)F1705/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001729B-page 446
PIC16(L)F1705/9
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DS40001729B-page 447
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DS40001729B-page 448
PIC16(L)F1705/9
APPENDIX A:
DATA SHEET
REVISION HISTORY
Revision A (12/2013)
Initial release of this document.
Revision B (04/2015)
Updated Sections 8.2.2, 20.1.2, 20.1.3, 21.1, 21.1.1,
22.3, 28.2.1, 29.4.2, 32.0 (Electrical Specifications)
and 33.0 (DC and AC Characteristics Graphs and
Charts); Updated introductory paragraph of Section
21.0; Added Sections 3.2 (High-Endurance Flash)
and 6.5.5 (Clock Switch Before Sleep); Updated
Tables 1, 2, 1-2, 3-1, 3-3, 3-4, 3-5, 6-1; Updated note
references, bit 2 and values on POR, BOR and all
other Resets for the ADCON1 register in Table 3-10;
Updated Figures 3-1, 6-7, 18-2 through 18-6, 20-1,
22-1 and 25-1; Added note to Figure 21-1; Updated
Registers 20-1, 20-2 and 21-1; Other minor
corrections.
DS40001729B-page 449
PIC16(L)F1705/9
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers
should
contact
their
distributor,
representative or Field Application Engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://www.microchip.com/support
DS40001729B-page 450
PIC16(L)F1705/9
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office .
[X](1)
PART NO.
Device
/XX
XXX
Package
Pattern
Examples:
a)
b)
Device:
PIC16F1705, PIC16LF1705,
PIC16F1709, PIC16LF1709
Blank
T
Temperature
Range:
I
E
= -40C to +85C
= -40C to +125C
Package:(2)
ML
P
SP
ST
SL
SO
SS
=
=
=
=
=
=
=
Pattern:
(Industrial)
(Extended)
QFN
PDIP
SPDIP
TSSOP
SOIC
SOIC
SSOP
PIC16LF1705- I/P
Industrial temperature
PDIP package
PIC16F1709- E/SS
Extended temperature,
SSOP package
Note
1:
2:
DS40001729B-page 451
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Trademarks
== ISO/TS 16949 ==
DS40001729B-page 452
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ASIA/PACIFIC
EUROPE
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Web Address:
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Tel: 91-80-3090-4444
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Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
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Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
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Tel: 86-10-8569-7000
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Tel: 852-2943-5100
Fax: 852-2401-3431
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Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
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Tel: 512-257-3370
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Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
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Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
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Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
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Itasca, IL
Tel: 630-285-0071
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Tel: 216-447-0464
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Tel: 281-894-5983
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Fax: 317-773-5453
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
China - Dongguan
Tel: 86-769-8702-9880
China - Hangzhou
Tel: 86-571-8792-8115
Fax: 86-571-8792-8116
India - Pune
Tel: 91-20-3019-1500
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Kaohsiung
Tel: 886-7-213-7828
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Canada - Toronto
Tel: 905-673-0699
Fax: 905-673-6509
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Germany - Pforzheim
Tel: 49-7231-424750
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Italy - Venice
Tel: 39-049-7625286
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Poland - Warsaw
Tel: 48-22-3325737
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
01/27/15
DS40001729B-page 453