3.

1 Static Random Access Memory (SRAM)

SRAM is a type of semiconductor memory consisting of CMOS transistors. Unlike
dynamic RAM (DRAM) which must be periodically refreshed, SRAM is based on a bi-stable
latch which will retain its value as long as the circuit is powered. Each bit is made of 6
transistors, arranged as two cross-coupled inverters and two access switches, as show in Figure 3
below. This bit has two stable states to represent either a logic zero or a logic one. There are two
additional transistors, labeled as M5 and M6 in the figure below, which are known as access
transistors since they control the access to the storage cell during write and read operations.
Memories are said to be static if no periodic clock signals are required to retain stored
data indefinitely. Memory cells in these circuits have a direct path to power supply or GND or
both. Read-write memory cell arrays based on flip-flop circuits are commonly referred to as
Static RAM or SRAMs.
3.1.1

Merits of SRAM

Low power dissipation

Superior noise margin

High switching speeds suitable for high-density SRAM arrays.

The memory cells do not need to be refreshed.

SRAMs are faster than DRAMs because of the differential pair of bit-lines.

The operational modes of SRAMs are simpler because the row and column address
signals are simultaneously loaded.

3.1.2

Demerits of SRAM

Very expensive

Low density

On the other hand, static memories have the great disadvantage of a large memory cell
compared to dynamic memories. The main reason for this is that resistive loads or load
transistors must counteract the leakage currents flowing through the cell. This increases
the cell area. Therefore, their capacities are normally smaller than those of dynamic
RAMs.

3.1.3

Challenges in SRAM
The following are the major challenges in the design of an efficient SRAM.

a) Power Consumption
In recently presented reduced-power processors, nearly half of the total system power
consumption is attributed to the memory circuits. Hence, reducing the power dissipation in
memories can significantly improve the system Power-efficiency, performance, reliability and
overall costs.
b) Read and Write Access Times
Memory applications require techniques for maximizing the access speeds of static
memories with minimal power consumption to optimize the overall system performance. The
performance of the address decoders, sense amplifiers and the periphery I/O circuitry need to be
simultaneously improved for achieving this goal.
c) Reliability
CMOS technology scaling trends, applications and operating conditions have added both
reliability and robustness as design metrics in addition to the traditional metrics of power, speed,
area and cost. Reliability is normally deals with the immunity to hard failures such as electro
migration, hot carrier effects, or dielectric breakdowns.
3.1.4

Applications of SRAM

SRAM is used in personal computers, workstations, routers and peripheral equipment,

internal CPU caches and external burst mode SRAM caches, hard disks buffers, router buffers,
etc. LCD screens and printers also normally employ static RAM to hold the image displayed or
to be printed. Some SRAM buffers are

Also found in CDROM and CDRW drives; usually 356 KB or more are used to buffer
track data, which is transferred in blocks instead of as single values.

Many categories of industrial and scientific subsystems, automotive electronics, and

similar contains static RAM. Some amounts (kilobytes or less) are also embedded in
practically all modern appliances, toys, etc that implements an electronic user interface.
Several megabytes may be used in complex products such as digital cameras, cell phones,

synthesizers; etc. SRAM in its dual ported form is sometimes used for real-time digital
signal processing circuits.

The standalone SRAMs can be integrated as an external memory during board design
stage.

3.2 Architecture of SRAM

The preferred organization for Random Access Memory is shown in Fig 3.1. This
Organization is random-access architecture, which is an Asynchronous design. The name is
derived from the fact that memory locations (addresses) can be accessed in random order at a
fixed rate, independent of physical location, for reading or writing. The storage array, or core, is
made up of simple cell circuits arranged to share connections in horizontal rows and vertical
columns. The horizontal lines, which are driven only from outside the storage array, are called
word lines, while the vertical lines, along which data flow into and out of cells, are called bit
lines. A cell is accessed for reading or writing by selecting its row and column.
Each Cell can store 0 or 1. Memories may simultaneously select 4, 8, 16, 33, or 64
columns in one row depending on the application. The row and column (or group of columns) to
be selected is determined by decoding binary address information. For example, consider a row
decoder that has 3

out-put lines, a different one of which is enabled for each different n-bit

input codes. The column decoder takes m inputs and produces 3

bit line access signals, of

which any of them can be enabled at one time. The bit selection is done using a multiplexer
circuit to direct the corresponding cell outputs to data registers. In total, 3 n X 3 m cells are stored
in the core array.

Figure 3.1: Memory organizations

3.2.1 Circuit design

A Schematic Editor is used for capturing (i .e. describing) the transistor-level design of
the gate. The Schematic Editors provide simple, intuitive means to draw, to place and to connect
individual components that make up the design. The resulting schematic drawing must
accurately describe the main electrical properties of all components and their interconnections.
Also included in the schematic are the supply connections (V dd and Gnd), as well as all pins for
the input and output signals of the circuit. From the schematic, a net list is generated, which is
used in later stages of the design. The schematic design of single SRAM cell is shown below.

Pass
transistor

Figure 3.2: schematic of single SRAM

3.2.3 Working principle
The Data storage cell i.e., the 1-bit memory cell in static RAM arrays invariably consists
of simple latch circuit with two stable operating points (states). Depending on the persevered
state of the two-inverter latch circuit, the data being held in the memory cell will be interpreted
either as a logic 0 or as logic 1. To access (read and write) the data contained in the memory
cell via the bit line, we need at least one switch, which is controlled by the corresponding word
line, i.e., the row address selection signal. Usually, two complementary bit lines (columns). This
can be likened to turning the car steering wheel with both left and right hands in complementary
directions.

3.2.3 Operation of SRAM

SRAM memory cells are based on the latch Structure with two back-to-back connected
inverters & two pass transistors. Data can be written by driving WL high & driving the lines BL
& ~BL with data with complementary values. Because the bit lines are driven with more force
than the force with which the cell retains its information (the transistors driving the lines BL &
~BL are more powerful, i.e. these are larger than the NMOS of inverters), the cell will be forced
to the state presented on the lines BL & ~BL.

BL=0
BL_bar=1

Figure 3.3: schematic of single SRAM cell when bit line bar is enabled

BL=1
BL_bar=0

Figure 3.4: schematic of single SRAM cell when bit line is enabled

3.3 Problem Definition

Static RAM plays a key role in modern devices as the technology advances and the
needs for high speed and performance of very deep sub-micron CMOS designs are increasing.
As the sizing of the SRAM is in nanometre scale the variations in electrical parameters i.e.,
density of impurity concentration, oxide thickness and diffusion depths have to maintain
carefully. The conventional 6T memory cell comprises of two CMOS inverters cross coupled
with two pass transistors connected to a complementary bit lines. The data retention of the
SRAM cell in hold state and the read state are important constraints in advanced CMOS
processes.
3.3.1 Problem definition
Semiconductor memory arrays capable of storing large quantities of digital information are
essential to all digital systems. The amount of memory required in a particular system depends
on the type of application, but, in general, the number of transistors for the information (data)
storage function is much larger than the number of transistors used for logic operations and other
purposes. The ever-increasing demand for larger data storage capacity has driven the fabrication
technology and memory development toward more compact design rule and, consequently,
toward higher data storage densities. Thus, the maximum realizable data storage capacity of
single-chip semiconductor memory arrays approximately doubles every two years. On-chip
memory has become widely used subsystems in many VLSI circuits, and commercially available
single-chip read/write memory capacity has reached one gigabytes. This trend toward higher
memory density and larger storage capacity will continue to push the leading edge of digital
system design.