High Layer Count PCB

Technology Trends in KOREA

April, 21 2011
Sang Soo LEE
ISUPETASYS

Contents

Definition of High Layer Count PCB

Core Technology Trends

High Layer Count PCB Technology Drivers

Interconnection Reliability

Next Page

Definition of High Layer Count PCB

Core Technology Trends

High Layer Count PCB Technology Drivers

Interconnection Reliability

1. Definition of High Layer Count PCB

High Layer Count PCB

With the popularization of the Internet,

wireless data system and mobile communication,
High
Hi
h layer
l
countt PCB is
i required
i d to
t transmit
t
it data
d t
rapidly and fulfill the need to process data with
high speed
Application

Line Card, Backplane for Communication Network

High-End
g
Router,, Server,, Storage
g
Workstation, Super Computer.

General Specification

Layer Count : +18L

Thickness : <100mil, Aspect ratio : over12:1
Trace Width/Space
p
: 0.075mm/0.075mm
Surface Finish : L/F OSP,ENIG, Electrolytic Ni/Gold, Silver, Tin,
L/F HASL
Impedance : Single ended/Differential
Base Material : High Tg FR-4,Low/Ultra Dk/Df & Lead free

2. Market Characteristics & Trends

Market Characteristics

Relatively conservative purchasing than consumer product PCB

Prefer to highly experienced PCB supplier
Listing on the OEM Vendor List
EMS has no independent authority to select PCB supplier
Without almost perfect internal QA sys
sys, Higher Claim charge (Ave USD $4~5
$4~5,000/pcs)
000/pcs)
No merit at all, without almost perfect inner layer process yield rate (see the below)

11 of 12 = 91.6%
yield, 3
3~4
4 cores

0%, 8 + cores

2. Market Characteristics & Trends

Changing Traditional Trends

Giant industrial OEM rushing toward ASIAN PCB SHOPS. WHY?
router. server. supercomputer. Aero space., etc

Conventionally strong U.S/ Europe pcb shops

Closed local factories since IT Bubble or transit SHOPS in Southeast Asia.

Unlike Asian, reluctant to invest aggressively new manufacturing facilities

Brought to long term delivery (8~10 weeks)

Asia PCB Suppliers surprisingly playing well

well doing job
job with
Excellent technology and brand new facility
Low PPM level of Defect
Delivery responsiveness

Next Page

Definition of High Layer Count PCB

Core Technology Trends

High Layer Count PCB Technology Drivers

Reliability

1. Top Stage- Core technology Trends

Industrial technology driver

Increasing traffic density across internet,
internet data storage are need for higher volume
data throughput
The next generation of back planes will require serial data rates of 10Gbps while
the emerging. Intermediate back plane products will employ 6.25 Gbps serial data
rates. 5/6.25 Gbps => 10Gbps
High volume data throughput & High speed signal requiring pcb
To design circuit with total signal integrity such as highly accurate impedance
control, time delay, signal loss, skin effect, skew etc.

System Roadmap
Product

Technology
gy

Router

Band Width
Serial Data Rate

S
Server

Clock Speed

2009

2010

2011

2012

10Gbps

20Gbps

40Gbps

6.25Gbps

10Gbps

20Gbps

2Gh
2Ghz

2 5Gh
2.5Ghz

3 5Gh
3.5Ghz

2. Middle Stage Core Technology Trends

Core technology for High Layer Count PCB
Higher Volume data throughput & clock speed put dramatically impact on
PCB Design. Manufacturing. Reliability and Environmental issue
Routing Density
- HDI (Blind & Buried Via)
- VIP (Via in Pad)
- Reduction for Layer Count, Line width

High Speed Signal Integrity

- Electrical Simulation
- Buried Capacitance & Resistance
- Material & Design (Ultra Low Dk/Df)

Environmental Regulation
- Lead Free
- ROHS

Interconnection Reliability
- IST
- CAF

2.SignalInt
2
SignalInt
egrity

1.Routing
Density

Higher Data
Rate &
Clock
Speed
p
3.Environment
al Regulation

4.Interconnectio
n Reliability

10

Next Page

Definition of High Layer Count PCB

Core Technology Trends

High Layer Count PCB Technology Drivers

Reliability

1. High Layer Count PCB Technology Drivers 1

Core driver 1. Material
What is a markets needs for material?
Guaranteed same electrical performance (Dk/Df) with lead free compatible material.
Guaranteed thermal reliability after lead free assembly.
Supply a low cost lead free compatible material
material.

Markets
Market
s
Needs

Low Cost

11

1. High Layer Count PCB Technology Drivers 1

12

Tier 3~5 laminates are gaining an increasing share of the market for
high-speed applications (Low Dk / Low Df)

Source by IPC

1. High Layer Count PCB Technology Drivers 1

13

What is a difference?
Should use a lead free alloys
y instead of Sn/Pb alloys.
y
SAC Solder need more higher reflow temperatures. Up to 20C higher
Reflow Type

Solder Type

Solder Melting Point

Peak Reflow Temperature

Sn/Pb Reflow

Eutectic Solder

183

210~240

Lead-Free
Lead
Free Reflow

SAC (96.5Sn/3.0Ag/0.5Cu) Solder

217

240~260
240
260

JEDEC Profile
(J-STD-020C)
Upper line: Lead free Reflow
Lower line: Sn/Pb Reflow

1. High Layer Count PCB Technology Drivers 1

14

What we are considering

Comparison of thermal properties for laminate

Test Items

Dicy Cured 170

Non-Dicy Cured 170

Low Dk/Df 200

Test Vehicle

Laminate (Double Side)

Laminate (Double Side)

Laminate (Double Side)

CTE

3.7%

3.0%

3.5%

TMA (Tg)

170.0

170.0

170.0

TGA (Td)

325.0

350.0

365.0

T260

4min ~ 8min

Over 60min

Over 30min

T288

2min

Over 10min

Over 10min

1. High Layer Count PCB Technology Drivers 1

15

1) Comparison of thermal properties for 16L Board

Test Items

Dicy Cured 170

Non-Dicy Cured 170

Low Dk/Df 200

Layer Count

16L

16L

16L

Overall Thickness

2.38mm (9.4mil)

2.38mm (9.4mil)

2.38mm (9.4mil)

CTEBGA Area

3.31%

3.52%

2.88%

TMA TgBGA Area

176.6

176.2

200.6

T260-Clad

3.5 min

Over 20 min

Over 20 min

T288-Clad

0 min

3.58 min

1.63 min

2) Comparison of thermal properties for 28L Board

Test Items

Dicy Cured170

Non-Dicy Cured 170

Low Dk/Df 200

Layer Count

28L

28L

28L

Overall Thickness

3.0mm (118mil)

3.0mm(118mil)

3.0mm(118mil)

CTEBGA Area

3.83%

3.65%

3.35%

TMATgBGA Area

163 4
163.4

161 0
161.0

177 4
177.4

TGA (Td)

312.5

328.0

338.8

T260-Clad

3.2 min

Over 20 min

12.85 min

T288-Clad
T288
Clad

0 min

2.2 min

0 min

Lead-Free Reflow 5X

Fail

Pass

Fail

1. High Layer Count PCB Technology Drivers 1

16

What we are considering

Lead Free Reflow Test

Lead free reflow test is necessary to confirm the evaluation result.

You can find de-lamination in black spot area.

Dicy Cured 170
170C
C Non-dicy
Non dicy cured 170
170C
C

X-Section Dicy Cured 170C

Low Dk/Df 200

200C
C

X-Section Low Dk/Df 200C

Evaluation report shows a little bit difference between raw material and PCBs.
PCBs
Basically, Thermal reliability is affected by board design (Layer Count,Thickness)

1. High Layer Count PCB Technology Drivers 2

17

Core driver 2. Routing Density

2 1 Routing Density : Finer line width & Layer Count increasing
2-1.
Required : Layer counts 18~22L 24~30L / Line width 5mil 4mil 3mil
Key Point 1. (layer count increasing)
Handle thin Coreless 100um in process
Registration Control
High Aspect Ratio of plating

Key Point 2.
2 Finer line width
Signal line width tolerance 10% 7%
Signal line width 3/3 mil will cause drastic
Yield drop
p

Road Map
Internal Lines & Spaces
External Lines & Spaces
BGA Ball Pitch (Goal)
1.0mm 3 lines
0.8mm 2 lines

2011
3 / 4 mil
3.5/4 mil

2012
3/3mil

1. High Layer Count PCB Technology Drivers 2

18

2-2. Routing Density : Drill to Metal

Required : Ball Pitch of BGA & CCGA are smaller design as 0.4 & 0.5mm from 0.8 &1.0mm pitch
Required
R
i d : Routing
R ti Density
D
it is
i higher
hi h between
b t
pad
d to
t pad
d
What is Drill to Metal?

Key Point

Spacing between drill edge to around signal trace

Spacing between drill edge to around Anti-pad
edge
Signal D2M

Signal D2M
Annular ring + Spacing

Prepreg

Drill

Plane D2M
Anti pad Size

Prepreg

Plane Anti pad

D2M

2011
7mil

2012
6mil

9mil 8mil 7mil

Pattern

ThinCore

Using
U i S
Smallest
ll t Drill
D ill size
i as 6~10mil
6 10 il
Keep upgrade Registration Capability

26mil 24mil 22mil

2011

2012

22mil

20mil

2. High Layer Count PCB Technology Drivers 2

2-3. Routing Density : HDI

19

Staggered Via
(1~3L)

Required : HDI design is required for Line Card to reduce

Layer count

Buried Via
Hole (2~25L)
Buried Via
Core (13~14L)

Layer Count : 14~26

Board Thickness : 2.0~2.8t
Micro Via : 127um, 200um
Type : 1-2/2-3 Staggered via, 1-3 Skip via
Min. Via : 200um
Prepreg used for Micro Via holes

Key Point
Registration within 3mil
- PEP, Registration Validation Coupon
Plated inner layer yield control
Control copper thickness on plated signal layers
Laser drilling
- Remove smear with normal prepreg

Standard glass

Spread glass

The fixed energy can not Exactly fit the poor area
(arrow1) & the glass rich area (arrow2) at the same time

2. High Layer Count PCB Technology Drivers 2

20

2-4.Routing Density : Via in Pad

What is VIP?
VIP stands for Via In pad and its structure has
plugged with via epoxy and topside is capped with plating
It was used to increase routing density and attach the

<BGA Area>

Smaller components

Merits
Provides a flat coplanar surface
Make routing easier and more traces on PCB
Increase component density
Potential EMI. SI benefits
Help thermal management
A llower costt & risk
i k off soldering
ld i problem
bl

<PTH N
Normal>
l>

<VIP>

2. High Layer Count PCB Technology Drivers 2

21

2-4. Routing Density : Via in Pad

Application : Surface mounting BGA pad
Smallest BGA & CCGA design
Layer Count : 14~28
Board Thickness : 2
2.0~3.2t
0~3 2t
Type : Plugging for Plated and External MicroVia
Min. Via : 200um
FHS A/R :15:1

Key Point
Pull the wire vertically by using a 50kg load at 10 cm / minute
Until the pad is peeled off and record the load percentage.
Average force of 250 Newtons/Sq.cm [~360 Pounds-force/Sq]

S/N1,Condor #3
@20X Magnification

S/N1,Condor
,
#4
@20X Magnification

S/N2,Condor
,
#6
@20X Magnification

2. High Layer Count PCB Technology Drivers 2

22

2-4. Routing Density : Via In pad

Via Plugging -Criterion

Failure Mode

Air pocket in MVH

Specification

Non filling in PTH

Planarization

Dimple

Air Pocket

Dimple

Note

Under 5%
(Via Hole Dimension)

Under 50um

Normal

None

None

Stric (Mil/Areo)

Specification

Higher Aspect ratio but more strict criterion

2. High Layer Count PCB Technology Drivers 2

2-5.Routing Density : Via In pad

23

(Paste- Low CTE, High Peel Strength)

A

35-45

30-40

30-40

35-45

90days

90days

60days

90days

141

168

160

170

ppm/

39

39

32

24

ppm/

143

105

83

70

25

MPa

7200

5200

8600

8500

100

5800

4300

6200

6700

150

820

2600

4300

5300

200

340

870

2600

1300

250

280

660

2100

700

V Type Viscosity

Pas/25
10

Shelf Life
5
Tg (TMA)
CTE

Rate of moisture absorption

(DMA)

Absorptance
Dill Size
P C k
Pan-Cake

JISC6481

0.23

0.16

0.15

0.15

Avg

4~5

2~3

2~3

22.5

15

17.5

17.5

100

100

100

100

94V-0

94V-0

94V-0

94V-0

400

670

900

400

8010
11010
15030

14030
PCB
11060
15030
FCPKG)

11060
15030

11060
15030

Max
%

UL
Peel Strength

Curing Condition

g/cm

min

3. High Layer Count PCB Technology Drivers 3

24

Core driver 3. High Aspect Ratio Plating in Acid Copper

3 1 High Aspect Ratio Trend & Plating Core driver
3-1.

Trends : Aspect ratio(DHS) which are Conventional boards will be increased about 13:1 in near term.

Request : Increasing Layer counts and Routing Density, It is caused for plating capability to enhances high
Aspect ratio Board Reliability.

21:1
18:1
15:1

2012~2016
2010~2011
2008~2009
2006~2007

Aspect Ratio
Trend
- Use RPP and optimize a RPP parameter for thick
Plating copper thickness

12:1
13:1

- Consider a material property for preventing

plating void
(Activation energy are different among raw materials)

9:1
6:1
3:1

- Check the metal ion concentration in the plating

Tank for better copper property

12:1
11:1
10:1

- Consider full build electroless copper plating.

It is easy to control plating rate.

0
2006~2007

2008~2009 2010~2011

2012~2016

IPC International Technologies Roadmap 2006~2007

State of arts boards may have more high aspect ratio (18:1~24:1)

3. High Layer Count PCB Technology Drivers 3

25

3-2. Desmear

Trends : The low Dk/Df Material construction challenge and the fluidity challenge of high aspect ratio hole
- To improve
impro e a Signal integrit
integrity, generall
generally use
se lo
low Dk/Df Material
- High Aspect ratio drop the fluidity.

Request : Because of low Dk/Df Material use and high aspect ratio, Desmear process must be setup for
new material.
- Consider plasma machine for de-smear, because gas fluidity is better than liquid and
Have a better etch rate (Positive etch back).

Positive Etch Back 0.24mil

- Keep Improve a swelling process for getting a more etch rate and roughness on hole wall
- Consider new basket design for better fluidity

3. High Layer Count PCB Technology Drivers 3

3-2. Desmear

Trends : As required lead free conditions, a raw material of low Dk/Df need a stronger for heat.
Based on this requirements
req irements of market,
market low
lo Dk/Df material added a filler construction
constr ction in resin.
resin

26

3. High Layer Count PCB Technology Drivers 3

3-3. Pulse Plating MVH, PTH

27
Test Panel Spec.
-Nelco4 000-13SI
-Layer Count: 28L
-Board Thick.:196mil
-DHS:10.8mil
-MVH:8mil
-DHS A/R:17.8:1

Cu plating Capability
Cu plating thickness in PTH (DHS 10.8mil)
<Target:1.1mil, min.avg.1.0mil, min:0.8mil>
Min:1.02mil, Max:1.32mil, Avg:1.14mil
C plating
Cu
l ti
thi
thickness
k
iin MVH (size:8mil)
( i 8 il)
Min:1.46mil, Max:1.78mil, Avg:1.57mil
Reliability
y Thermal Stress ((3X,6X)
, )

Item

3X PTH

3X MVH

6X PTH

6X MVH

Delamination
Wicking(mil)
Hole Roughness(mil)
Nail Head(%)
Smear
( )
Resin Recession(%)
Pull away
Copper Crack

None
1.52
0.27
132.4%
None
3.4%
None
None

None
0.6
None
None
None

None
1.41
0.29
127.8%
None
4.7%
None
None

None
0.76
None
None
None

4. High Layer Count PCB Technology Drivers 4

28

Core driver 4. Signal Integrity

4 1 Ultra Low Dk/Df
4-1.
Required : Low Dk/Df material used for High Speed board
Signal Attenuation
1Gbps

5Gbps

FR 4
FR-4

Mid Low loss: 0.01-0.015

0 01 0 015

Nelco N4000-6
Isola FR406
Panasonic R-1766

Nelco N4000-13
Isola FR408HR
Panasonic Megtron4
g

10Gbps

20Gbps

Ultra Low loss < 0

0.01
01
Nelco N4000-13SI
Isola IS620/IS640
Panasonic Megtron6
g

- Still cost adder

- Well defined hole wall process condition for higher Tg/Td matl
- Higher
Hi h d
data
t rate/Faster
t /F t rise
i time
ti
/Longer
/L
lines
li
off large
l
back
b k planes
l
- Propagation delay. Skin effect. P or S parameter also should be taken into
consideration

4. High Layer Count PCB Technology Drivers 4 Confidential

29

4-2.Fiber weave effect (Special Glass weave)

Required : Traditional Glass weave caused
Dk/Df variation instability for a pair
transmission on spread out of glass weave.
Normal type
Non treatment # 1080

Key Point
Using
the
weave
U i
th high
hi h density
d
it off special
i l glass
l
Make Dk/Df variation instability.
Thickness is thinner because of yarn is spread out
The gap is smaller than normal type
#106, #1080 => #1067,1078

Highly spread out

Treatment #1078

4. High Layer Count PCB Technology Drivers 4

Confidential

MNC: Must Not-Cut

Layer

4-3.Back Drilling
Required : Capacity launches can act as low-pass filter,
the effect of which is top
p rohibit the
transmission of high frequencies (Stub Effect)

Stub
Length

The capacitance and the stub are both reduced

Key Point
Only incremental improvements on the PCB for
Signal speed increasing
Yield and quality control for single & multiple depth
Depth tolerance is changed from 254um to 127um
Back drilling positioning

1~4L

4~26L

Back-Drill : Multiple Depth

4~26L

Source: Worldwide High-speed Electronics Tech.& Market Trends For the

Years 06~16

30

Short NG: Drill

Position error

4. High Layer Count PCB Technology Drivers 4

4-3-1.Effect of Back Drilling

Confidential

31

4. High Layer Count PCB Technology Drivers 4

32

4-4. Buried Capacitance

Required : ultra thin core thickness 50um 24um 12um
Process
P
: Hi P
Pott T
Testt : No
N ffailure
il
on I/L cores and
d finished
fi i h d boards
b
d

Key Point
How to handle while proceed thinner core
between inner to press process
Control
C t l Hi-pot
Hi
t test
t t conditions
diti
Registration

Incoming Inspection

Post Etch Puncher

AOI

I/L Prep

Hi Pot Test
For Inner-layer Boards

Acid Rinse only

(Reverse Treated Foil)

Customer
Condition
Ultra Flex line
(1mil Core Compatible line)

Large H
Hole

Smallestvi
a

Max. Delay time is 24hr

BC 24um

Dry Film Lamination

Horizontal Oxide

Imaging with UV Exp.

Lamination &
Electrical Test

DES Line
(Cupric Acid)

Hi Pot Test
For Finished Boards

Ultra Flex DES line

(1mil Core Compatible line)

Customer
Condition

4. High Layer Count PCB Technology Drivers 4

33

4-5.Signal Integrity Simulation

Required : Frequency increasing rapidly, problems of reflection, crosstalk,
Power and Ground noise are required signal integrity simulation
to reduce time and failure cost

Port2
Port1

Signal impedance matching / Critical Net Return Loss Analysis

S parameter
Via Hole Return Attenuation
Key P
K
Point
i t
Optimized Design for Plating thickness improvement
Higher accurate single & differential impedance
To reduce time and failure cost
- Noise of Crosstalk, Reflection, Power/Ground
- EMI Issue / Skew control matters
- Group Delay / Jitter control

4-6. Electrical Performance Measurement

Required : Real SI testing is one of the Hot Issue!
Particularly signal loss value at real circuit board
Panel edge placed coupon testing is not fully enough
Trace Impedance
Insertion Loss S21 / Return Loss S11
Conductor Loss dB/ Dielectric Loss in dB
Propagation velocity & Delay/ SPICE Model (RLGC)
Crosstalk,
Crosstalk Jitter,
Jitter Eye-Diagram/ Current Distribution
S-parameter in frequency domain

34

Next Page

Definition of High Layer Count PCB

Core Technology Trends

High Layer Count PCB Technology Drivers

Interconnection Reliability

5. High Layer Count PCB Technology Drivers 5

35

Coredriver 5. Interconnection Reliability

I
Interconnection
i Reliability
R li bili
Required: Highest Interconnection Reliability
Concern: Conventional Reliability Test Method has
long term and Random selection to verify

Key Point
Conventional Reliability Test Method has
long term and Random selection to verify
- Thermal Stress
- Thermal Shock
Needs: Want to guarantee Long term Reliability
Conventional Reliability Test Method are changed by
electrical test method in easy & high reliability such as
- IST
- CAF

5-1. Conventional Thermal stress & Cycling

5. High Layer Count PCB Technology Drivers 5

5-2. IST
IST : Interconnect Stress Test
Monitoring variation of resistance value
Inside hole wall in real time
Barrel Crack

ICDs

36

5. High Layer Count PCB Technology Drivers5

5-4. CAF

5-5. C-SAM

CAF : Conductive Anodic Filament

Monitoring variation of resistance value in real time
( hole to hole, hole to trace, trace to trace,
layer to layer)

Possible CAF growth Observed between

Hole to Trace.

C-SAM : C-mode Scanning Acoustic Microscope

Non destructive Internal Inspection for
Detecting De-lamination

37

Conclusion
Future Challenges
High speed serial link electrical packaging challenges due to Increasing data rates
Special
p
Impedance
p
Connectors(7%
(
~ 5%))
Back drilling of vias at the PTH connectors will be challenge
Common mode noise due to phase skew between differential pairs and Connectors
Predict Fiber weave effect in simulation
Simulate Resin content effect
Low loss material Vs. Crosstalk Vs. reflection

38

39