NATIONAL UNIVERSITY OF HO CHI MINH CITY

UNIVERSITY OF INFORMATION TECHNOLOGY

FACULTY OF COMPUTER ENGINEERING

CHAPTER 9: TESTBENCH & VERIFICATION

Agenda

Chapter 1:
Chapter 2:
Chapter 3:
Chapter 4:
Chapter 5:
Chapter 6:
Chapter 7:
Chapter 8:
Chapter 9:
Chapter 10:

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Introduction
Modules and hierarchical structure
Fundamental concepts
Structural modeling (Gate- and switch-level modeling)
Dataflow modeling (Expression)
Behavioral modeling
Tasks and Functions
Finite state machines
Testbench and verification
VHDL introduction

Circuit Design with HDL - Chapter 9

Digital design flow (ASIC design flow)

Simulation & Function Verification
+ Design is simulated and tested for
functionality before turning into hardware
+ Do not consider gate, propagation delay,
hazards, glitches, race conditions, setup
and hold violations, and other related
timing issues.
+ Test data are generated by testbench or
waveform editor

Design Specification
Behavior Description
Pre-synthesis verification
Synthesis
Routing and Placement
Timing analyis

Post-synthesis verification
Physical layout
Chip
Ref. Verilog Digital System Design, Zainalabedin Navabi

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Circuit Design with HDL - Chapter 9

Digital design flow (ASIC design flow)

Simulation by input waveform

Simulation by testbench

Circuit Design with HDL - Chapter 9

EDA (Electronic Design Automation) flow

Qsim in Quartus II

Usually good for small design

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EDA (Electronic Design Automation) flow

(ModelSim,VCS)

Using Verilog language for testing design module -> Testbench

Testbench is a code for test, not a part of final design.
Timing & display procedures: important in designing testbench
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Circuit Design with HDL - Chapter 9

Procedure to verify an IP core/Chip

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Circuit Design with HDL - Chapter 9

Test plan
Test plan is a documment that may include:
-

A test environment

A test strategy (check list)

A list of testcases (detail for check list)

A method for generating testcases (random or a vast

amount of testcases)

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A bugs list

Circuit Design with HDL - Chapter 9

Test plan evaluating result method

Observe result model

Self-checking model

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Test plan
basic components in a testbench
Initialization

Clock generation

Input stimuli

DUT
(Design Under
Test)

Monitor output

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Test plan example of a test environment

Control LCD
COMPARE
Master (LCD_ctrl)

Slave (LCD_ctrl)

ahb_monitor
2

0000-1000

1000-2000

APB
Slave
(VIP)

0000-2000

S
APB Bus

Mem
Controller
(DW)
1

AHB Bus
Clk & reset_n
gen

Sdram
smart
model

20000000-40000000

AHB
Slave
(VIP)

40001000-40002000

ahb_monitor

50000000-60000000

AHB
Master1
(VIP)

AHB/APB
Bridge

framework_top.v

tb_LCD_ctrl.v

Self-checking result with a

test pass

A test enviroment of the self-checking model

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Test plan Example of a test strategy

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Test plan Example of a list of testcases

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Testbench - Introduction
Writing a testbench is as complex as writing the RTL code itself.
These days ASICs are getting more and more complex and thus verifying
these complex ASIC has become a challenge.
Typically 60-70% of time needed for any ASIC is spent on
verification/validation/testing.
Even though the above facts are well known to most ASIC engineers, still
engineers think that there is no glory in verification.
Source: http://www.asic-world.com/verilog/task_func1.html#Task

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Testbench - Introduction
For writing testbenches it is important to have the design specification of

the Design Under Test (DUT) .

Specs (DUT) need to be understood clearly

A test plan, which basically documents the test bench architecture

The test scenarios (test cases) in detail, needs to be made.

In testbench, a dummy template which basically declares inputs/inouts to

DUT as reg and outputs from DUT as wire

Note: there is no port list for the test bench.

Source: http://www.asic-world.com/verilog/task_func1.html#Task

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Testbench - Example

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Structure of a testbench
A test bench is a program which
can give arbitrary inputs to Design
Under Test (DUT) and observe
their outputs.

Provide
inputs

DUT

Observer
Outputs

module testbench;
reg [7:0] dat, declaration of signals
Connection of DUT
The description of the clock
initial begin
.
end
Test case;
endmodule

A description of testbench in Verilog-HDL

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Circuit
Design with HDL - Chapter 9

Structure of testbench (cont.)

2 styles
Stimulus and Design block instantiated
in a Dummy top-level module

Stimulus block instantiates Design block

Style 1
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Style 2 (usually used)

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Structure of testbench (cont.)

Style 1
Stimulus and Design block instantiated in a Dummy top-level
module

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Structure of testbench (cont.)

Style 1 (cont.)

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Structure of testbench (cont.)

Style 1 (cont.)
Another view of this: 3 chunks of Verilog, one for each of:

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Structure of testbench (cont.)

Style 1 (cont.)

Module testAdd (testbench) generated inputs for module halfAdd (DUT) and
display changes. Module tBench is top level
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Structure of testbench (cont.)

Style 1 (cont.)

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Structure of testbench (cont.)

Style 2
Stimulus block instantiates Design block

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Structure of testbench (cont.)

Style 2 (cont.)

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Structure of testbench (cont.)

Style 2 (cont.)

// DUT

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Structure of testbench (cont.)

Style 2 (cont.)

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Structure of testbench (cont.)

Style 2 (cont.)

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Testbench techniques
Simulation control
$stop, $finish: stop and finish a simulation.

A stop simulation can be resumed, finish one can not.

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Testbench techniques
Limiting data set
Instead of setting simulation time limit, a testbench can put a

limit on the number of data put on inputs of a DUT

$random: generate random data

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Testbench techniques
Applying synchronized data
Synchronize data with clock

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Testbench techniques
Synchronized display of result

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Testcases
Test vector definition

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Test vector definition State change

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Test vector definition (cont.)

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Test vector definition (cont.)

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Test vector definition (cont.)

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Test vector definition (cont.)

Question:
For the logic below, we got output average 3,
with the input a1=4, a2=2, a3=3, and a4=3.
The result is looks OK. However what kind of bugs may exist in
the logic?

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Test vector definition (cont.)

A sample answer

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Test vector definition (cont.)

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Test vector definition (cont.)

Many kind of bugs escape through RTL simulation test. This means that

we can not be sage from bugs even if simulation test looks OK.
Therefore the following method is the most terrible way to fix bugs.
Never do this way.

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Test vector definition (cont.)

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Example
Example 1

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Example 1 (cont.)

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Example 2
Encoder 8-to-3

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Example 2 (cont.)
module encoder8_3( output reg [2:0] encoder_out, input enable, input [7:0] encoder_in );
always @ (enable or encoder_in)
begin
if (enable)
case ( encoder_in )
8'b00000001 : encoder_out = 3'b000;
8'b00000010 : encoder_out = 3'b001;
8'b00000100 : encoder_out = 3'b010;
8'b00001000 : encoder_out = 3'b011;
8'b00010000 : encoder_out = 3'b100;
8'b00100000 : encoder_out = 3'b101;
8'b01000000 : encoder_out = 3'b110;
8'b10000000 : encoder_out = 3'b111;
default : $display("Check input bits.");
endcase
end
endmodule
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Example 2 (cont.)
module stimulus;
wire[2:0] encoder_out;
reg enable;
reg[7:0] encoder_in;
reg [2:0] expected;
encoder8_3 enc( encoder_out, enable, encoder_in );
initial begin
enable = 1; encoder_in = 8'b00000010, expected = 3b001;
#1 $display("enable = %b, encoder_in = %b, encoder_out = %b, expected_out =
%b", enable, encoder_in, encoder_out, expected);
#1 enable = 0; encoder_in = 8'b00000001; expected = 3b001;
#1 $display("enable = %b, encoder_in = %b, encoder_out = %b, expected_out = %b
", enable, encoder_in, encoder_out, expected);
#1 enable = 1; encoder_in = 8'b00000001; expected = 3b000;
#1 $display("enable = %b, encoder_in = %b, encoder_out = %b, expected_out = %b
", enable, encoder_in, encoder_out, expected);
#1 $finish;
end
endmodule
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Self-checking simulation

##############################
Applying reset
Came out of Reset
Terminating simulation
Simulation Result : PASSED
##############################

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##############################
Applying reset
Came out of Reset
Terminating simulation
Simulation Result : FAILED
---- time=???, signal_value==???,
expect_value=???-------##############################

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Debuging

Debug by Synopsyss DVE tool

Source: http://www.synopsys.com/Tools/Verification/FunctionalVerification/Pages/VCS.aspx

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Debuging (cont.)

Debug by Synopsyss DVE tool

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Coverage report

Source: http://www.synopsys.com/Tools/Verification/FunctionalVerification/Pages/VCS.aspx

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Coverage report (cont.)

Example of a code coverage report

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Testbench State of the art

System Verilog has OPPs support to enhance the reusability,
special construct for randomization and coverage.
There are multiple such industry level standard verification
methodologies such as VMM, OVM and UVM.
These methodologies also provide set of base class libraries
and utilities that are very useful across the entire spectrum of

verification activities

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More reference
http://www.asic-world.com/verilog/art_testbench_writing.html

http://testbench.in/

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