Threshold Voltage Modeling of Deeply Depleted

Channel MOSFET and Simulation Study of its

Analog Performances
Sarmista Sengupta1, Soumya Pandit2
Institute of Radio Physics and Electronics
University of Calcutta, Kolkata, India
sarmista.sengupta@gmail.com1, soumya.pandit.rpe@gmail.com2
Abstract This paper presents the analytical models for the
long channel and short channel threshold voltage of Deeply
Depleted Channel (DDC) MOS transistor. The model predicted
results are compared with TCAD simulation results. This paper
also reports the comparative study of the analog performances of
the DDC MOS transistor with those of a uniformly doped
transistor. The TCAD tool is calibrated with published data of
DDC MOS transistor. The better immunity of the DDC MOS
transistor in comparison to the conventional bulk MOS
transistor is demonstrated through simulation results.
Keywords DDC, Depletion depth, Doping, Intrinsic gain,
Surface potential, VT variation.

I.

INTRODUCTION

HE three potential MOS transistor structures which draw

significant interest of the researchers and semiconductor
industries as solutions to nano-scale challenges with reduced
short channel effects and low power consumption are FinFET,
ultra-thin body silicon-on-insulator (UTB-SOI) and deep
depleted channel MOS transistor [1]. Since 2001, the
International Technology Roadmap for Semiconductor (ITRS)
shows FinFET and UTB-SOI as the two successor MOS
transistors. The FinFET structure has been adopted by Intel for
its 22nm onwards chip design. The UTB-SOI devices are also
used by leading semiconductor chip designers and
manufacturers including ST Microelectronics. The deeply
depleted channel (DDC) MOS transistor has recently been
announced by SuVolta as a competitor to FinFET and UTBSOI MOS transistor, for its several advantages. These are
reduced random dopant fluctuation (RDF) effect because of
the use of lightly doped channel [2]-[3], increased carrier
mobility due to reduced scattering of the carriers in the
channel. In addition, as the DDC MOS transistor is based on
the existing bulk CMOS technology with little modifications,
the layout IPs of the bulk MOS transistors can be used for
them. The DDC MOS transistor is implemented in 65nm
process technology and reported in [3] [6].
The DDC MOS transistor, as shown in Fig. 1, has four
different doping layers deposited on the substrate. It has a low
doped epitaxial layer forming the channel followed by a
threshold voltage adjustment layer. Below this layer lies the
highly doped screening region. An anti punch through layer

follows the screening layer. The doping concentration of the

screening region is much higher than those of the channel, the
threshold voltage adjustment region and the bulk substrate.
This therefore, restricts the depletion region, which is
terminated at the edge of the screening region. The screening
region electrostatically shields the channel from the drain,
thereby the depletion width is reduced and hence the
capacitive coupling between the channel and the drain of the
DDC MOS transistor is also reduced. Therefore, the short
channel effect is less for the DDC transistor. Previous work
has been carried out for the theoretical studies of abrupt
retrograde (AR) and graded retrograde (GR) channel profiles
[7]. However the doping profile for the reported DDC device
is somewhat a combination of such two profiles.
This paper presents an analytical model of long channel
threshold voltage, threshold voltage roll off and drain induced
barrier lowering effect of the DDC MOS transistor. The
models are verified against TCAD simulation results. Some
analog performances of the DDC MOS transistor are also
studied and are compared with that of a conventional
uniformly doped MOS transistor. The output resistance and
the intrinsic gain of the DDC MOS transistor are found to be
higher than that of the uniformly doped transistor. This is
because of better immunity of the DDC MOS transistor to
short channel effects.
The rest of the paper is organized as follows. Section II
presents the analytical model developed. Section III presents
the simulation set up. The analytical and simulation results
along with discussions are provided in section IV. Finally
section V concludes the paper.
II.

MODEL DEVELOPMENT

A. Approximation of the Channel Profile

For the DDC MOS transistor, shown in Fig.1, the real
doping profile of the channel region, threshold voltage
adjustment and the screening region [6] is shown in Fig. 2. In
the present work the doping profile given is mathematically
approximated by a combination of abrupt retrograde (AR) and
two successive graded retrograde channel (GR) profiles [8] as
shown in Fig. 2. Here x1 is the depth through which the low
doped region extends. d and

d1 are the thicknesses of the two

GR regions. N S , NVT and N peak represent the doping level

F is the Fermi potential. The average channel doping

concentration N av is computed by integrating the total
Here,

depleted charge and then dividing it by the depletion depth.

1 W dm
(4)
N av
N ( x)dx
Wdm 0
Using (1) and (4) we can find

N av as,

x1 d

2Wdm

Nav N S

Wdm

NVT N S

(5)

N peak NVT

x1 d
Wdm x1 d
NVT
1
W
2
d

1
dm
The long channel threshold voltage for the DDC MOS
transistor is found out to be,

Fig. 1. Schematic diagram of a DDC MOS transistor.

VT 0 VFB 2F

q
N avWdm
Cox

where VFB is the flat band voltage,

(6)

Cox is the oxide capacitance

per unit area, and Wdm is given by (3).

Fig. 2. Non-uniform doping profile of the DDC MOS transistor.

of low doped channel and the peaks of threshold voltage

adjustment and screening layers respectively. The profile is
mathematically described as,
NS ; x x1

N NVT NS x x1 ; x x x d
1
1
(1)
S
d
N x
N Npeak NVT x x1 d ; x d x x d d
1
1
1
VT
d1

Npeak ; x1 d d1 x
where x is along the depth of the device.
B. Long Channel Threshold Voltage Model
The surface potential is obtained from one dimensional
Poissons equation along the depth of the transistor and is
given as [9],

si

Wdm

xN x dx

(2)

Integrating (2) using (1) the maximum depletion depth is

obtained as is given by (3).

Wdm

4 siF
N
2
1 S x1 d
qN peak N peak

N
d
N NS x 2 d d
1 VT x1 d 1 d1 VT
1

N peak
3
N peak
3

(3)

C. Short Channel Threshold Voltage Model

In order to derive the short channel threshold voltage model,
we start with 2-dimensional Poisson equation, which is written
as,
2 x, y 2 x, y qN av
(7)

si
x 2
y 2
Here y is in the direction along the channel.
Now the gradient of the field along x -direction is found as,
Fx x, y Fx 0, y Fx Wdm , y

x x
x
Wdm
V VFB S y
(8)
ox GS
si
toxWdm
2
The term due to lateral field Fy x, y in the Poissons

y 2

equation is treated as uniform along the depth with an average

value FSy where FSy represents Fy at the surface.

is the

channel-field spreading parameter that accounts for the nonuniform lateral field across the channel thickness. It usually
has a value between 1 and 1.3 [10]. Using (8) and the above
condition, (7) can be reduced to,
d 2S y S y qN av VGS VFB
(9)

dy 2
lt 2
si
lt 2
where S is the surface potential and lt is the characteristic
length given by,
si Wdm .
lt
tox

(10)

The boundary conditions are,

S 0 Vbi ; S L Vbi VDS

(11)

ox

Vbi is the source/drain-channel built-in potential and

VDS is the drain bias.

Using boundary conditions (11), (9) can be solved to give
S ( y ) as given by (12).
L

lt
Vbi 1 e

S y
L

2 sinh
lt

lt

Vbi e 1 VDS

2 sinh
lt

V
DS y

l
e t

(12)

y
l
e t

Here is a parameter defined as,

q N av

si

The surface potential is minimum at

lt 2 VGS VFB .

y0 which can be

found by solving dS y dy 0 . Thus the minimum surface

potential is, S min S y0 . At threshold condition,

S min

becomes 2F . Thus (12) gives a second order polynomial in

VT ( VT 0 VT ). The root of the polynomial is found to be,

L
cosh
2 Vbi S VDS
2lt
VT

L
L
2 sinh 2
sinh 2
2lt
2lt

Vbi S Vbi S VDS

(13)

VT being a function of channel length L and drain bias

VDS , (13) represents the threshold voltage shift due to short

channel effect and DIBL.
III.

DEVICE STRUCTURES A ND SIMULATION SETUP

The oxide thickness of the device is 1.8nm as per 65 nm

node requirement given by the ITRS. The concentrations for
the deep source/drain and the extensions are 3.71020 cm-3 and
2.51020 cm-3 respectively. The source/drain contacts are made
up of aluminum. The concentration of the low doped channel
is 21017 cm-3. The peak concentrations of the threshold
voltage adjustment and screening layers are taken to be 31018
cm-3 and 31019 cm-3 respectively. The poly gate concentration
is selected to obtain the desired VT as reported in [4]. The
channel length is taken to be 45 nm.
The uniform doped channel device (UNIF) has a substrate
concentration same as the background concentration of the
DDC device, i.e. 11018 cm-3.
The simulations for the device structures are done using
version 5.16.3.R of Silvaco ATLAS 2D device simulator.
Shockley-Read-Hall recombination model and incomplete
ionization models are incorporated in the simulation
procedure. Shockley-Read-Hall recombination model and
incomplete ionization models are incorporated in the
simulation procedure. The carriers are made to obey Fermi
statistics and energy balance equations are solved using

Hydrodynamic model. All the simulations are done at 300 K.

Lombardi CVT model is used for mobility modeling. The
mobility calibration is performed with reference to reported
data [11]. Good agreement between the TCAD simulated and
the experimental data can be observed from Fig. 3. The
accuracy of the device simulation crucially depends upon
appropriate grid allocation in the simulation process. In this
work the accuracy of simulation results is assured by abiding
the guidelines given in [12].
-3

Drain Current IDS (A/ m) in logscale

Here

10

VDS = 0.9 V

-4

10

VDS = 0.1 mV

-5

10

L = 45 nm
-6

10

Experimental
Calibrated

-7

10

-8

10

0.0

0.2

0.4
0.6
0.8
1.0
1.2
Gate-to-Source Voltage VGS (V)

1.4

Fig. 3. Calibration against experimental data [9].

IV.

RESULTS AND DISCUSSIONS

A. Analytical Model Results

The surface electrostatic potential of the n-channel DDC
MOS transistor as obtained from the derived analytical model
is compared with TCAD simulation results and is shown in
Fig.4. The observation is made for a channel length of 45 nm.
Two bias conditions ( VGS =0.2V, VDS =0.1V and

VGS =0.2V, VDS =0.8V) are considered here. A close

agreement between the simulation and model predicted result
is observed. The threshold voltage roll off and the DIBL
characteristics of the DDC MOS transistor, as obtained from
the derived analytical model as well as TCAD simulation
results are shown in Fig. 5 and Fig. 6 respectively. It is
observed that the model predicted results closely match with
the TCAD simulation results. These demonstrate the accuracy
of the derived model.
B. TCAD Simulation Study of Analog Performances
Fig. 7 and 8 present a comparative study of analog
performances between the DDC and UNIF transistors. Fig. 7
shows the variation of the output resistance and intrinsic gain
with the gate overdrive voltage for the two devices. It is
observed that DDC offers better output resistance and intrinsic
gain. This is because of the fact that the DDC MOS transistor
is better immune from the DIBL phenomenon.
It has been found that the values of Wdm are 24.2 nm and
35.5 nm respectively for the DDC and UNIF devices. This
lowering of depletion depth reduces the characteristic length
as observed from (10). Reduction in characteristic length in
turn reduces the denominator of threshold voltage shift
according to (13) thus offering lesser threshold voltage shift
due to SCE and DIBL.
The improvement in maximum intrinsic gain is observed to
be 5.26 dB. The variation of the transconductance generation
efficiency and Early voltage parameter with gate over-drive

gate voltage for the two transistors are shown in Fig. 8.

The authors thank TEQIP Phase-II, University of Calcutta

and D.S.T., Govt. of India (under Fast Track Young Scientist
Scheme) for supporting the research work financially.

Model
TCAD data

VDS = 0.8V

0.4
0.2
0.0

DDC
UNIF

VGS = 0.2 V
VDS = 0.1 V
0.2
0.4
0.6
0.8
1.0
Normalized distance from source to drain (y/L)

L = 45 nm
VDS = 0.4 V

10

10

10

10

Fig. 4. Comparison between model and simulation results for surface potential.
VDS = 0.8 V

0.5

-0.2

VDS = 50 mV

0.0
0.2
0.4
0.6
Gate overdrive voltage VGS-VT (V)

25

Model
TCAD data

0.3

-1

0.1
200n

400n
600n
800n
Channel length L (m)

DDC
UNIF

15

0.4
10
0.2

0
-0.2

Model
TCAD data

Threshold voltage VT (V)

0.28

0.6

L = 45 nm
VDS = 0.4 V

Fig. 5. Comparison between model and simulation results for VT roll-off.

0.32
0.30

0.8

20

0.2

10
0.8

Fig. 7. Comparison of gain and output resistance for DDC and UNIF devices.

0.4

gm/ID (V )

Threshold voltage VT (V)

0.0
0.2
0.4
0.6
Gate overdrive voltage VGS-VT (V)

Early voltage VA (V)

0.6

10

VGS = 0.2 V

Intrinsic gain G (gmRO)

Surface potential S (V)

0.8

10

L = 45 nm

1.0

Output resistance RO (. m) in logscale

1.4
1.2

ACKNOWLEDGMENT

0.0
0.8

Fig. 8. Comparison of and early voltage for DDC and UNIF devices.

REFERENCES

L = 45 nm

0.26

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0.24

[3]

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0.0

0.2
0.4
0.6
Drain-to-source voltage VDS (V)

0.8

Fig. 6. Comparison between VT due to DIBL from model and simulation results.

It is observed that the DDC MOS transistor has better early

voltage. However the two devices have comparable
transconductance generation efficiency.
V.

CONCLUSION

The depletion depth of the DDC MOS transistor terminates

at the edge of highly doped screening region. Thus
characteristic length decreases and in turn lessens threshold
voltage shift due to SCE and DIBL with respect to a uniformly
doped device. Close agreement between the model predicted
results and those obtained from TCAD simulation
demonstrates the accuracy of the model. Comparison of the
performances between the DDC and UNIF transistors depicts
the improvement achieved by the former one.

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