Module 5

Some of the notes are given in the Xerox center

What is a Logic Family?
In Digital Designs, our primary aim is to create an Integrated Circuit (IC).
A Circuit configuration or arrangement of the circuit elements in a special manner will result in a
particular Logic Family.
What are the advantages of creating different Logic Families?
Electrical Characteristics of the IC will be identical. In other words, the different parameters like
Noise Margin, Fan In, Fan Out etc will be identical.
Different ICs belonging to the same logic families will be compatible with each other.
Some Characteristics we consider for the selection of a particular Logic Family are:

Supply voltage range

Speed of response

Power dissipation

Input and output logic levels

Current sourcing and sinking capability

Fan-out

Noise margin

The basic Classification of the Logic Families are as follows:

Bipolar Devices

MOS Devices

Hybrid Devices

Bipolar Families:
1. Diode Logic (DL)

2. Resistor Transistor Logic (RTL)

3. Diode Transistor Logic (DTL)
4. Transistor- Transistor Logic (TTL)
5. Emitter Coupled Logic (ECL) or Current Mode Logic (CML)
6. Integrated Injection Logic (IIL)
MOS Families:
1. P-MOS Family
2. N-MOS Family
3. Complementary-MOS Family
1. Standard C-MOS
2. Clocked C-MOS
3. Bi-CMOS
4. Pseudo N-MOS
5. C-MOS Domino Logic
6. Pass Transistor Logic
Hybrid Family:
1. Bi-CMOS Family
TTL: Transistortransistor logic (TTL) is a class of digital circuits built from bipolar junction
transistors (BJT) and resistors. It is called transistortransistor logic because both the logic gating
function (e.g., AND) and the amplifying function are performed by transistors (contrast this with
RTL and DTL). TTL is notable for being a widespread integrated circuit (IC) family used in
many applications such as computers, industrial controls, test equipment and instrumentation,
consumer electronics, synthesizers, etc. The designation TTL is sometimes used to mean TTLcompatible logic levels, even when not associated directly with TTL integrated circuits, for
example as a label on the inputs and outputs of electronic instruments. The basic Input for the
TTL family is the NAND Gate. The TTL circuit uses a special multi-emitter transistor that is
fabricated with several emitters at its input.The no. of emitters depend on the fan-in of the
circuit.

ECL: Emitter-Coupled Logic is based on the use of a multi-input differential amplifier to

amplify and combine the digital signals, and emitter followers to adjust the dc voltage levels. As
a result, none of the transistors in the gate ever enter saturation, nor do they ever get turned
completely off. The transistors remain entirely within their active operating regions at all times.
As a result, the transistors do not have a charge storage time to contend with, and can change
states much more rapidly. Thus, the main advantage of this type of logic gate is extremely high
speed. ECL's major disadvantage is that each gate continuously draws current, which means it
requires (and dissipates) significantly more power than those of other logic families, especially
when quiescent.
A/D and D/A Convertors:
R-2R DAC: An alternative to the binary-weighted-input DAC is the so-called R/2R DAC, which
uses fewer unique resistor values. A disadvantage of the former DAC design was its requirement
of several different precise input resistor values: one unique value per binary input bit.
Manufacture may be simplified if there are fewer different resistor values to purchase, stock, and
sort prior to assembly.
Of course, we could take our last DAC circuit and modify it to use a single input resistance
value, by connecting multiple resistors together in series:

Unfortunately, this approach merely substitutes one type of complexity for another: volume of
components over diversity of component values. There is, however, a more efficient design
methodology.
By constructing a different kind of resistor network on the input of our summing circuit, we can
achieve the same kind of binary weighting with only two kinds of resistor values, and with only a
modest increase in resistor count. This "ladder" network looks like this:

Mathematically analyzing this ladder network is a bit more complex than for the previous circuit,
where each input resistor provided an easily-calculated gain for that bit. For those who are
interested in pursuing the intricacies of this circuit further, you may opt to use Thevenin's
theorem for each binary input (remember to consider the effects of the virtual ground), and/or
use a simulation program like SPICE to determine circuit response. Either way, you should
obtain the following table of figures:

--------------------------------| Binary | Output voltage |

--------------------------------| 000 |
0.00 V |
--------------------------------| 001 |
-1.25 V |
--------------------------------| 010 |
-2.50 V |
--------------------------------| 011 |
-3.75 V |
--------------------------------| 100 |
-5.00 V |
--------------------------------| 101 |
-6.25 V |
--------------------------------| 110 |
-7.50 V |
--------------------------------| 111 |
-8.75 V |
---------------------------------

As was the case with the binary-weighted DAC design, we can modify the value of the feedback
resistor to obtain any "span" desired. For example, if we're using +5 volts for a "high" voltage
level and 0 volts for a "low" voltage level, we can obtain an analog output directly corresponding
to the binary input (011 = -3 volts, 101 = -5 volts, 111 = -7 volts, etc.) by using a feedback
resistance with a value of 1.6R instead of 2R.
Successive Approximation A/D Convertor:
This type of converter is used to convert analog voltage to its corresponding digital output. The
function of the analog to digital converter is exactly opposite to that of a digital to analog
converter. Like a D/A converter, an A/D converter is also specified as 8, 10, 12 or 16 bit. Though
there are many types of A/D converters, we will be discussing only about the successive
approximation type.
Successive Approximation Type Analog to Digital Converter
A successive approximation A/D converter consists of a comparator, a successive approximation
register (SAR), output latches, and a D/A converter. The circuit diagram is shown below.

The main part of the circuit is the 8-bit SAR, whose output is given to an 8-bit D/A converter.
The analog output Va of the D/A converter is then compared to an analog signal Vin by the
comparator. The output of the comparator is a serial data input to the SAR. Till the digital output
(8 bits) of the SAR is equivalent to the analog input Vin, the SAR adjusts itself. The 8-bit latch at
the end of conversation holds onto the resultant digital data output.

Working:
At the start of a conversion cycle, the SAR is reset by making the start signal (S) high. The MSB
of the SAR (Q7) is set as soon as the first transition from LOW to HIGH is introduced. The
output is given to the D/A converter which produces an analog equivalent of the MSB and is
compared with the analog input Vin.
If comparator output is LOW, D/A output will be greater than Vin and the MSB will be cleared by
the SAR.
If comparator output is HIGH, D/A output will be less than Vin and the MSB will be set to the
next position (Q7 to Q6) by the SAR.
According to the comparator output, the SAR will either keep or reset the Q6 bit. This process
goes on until all the bits are tried. After Q0 is tried, the SAR makes the conversion complete
(CC) signal HIGH to show that the parallel output lines contain valid data. The CC signal in turn
enables the latch, and digital data appear at the output of the latch. As the SAR determines each
bit, digital data is also available serially. As shown in the figure above, the CC signal is
connected to the start conversion input in order to convert the cycle continuously.
The biggest advantage of such a circuit is its high speed. It may be more complex than an A/D
converter, but it offers better resolution.
Advantages:

Capable of high speed and reliable

Medium accuracy compared to other ADC types

Good tradeoff between speed and cost

Capable of outputting the binary number in serial (one bit at a time) format.

Disadvantages:

Higher resolution

successive approximation ADCs will be slower

Speed limited to ~5Msps

PS:: If you have time, please study the dual slope A/D
convertor from the book as well.
Module 4:
ASIC: An application-specific integrated circuit (ASIC), is an integrated circuit (IC) customized
for a particular use, rather than intended for general-purpose use. For example, a chip designed to
run in a digital voice recorder or a high-efficiency Bitcoin miner is an ASIC. Application-specific
standard products (ASSPs) are intermediate between ASICs and industry standard integrated
circuits like the 7400 or the 4000 series.
As feature sizes have shrunk and design tools improved over the years, the maximum complexity
(and hence functionality) possible in an ASIC has grown from 5,000 gates to over 100 million.
Modern ASICs often include entire microprocessors, memory blocks including ROM, RAM,
EEPROM, flash memory and other large building blocks. Such an ASIC is often termed a SoC
(system-on-chip). Designers of digital ASICs often use a hardware description language (HDL),
such as Verilog or VHDL, to describe the functionality of ASICs.
CPLD: A complex programmable logic device (CPLD) is a programmable logic device with
complexity between that of PALs and FPGAs, and architectural features of both. The main
building block of the CPLD is a macrocell, which contains logic implementing disjunctive
normal form expressions and more specialized logic operations.
Some of the CPLD features are in common with PALs:
Non-volatile configuration memory. Unlike many FPGAs, an external configuration ROM isn't
required, and the CPLD can function immediately on system start-up.
For many legacy CPLD devices, routing constrains most logic blocks to have input and output
signals connected to external pins, reducing opportunities for internal state storage and deeply
layered logic. This is usually not a factor for larger CPLDs and newer CPLD product families.
Other features are in common with FPGAs:
Large number of gates available. CPLDs typically have the equivalent of thousands to tens of
thousands of logic gates, allowing implementation of moderately complicated data processing
devices. PALs typically have a few hundred gate equivalents at most, while FPGAs typically
range from tens of thousands to several million.
The most noticeable difference between a large CPLD and a small FPGA is the presence of onchip non-volatile memory in the CPLD. The characteristic of non-volatility makes the CPLD
devices used in modern digital designs for performing "boot loader" functions before handing

over control to other devices not having this capability. A good example is where a CPLD is used
to load configuration data for an FPGA from non-volatile memory.

Implementing functions with multiplexers

We could implement a function of n variables with an n-to-1 multiplexer.
The muxselect inputs correspond to the functions input variables, and are used to select one
row of the truth table.
Each muxdata input corresponds to one output from the truth table. We connect 1 to data input
Di for each function minterm mi, and we connect 0 to the other data inputs.
For example, here is the function, C(X,Y,Z) = m(3,5,6,7). Implement it using 8x1 MUX.
Given below is the truth table and the MUX.
X
0
0
0
0
1
1
1
1

Y
0
0
1
1
0
0
1
1

Z
0
1
0
1
0
1
0
1

C
0
0
0
1
0
1
1
1

X,Y and Z are taken as the selection lines. The data inputs are either 1 or 0.
The same function C(X,Y,Z) = m(3,5,6,7) can be implemented using 4x1 MUX. In this
instead of using three variables to select one row of the truth table, well use two variables to
pick a pair of rows in the table. The multiplexer data inputs will be functions of the remaining
variable. X and Y are taken as the select inputs and Z as the data input as X and Y values are
constant throughtout the truth table however, the value of Z varies. So, C is a function of Z only.

When XY=00, C=0

When XY=01, C=Z
When XY=10, C=Z
When XY=11, C=1
So, the MUX is: