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IC Package Release - Version Description
IC Package Release - Version Description
IC Package Release - Version Description
2014-15 release
IC Package
release_version
ASSURA 4.1
ASSURA 4.1
ASSURA 4.1
CONFRML14.1
CONFRML14.1
CONFRML14.1
CONFRML14.1
CTOS 14.1
EDI 14.1
EDI 14.1
EDI 14.1
EDI 14.1
EDI 14.1
EDI 14.1
EDI 14.1
EDI 14.1
ET 14.1
ET 14.1
ET 14.1
ET 14.1
ET 14.1
ETS 13.1
ETS 13.1
ETS 13.1
ETS 13.1
ETS 13.1
EXT 14.1
EXT 14.1
EXT 14.1
EXT 14.1
EXT 14.1
Description
Assura(TM) Design Rule Checker
Assura(TM) Layout Vs. Schematic Verifier
Assura(TM) Multiprocessor Option
CCD Multi-Constraint Check Option
Encounter (R) Conformal Constraint Designer - XL
Encounter Conformal Low Power - GXL
Encounter Conformal ECO Designer - GXL
C-to-Silicon Compiler - L
Encounter Digital Implementation System XL
Encounter CPU Accelerator Option
Encounter Mixed Signal GXL Option
Encounter Giga Scale GXL Option
Encounter Universal 20 GXL Option
Encounter Clock Concurrent Optimization
Encounter Advanced Node GXL Option
Encounter Low Power GXL Option
Encounter True Time ATPG Advanced
Option to RC - DFT Architect Advanced
Encounter Test LBIST Option
Encounter Test Advanced MBIST Option
Encounter Diagnostics Basic
Encounter Library Characterizer - GXL
Encounter Power System XL
EPS Advanced Analysis GXL Option
Encounter Timing System-XL
ETS Advanced Analysis GXL Option
Cadence QRC Advanced Modeling20 GXL Option
Cadence QRC Extraction - XL
Cadence QRC Advanced Modeling GXL Option
Cadence QRC Advanced Analysis GXL Option
Cadence QRCX Display Technology Option
Europractice Cadence
2014-15 release
IC 6.1.6
IC 6.1.6
IC 6.1.6
IC 6.1.6
IC 6.1.6
IC 6.1.6
IC 6.1.6
IC 6.1.6
IC 6.1.6
IC 6.1.6
IC 6.1.6
IC 6.1.6
IC 6.1.6
IC 6.1.6
IC 6.1.6
IC 6.1.6
IC 6.1.6
IC 6.1.6
IC 6.1.6
IC 6.1.6
IC 6.1.6
IC 6.1.6
IC 6.1.6
IC 6.1.6
IC 6.1.6
IC 6.1.6
IC 6.1.6
IC 6.1.6
IC 6.1.6
IC 6.1.6
IC 6.1.6
IC 6.1.6
IC 6.1.6
Europractice Cadence
2014-15 release
IC 6.1.6
IC 6.1.6
IC 6.1.6
INCISIV 14.1
INCISIV 14.1
INCISIV 14.1
INCISIV 14.1
INCISIV 14.1
INCISIV 14.1
INCISIV 14.1
INCISIV 14.1
INCISIV 14.1
INCISIV 14.1
INCISIV 14.1
INCISIV 14.1
LIBERATE 13.1
LIBERATE 13.1
LIBERATE 13.1
LIBERATE 13.1
LIBERATE 13.1
LIBERATE 13.1
LIBERATE 13.1
LIBERATE 13.1
LIBERATE 13.1
LIBERATE 13.1
LIBERATE 13.1
LIBERATE 13.1
Europractice Cadence
2014-15 release
MMSIM 13.1
MMSIM 13.1
MMSIM 13.1
MMSIM 13.1
MMSIM 13.1
MMSIM 13.1
MVS 14.1
MVS 14.1
PVS 14.1
PVS 14.1
PVS 14.1
PVS 14.1
PVS 14.1
PVS 14.1
PVS 14.1
PVS 14.1
PVS 14.1
PVS 14.1
PVS 14.1
PVS 14.1
PVS 14.1
PVS 14.1
PVS 14.1
PVS 14.1
PVS 14.1
PVS 14.1
PVS 14.1
RC 14.1
RC 14.1
RC 14.1
RC 14.1
Europractice Cadence
2014-15 release
SSV 14.1
SSV 14.1
SSV 14.1
SSV 14.1
SSV 14.1
SSV 14.1
VIPCAT 11.3
VIPCAT 11.3
VIPCAT 11.3
VIPCAT 11.3
VIPCAT 11.3
VIPCAT 11.3
VIPCAT 11.3
VIPCAT 11.3
VIPCAT 11.3
VIPCAT 11.3
VIPCAT 11.3
VIPCAT 11.3
VIPCAT 11.3
VIPCAT 11.3
VIPCAT 11.3
Europractice Cadence
2014-15 release
Systems Package
release_version
ASI 16.6
ASI 16.6
ASI 16.6
ASI 16.6
ASIS 16.65
ASIS 16.65
ASIS 16.65
INCISIV 14.1
INCISIV 14.1
INCISIV 14.1
INCISIV 14.1
INCISIV 14.1
INCISIV 14.1
INCISIV 14.1
INCISIV 14.1
INCISIV 14.1
INCISIV 14.1
INCISIV 14.1
INCISIV 14.1
SPB 16.6
SPB 16.6
SPB 16.6
SPB 16.6
SPB 16.6
SPB 16.6
SPB 16.6
SPB 16.6
SPB 16.6
SPB 16.6
SPB 16.6
Description
Allegro Sigrity Power Aware SI Option
Allegro Sigrity System Serial Link Option
Allegro Sigrity Package Assessment and Extraction Option
Allegro Sigrity SI Base
Allegro Sigrity Power Integrity Signoff and Optimization Option
Allegro Sigrity PI Base
Cadence IO-SSO Analysis Suite
AMS Designer with Flexible Analog Simulation
Virtuoso AMS Designer Verification Option
Incisive Enterprise Simulator - XL
Digital Mixed Signal Option to IES
Incisive Advanced Option
Verifault(R)-XL simulator
Incisive Low-Power Simulation Option
Incisive Enterprise Manager
Cadence(R) Export Model Packager
Incisive Software Extensions
Incisive Enterprise Verifier - XL
Incisive Formal Verifier
Allegro(R) Design Authoring
Allegro PCB Designer
Allegro PCB High-Speed Option
Allegro PCB Miniaturization Option
Allegro(R) PCB Team Design Option
Allegro PCB Routing Option
Allegro PCB Design Planning Option
Allegro(R) PCB Librarian
Allegro(R) ASIC Prototyping with FPGA's
Allegro Design Authoring Multi-Style Option
Allegro(R) AMS Simulator
Europractice Cadence
2014-15 release
SPB 16.6
SPB 16.6
SPB 16.6
SPB 16.6
SPB 16.6
SPB 16.6
SPB 16.6
SPB 16.6
VIPCAT 11.3
VIPCAT 11.3
VIPCAT 11.3
VIPCAT 11.3
VIPCAT 11.3
VIPCAT 11.3
VIPCAT 11.3
VIPCAT 11.3
VIPCAT 11.3
VIPCAT 11.3
VIPCAT 11.3
VIPCAT 11.3
VIPCAT 11.3
VIPCAT 11.3
VIPCAT 11.3
Europractice Cadence
2014-15 release
TLM Package
release_version
CONFRML14.1
CONFRML14.1
CONFRML14.1
CTOS 14.1
INCISIV 14.1
INCISIV 14.1
INCISIV 14.1
INCISIV 14.1
INCISIV 14.1
INCISIV 14.1
INCISIV 14.1
INCISIV 14.1
INCISIV 14.1
INCISIV 14.1
INCISIV 14.1
INCISIV 14.1
INCISIV 14.1
RC 14.1
RC 14.1
RC 14.1
VIPCAT 11.3
VIPCAT 11.3
VIPCAT 11.3
VIPCAT 11.3
VIPCAT 11.3
VIPCAT 11.3
VIPCAT 11.3
VIPCAT 11.3
VIPCAT 11.3
VIPCAT 11.3
Description
Encounter Conformal Low Power - GXL
Encounter (R) Conformal Constraint Designer - XL
CCD Multi-Constraint Check Option
C-to-Silicon Compiler - L
Virtuoso AMS Designer Verification Option
Digital Mixed Signal Option to IES
Incisive Advanced Option
Verifault(R)-XL simulator
Incisive Low-Power Simulation Option
AMS Designer with Flexible Analog Simulation
Incisive Enterprise Verifier - XL
Incisive Enterprise Manager
Cadence(R) Export Model Packager
Incisive Software Extensions
Cadence System Creator - L
Incisive Formal Verifier
Incisive Enterprise Simulator - XL
Encounter RTL Compiler - XL
Encounter RTL Compiler CPU Accelerator Option
Encounter RTL Compiler Low Power Option
VIP for PCI Express 3.0
VIP for USB 3.0 & OTG
Memory Model for Flash ONFi 3
Memory Model for LRDIMM
Memory Model Portfolio
VIP for HDMI 1.4
VIP for OCP 3.0
SOC Portfolio
VIP for PCI Express 1.1 & 2.0 PureSuite - Initial Release
VIP for SATA 6G
Europractice Cadence
2014-15 release
VIPCAT 11.3
VIPCAT 11.3
VIPCAT 11.3
VIPCAT 11.3
VIPCAT 11.3
Europractice Cadence
2014-15 release
PCB Studio Package
release_version
ASI 16.6
SPB 16.6
SPB 16.6
SPB 16.6
SPB 16.6
Description
Allegro Sigrity SI Base
Allegro(R) Design Entry CIS
Allegro PCB Designer
Allegro(R) AMS Simulator
Allegro 2 FPGA System Planner Option
Europractice Cadence
2014-15 release
Cynthesizer Optional Package
release_version
FORTE
Cynthesizer Low Power
FORTE
Interface Generator
Virtual Systems Platform Optional Package
Release
Description
INCISIV 14.1
Cadence System Creator - L
3DIC Optional Package
Release
Description
EDI 13.1
Encounter Stacked Die GXL Option
IC 6.1.6
Virtuoso Stacked Die Option
Virtuoso Advanced Node Optional Package
Release
Description
ICADV 12.1
Virtuoso Advanced Node Framework
ICADV 12.1
Virtuoso Implementation Aware Design Option
ICADV 12.1
Virtuoso Advanced Node Option for Layout
EXT 14.1
Advanced Node Modeling Option
MVS 14.1
Litho Physical Analyzer
MVS 14.1
Distributed Process for 8 CPUs
SIP Optional Package
Release
SPB 16.6
SPB 16.6
SPB 16.6
Description
Cadence SiP Digital Architect - GXL
Virtuoso SiP Architect XL
Cadence Chip Integration Option
Description