Chapter-2

Literature Review
Daniel Baumgartner et al. [1] reports their work on a performance benchmark of different
implementations of some low-level vision algorithms. The algorithms are implemented on both
Digital Signal Processor (DSP) and Field Programmable Gate Array (FPGA) high-speed
embedded platforms. The target platforms are a TI TMS320C6414 DSP and an Altera Stratix
FPGA. The implementations are evaluated, compared and discussed. The paper claims that the
DSP implementations outperform the FPGA implementations, but at the cost of spending all its
resources to these tasks. FPGAs, however, are well suited to algorithms, which benefit from
parallel execution. In this work a performance benchmark of several DSP and FPGA
implementation of some low-level image processing algorithms was presented. Three algorithms
a Gaussian pyramid, a Bayer filter and a Sobel filter were implemented on both a high-end
DSP and on high-end FPGAs. Results shown indicate that all three low-level algorithms are
processed faster on the DSP than on the FPGA. The DSP implementation of the Gaussian
pyramid is about four times faster than the FPGA implementation, while the Bayer and the Sobel
filters perform about two times faster on the DSP.
Thus, the DSP outperforms the FPGA on a sub-function basis. However, from a system view the
FPGA benefits due to parallelism. Currently, authors are investigating how they can make use of
the advantages of both technologies to build a new platform which is based on both DSPs and
FPGAs. That platform would enable to split algorithms and to execute parts of the algorithm on
the processing unit (DSP or FPGA) which is better suited for.
Zhou Jianjun, Zhou Jianhong [2] introduces a kind of high-speed digital image
processing system based on ARM-DSP. This system increases the processing speed of digital
image and realizes accurate recognition of figures (characters) in images. The paper also
discusses the hardware structure of image tracking system taking ARM-DSP as main frame and
the development process and control flow of DSP. Finally, it looks forward to the development
prospect of image processing. This paper studies basic theories of digital image processing. The
system is roughly divided into two parts from function: DSP image acquisition and processing
part and ARM real-time control application part. Because the time sequence of ARM is different
from that of DSP, the data between the two parts is transmitted by a two-port RAM. It not only
meets the time sequence requirements of the system, but also improves the work efficiency of the
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system and makes the system more stable and reliable. Taking digital signal processor DSP and
complex programmable logic device as core, this paper constructs a recognition hardware
platform, along with the rapid development of large scale integrated circuit.
L. Siler , C. Tanougast , A. Bouridane [3] proposed approach that has resulted in much
improved processing times with smaller and flexible area utilization. Moreover, the proposed
architecture is scalable and can be tailored to process larger images. To demonstrate the
effectiveness of the approach, the architecture was implemented on Xilinx Virtex-FPGA
technology using VHDL structural description. The whole architecture was implemented into a
single FPGA without the use of any external memory and/or host machine.
Konstantinos Konstantinides [4] Hewlett- Packard, Reviewed a book on Embedded
Image Processing on the TMS320C6000 DSP: Examples in Code Composer Studio and
MATLAB by Shehrzad Qureshi, Springer, 2005, [14], the book is intended for signal and image
processing practitioners or software developers that plan to use a TI DSP. However, most of the
programming techniques demonstrated here can easily be applied to other embedded platforms.
According to the author, all examples have been tested and debugged on either the TI C6701
Evaluation Module or the C6416 DSP Starter Kit. focus on embedded image processing and, in
particular, on the efficient implementation of image processing algorithms on the TI
TMS320C6000 family of DSPs. the book is well written and succeeds in filling a big void in
image processing literature, tackling how to efficiently implement signal and image processing
algorithms using embedded processors.
Duan Jinghong et al. [5] presented an image processing system structure based on DSP
and FPFA, that is DSP is used as advanced image processing unit and FPGA as logic unit for
image sampling and display. The hardware configuration and working principle is introduced
firstly, and then some key problems which include of image data stored mode, color space
conversion and image transmission based on EDMA are described. Finally the program
flowchart for developing image processing software is given. The developed system can acquire
image, display image and make some image processing operations which include of geometry
transform, orthographic transform, operations based on pixels, image compression and color
space conversion. TMSC6713 DSP board is used as executing image processing algorithms. The
CPU on the board is TI DSP chip TMSC6713 which is a high performance float digital signal

processor with 255MHz.There are 1Mbits RAM, 8Mbytes with 32bit exterior expanded memory
SDRAM, 512Kbytes Flash, 4 user accessible LEDs and 4 DIP switches.
K. Benkrid , D. Crookes, A. Benkrid [6] proposed High level descriptions of task-specific
architectures specifically optimised for Xilinx XC4000 FPGAs. The library also contains high
level skeletons for compound operations, whose implementations include task-specific
optimisations. Skeletons are parameterisable, and different skeletons for the same operation can
be provided, for instance for different arithmetic representations. This gives the user a range of
implementation choices. This in turn supports experimentation with different implementations
and choosing the most suitable one for the particular constraints in hand (e.g. speed and area)
D. Chaikalis , N.P. Sgouros, D. Maroulis [7] stated that the parallel digital system realizes
a number of computational-heavy calculations in order to achieve real-time operation. The
processing elements can bedeployed in a systolic architecture and operate on multiple image
areas simultaneously. Moreover, memoryorganization allows random access to image data and
copes with the increased processing throughputof the system. Operating results reveal that the
proposed architecture is able to process 3D data at areal-time rate. The proposed system can
handle large sized InIms in real time and outputs 3D scenes of enhanced depth and detailed
texture, which apply to emerging 3D applications.
Pasquale Corsonello et. al.[8] implemented a widely known wavelet-based (SPIHT). The
computationally intensive 2Dwavelet-transform is performed by compression method, i.e. the
Set Partitioning In Hierarchical Trees algorithm means of custom circuits. The aim of this work
is to demonstrate and verify the feasibility of a compact and programmable image compression
sub-system that uses just one low-cost FPGA device. The entire system consumes just 1637
slices of an XC2V chip, it runs at 100 MHz clock frequency and reaches a speed performance
suitable for several real-time applications.

P Karthigaikumara, Anumolb, K Baskaranc, [9] Digital watermarking is the process of

embedding information into a digital signal in a way that is difficult to remove. The fragile and
semi fragile watermarking techniques have some serious disadvantages like increased use of
resources, larger area requirements, and high power consumption. In order to overcome this,
robust invisible watermarking technique is used in this paper for images. A watermark is
embedded in the host signal for authentication. The whole algorithm is designed and simulate
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dusing simulink block in MATLAB and then the algorithm is converted into Hardware
Description Language (HDL) using Xilinx system generator tool. The algorithm is prototyped in
virtex -6 (vsx315tff1156-2) FPGA. The results show that proposed designcan operate at
maximum frequency 344 MHz in Vertex 6 FPGA by consuming only 1.1 % of available device.
Samir Tagzout, Karim Achour, Oualid Djekoune [10] In this paper a novel algorithm for
computing the Hough transform is introduced. The basic idea consists in usinga combination of
an incremental method with the usual Hough transform expression to join circuit performances
and accuracy requirements. The algorithm is primarily developed to "t "eld programmable gate
arrays (FPGA) implementation that have become a competitive alternative for high-performance
digital signal processing applications. The induced architecture presents a high degree of
regularity, making its VLSI implementation very straightforward. This implementation may be
achieved by generator program, assuring a shorter design cycle and a lower cost. For illustration,
implementation results of 8-bit image pixels is given.
B. Krill et. al [11] Three intellectual property (IP) cores used in pre-processing and
transform blocks of compression systems including colour space conversion (CSC), twodimensional biorthogonal discrete wavelet transform (2-D DBWT) and three-dimensional Haar
wavelet transform (3-D HWT) have been selected to validate the proposed Dynamic Partial
Reconfiguration (DPR)design flow and environment. Results obtained reveal that the proposed
environment has a better solution providing: a scriptable program to establish the communication
between the field programmable gate array (FPGA) with IP cores and their host application,
power consumption estimation for partial reconfiguration area and automatic generation of the
partial and initial bitstreams. The design exploration offered by the proposed DPR environment
allows the generation of efficient IP cores with optimized area/speed ratios.
R. Haralick et al [12] defined classification in generic sense as the categorization of some
input data into identifiable classes via the extraction of significant features or attributes of the
data from a background of irrelevant details. The perception of texture is believed to play an
important role in the human visual system for recognition and interpretation and understanding
of synthetic and natural image objects. The interpretation of images is only possible if classifiers
can effectively label previously unseen objects. The recognition ability of classifiers depends on
the quality of feature used as well as the amount of training data available to them. Image
features are mostly extracted on shape and texture of segmented objects. They proposed a set of
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14 textural features extracted from a co occurrence matrix. They reported an overall accuracy
rate of 84 percent on eleven types of textures obtained from satellite images. The paper, thus,
lays foundation for texture based image classification using exhaustive features extracted from
one of the best texture description method i.e. the co-occurrence matrix.
Michael Unser [13] has proposed sum and difference histograms as an alternative to
usual co-occurrence matrices for texture analysis. The sum and difference of two random
variables with same variances are de-correlated and define the principal axes of their associated
joint probability function. Two maximum likelihood classifiers are presented depending on the
type of object used for texture characterization. He has proved that the sum and difference
histograms used conjointly, perform equally well as co-occurrence matrices with decrease in
computation time and memory storage. The paper, thus, suggests a novel texture feature in the
form of sum and difference histograms as an alternative to spatial gray level dependence matrix,
which can be used for texture classification.
P.S.Hiremath and S.Shivashankar [14] presents a feature extraction algorithm using
wavelet decomposed images of an image and its complementary image for texture classification.
The features are constructed from the different combination of sub-band images. These features
offer a better discriminating strategy for texture classification and enhance the classification rate.
The Euclidean distance measure and the minimum distance classifier are used to classify the
texture.

Lucia Dettori, Lindsay Semler [15] focuses on comparing the discriminating power of
several multi-resolution texture analysis techniques using wavelet, ridgelet, and curvelet-based
texture descriptors. The approach consists of two steps: automatic extraction of the most
discriminative texture features of regions of interest and creation of a classifier.
The comparison between wavelet, ridgelet, and curvelet is carried out and the paper thus
suggests that in comparing the three wavelet-based features, the Haar based descriptors
outperformed both Daubechies and Coiflet for most images and performance measures Coiflet
and Daubechies had similar performance, however Coiflet performed slightly higher with
accuracy rates in the 8593% compared to Daubechies at 8393%. Within all the wavelets, the
Haar wavelet outperformed the others.

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Trygve Randen, John Hkon Husy[16] reviewed most major filtering approaches to
texture feature extraction and perform a comparative study. Filtering approaches included are
Laws masks, ring/wedge filters, dyadic Gabor filter banks, wavelet transforms, wavelet packets
and wavelet frames, quadrature mirror filters, discrete cosine transform, eigen filters, optimized
Gabor filters, linear predictors, and optimized finite impulse response filters. The features are
computed as the local energy of the filter responses. The effect of the filtering is highlighted,
keeping the local energy function and the classification algorithm identical for most approaches.
For reference, comparisons with two classical non filtering approaches, co-occurrence
(statistical) and autoregressive (model based) features, are given. A ranking of the tested
approaches based on extensive experiments is presented in the paper.
S. E. Grigorescu et al. [17] considered various filter based texture feature extraction
operators, which comprise linear filtering, eventually followed by post-processing. The filters
used are Laws masks, filters derived from well-known discrete transforms and Gabor filters.
The post-processing step comprises non-linear point operations and/or local statistics
computation like mean and standard deviation. The performance is measured by means of the
Mahalanobis distance between clusters of feature vectors derived from different textures. The
results show that post-processing improves considerably the performance of filter based texture
operators. With a given type of post-processing the different filtering schemes lead to different
results. With an average Mahalanobis distance, all sinusoidal transforms and the Laws filter
bank give comparable results. Still, they are worse than those obtained with Gabor filters. All of
the sinusoidal transforms results in filters with a rectangular power spectrum with only two
possible orientations, while Gabor filters have an elliptical power spectrum with eight possible
orientations. Taking in consideration that the test material contains oriented textures only, it
seems plausible to explain the good results obtained with Gabor filters by their orientation
selectivity. The paper, thus, claims that the Gabor filters perform best among all linear filters for
feature extraction and some sort of post-processing necessarily improves the performance.
Phillipe P.Ohanian et al [18] compared textural features for pattern recognition. The
problem addressed is to determine which features optimize classification rate. Such feature may
be used in image segmentation, compression, inspection and other problems in Computer vision.
The goal is comparing and evaluating in quantitative manner the four types of features, namely
Markov random field parameters, Multi-channel filtering features, fractal based features and co11

occurrence features. Performance is assessed by the criterion of classification error rate with a
nearest neighbor classifier and the leave-one-out estimation method using forward selection.
Four types of textures are studied, two synthetic and two natural. The results show that the Cooccurrence features perform the best followed by fractal features. However, there is no
universally best subset of features. The paper, thus, deals with the performance evaluation of
four different types of feature extractors for texture classification.
Guoliang Fan et al. [19] produced experimentation on wavelet-based texture analysis and
synthesis using hidden Markov models (HMMs) and developed particularly, a new HMM, called
HMT-3S, for statistical texture characterization in the wavelet-domain. Wavelet-domain HMMs,
in particular hidden Markov tree (HMT), were recently proposed and applied to image
processing, where it was usually assumed that three sub-bands of the 2-D discrete wavelet
transform (DWT), i.e. HL, LH, and HH, are independent. The basic idea of the HMT-3S is that a
more complete statistical characterization of DWT can be implemented by more sophisticated
graph structures for Bayesian inference in the wavelet-domain. They have shown that, in
addition to the joint statistics captured by HMT, the new HMT-3S can also exploit the crosscorrelation across DWT sub-bands. The proposed HMT-3S is applied to texture analysis,
including classification and segmentation, and texture synthesis with improved performance over
HMT. Specifically, for texture classification, they studied four wavelet-based methods, and
experimental results show that HMT-3S provides the highest percentage of correct classification
of over 95% upon a set of 55 Brodatz textures. For texture segmentation, they demonstrated that
more accurate texture characterization from HMT-3S allows the significant improvements in
terms of both classification accuracy and boundary localization. For texture synthesis, they have,
in general, proved that wavelet domain statistical image modeling plays an important role in
texture characterization. The article, thus, focuses on the development of new model, the HMT3S, for describing textures for the synthesis and classification process.
Wei Benjie et al. [20], proposed a novel 32 bit processor whose structure is simple and
efficient for image processing. The specially designed CPU can be embedded into video encoder
or other multimedia processor, and work well, it can also be used to do DWT (digital wavelet
transform) with only few instructions. The paper claims that compared with the fixed ASIC
mode of image coding; the reconfigurable CPU circuit adopted is more flexible and has low cost.

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This paper puts forward a new image processor based on customed RISC CPU, then gives the
RTL design scheme described in VHDL for wavelet transform, which gets rid of the drawbacks
of ASIC. The suggestion for critical module in the design is given, and the advantages of
programmable CPU are also discussed. Refer to the RISC CPU architecture of MIPS, they study
on the whole structure of customed image processor, including work flow and implementation of
the circuit design, at last make experiments to verify it. Noticeably, the CPU proposed in this
paper is not only used for DWT, but also can be embedded into the image encoder as a
reconfigurable IP core for arithmetic coding or other purpose. The simulation results show that
the hardware model of the CPU is effective and practical.
Klaus Illgner [21] presented an overview of DSP architectures and their advantages for
embedded applications. The specific signal processing demands of image and video processing
algorithms in these applications and their mapping to DSPs are described. Recent results of
successful implementation of two major embedded image and video applications, digital still
cameras and video phones, on TI's TMS320C54x DSP series conclude the paper. This paper
analyses first basic processor architectures enabling imaging in portable and embedded devices,
Realizing such, mainly consumer market, applications is not only constraint by the integration
density of computational power, but cost and power consumption are equally important.
Therefore, catalogue DSPs and DSP-based systems sustain and even gain market shares against
specialized processor concepts involving a general purpose processor core (GPP) with
accelerator units. Reduced time-to-market combined with the ease to add features favors
programmable solutions over dedicated chip designs (ASICs). This paper aims in giving an
insight into how DSPs can be used for certain imaging applications and video processing. After
discussing todays platform concepts and why DSPs are especially well suited, the fundamental
operations of imaging applications are analyzed. Paper also discusses the feasibility and
implementation issues of image processing algorithms on DSPs. Finally, two examples of
implementing imaging systems on DSPs are introduced, a digital still camera and a video
communications codec.
J.A. Kalomiros, J. Lygouras [22] evaluated the performance of a hardware/software
architecture designed to perform a wide range of fast image processing tasks.The system
architecture is based on hardware featuring a Field Programmable Gate Array (FPGA) co-

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processor and a host computer. ALabVIEW host application controlling a frame grabber and an
industrial camera is used to capture and exchange video data with thehardware co-processor via a
high speed USB2.0 channel, implemented with a standard macrocell. The FPGA accelerator is
based on aAltera Cyclone II chip and is designed as a system-on-a-programmable-chip (SOPC)
with the help of an embedded Nios II software processor.The SOPC system integrates the CPU,
external and on chip memory, the communication channel and typical image filters
appropriatefor the evaluation of the system performance. Measured transfer rates over the
communication channel and processing times for the implemented hardware/software logic are
presented for various frame sizes.They also claimed that Partitioning a machine vision
application between a host computer and a hardware co-processor may solve a number of
problems and can be appealing in an academic or industrial environment where compactness and
portability of the system is not of primal importance.
D. Karatzas, A. Antonacopuos [23] argues that the challenging segmentation stage for
such images benefits from a human perspective of colour perception in preference to RGB colour
space analysis. The proposed approach enables the segmentation of text in complex situations
such as in the presence of varying colour and texture (characters and background). More
precisely, characters are segmented as distinct regions with separate chromaticity and/or
lightness by performing a layer decomposition of the image. The method described here is a
result of the authors systematic approach to approximate the human colour perception
characteristics for the identification of character regions. In this instance, the image is
decomposed by performing histogram analysis of Hue and Lightness in the HLS colour space
and merging using information on human discrimination of wavelength and luminance.
Zoltan Kato, Ting Chuen Pong[24] proposed a Markov random field (MRF) image segmentation
model, which aims at combining color and texture features. The theoretical framework relies on
Bayesian estimation via combinatorial optimization (simulated annealing). The segmentation is
obtained by classifying the pixels into different pixel classes. These classes are represented by
multi-variate Gaussian distributions. Thus, the only hypothesis about the nature of the features is
that an additive Gaussian noise model is suitable to describe the feature distribution belonging to
a given class. Here, we use the perceptually uniform CIE-L*u*v* color values as color features
and a set of Gabor filters as texture features. Gaussian parameters are either computed using a
training data set or estimated from the input image. We also propose a parameter estimation
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method using the EM algorithm. Experimental results are provided to illustrate the performance
of our method on both synthetic and natural color images.
Jue Wu, Albert C. S. Chung [25] proposed a non texture segmentation model using
compound MRFs based on a boundary model. The main target of this approach is to enhance the
performance of segmentation by emphasizing the interactions between label and boundary
MRFs. The comparisons with other existing MRF models show that the proposed model can give
more accurate segmentation results in both high and low noise level regions while preserving
subtle boundary information with high accuracy.

Michal Haindl, Stanislav Mike [26] proposed novel efficient and robust method for unsupervised
texture segmentation with unknown number of classes based on the underlying CAR and GM
texture models. Although the algorithm uses the random field type model it is relatively fast
because it uses efficient recursive parameter estimation of the model and therefore is much faster
than the usual Markov chain Monte Carlo estimation approach. Usual handicap of segmentation
methods is their lot of application dependent parameters to be experimentally estimated. Our
method requires only a contextual neighborhood selection and two additional thresholds. The
algorithms performance is demonstrated on the extensive benchmark tests on natural texture
mosaics. It performs favorably compared with four alternative segmentation algorithms.
Daniel Baumgartner et. al [27] In this work a performance benchmark of several DSP and
FPGA implementation of some low-level image processing algorithms was presented. Three
algorithms a Gaussian pyramid, a Bayer filter and a Sobel filter were implemented on both a
high-end DSP and on high-end FPGAs.

Summary of literature survey

The articles reviewed in literature survey can be classified broadly into two categories.

Algorithms for texture description, representation and modeling, to be applied in generic

sense to feature extraction process, for texture classification using the extracted features,
namely, Markov random field model, co-occurrence matrix descriptors, sum and
difference histogram descriptor, discrete wavelet transforms, Gabor function descriptors
etc. as applied in space and spatial frequency (transform) domains, with design details,

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optimality of choice, implementation details, necessity of post processing, variety of

input textures etc. detailed for each approach.

Selecting algorithms for hardware implementation of texture classification is challenging

task because of the constraints like sequential processing architecture of existing
processors, memory size etc.

It is obvious from the summary that, by and large, Multi-channel Gabor filters, Co-occurrence
matrix, and Wavelet transforms have been largely deployed by the researchers as feature
extractors for texture classification. Wavelet transforms are comparatively efficient and less time
consuming. It is suggested to implement Wavelet based techniques on hardware platform like
DSP and PLD.

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