Microelectronics Journal 46 (2015) 698705

Contents lists available at ScienceDirect

Microelectronics Journal
journal homepage: www.elsevier.com/locate/mejo

A broadband Low Noise Amplier with built-in linearizer in 0.13-mm

CMOS process
Habib Rastegar 1, Jee-Youl Ryu
Pukyong National University (PKNU), Department of Information and Communications Engineering, Republic of Korea

art ic l e i nf o

a b s t r a c t

Article history:
Received 20 April 2014
Received in revised form
23 February 2015
Accepted 15 May 2015

A linearized ultra-wideband (UWB) CMOS Low Noise Amplier (LNA) is presented in this paper. The
linearity performance is enhanced by exploiting PMOSNMOS common-gate (CG) inverter as a built-in
linearizer which leads to cancel out both the second- and third-order distortions. Two inductors are
placed at the drain terminals of CG transistors in the built-in linearizer to adjust the phase and
magnitude of the third-order distortion. A second-order band-pass Chebyshev lter is utilized in the
input port of common-source (CS) conguration to provide broadband input matching at 3.110.6 GHz
frequency range to a 50- antenna. Series and shunt peaking techniques are employed to extend the
bandwidth (BW) and to atten the gain response. Simulated in 0.13 mm CMOS technology, the CMOS LNA
exhibits state of the art performance consuming 17.92 mW of dc power. The CMOS LNA features a
maximum gain of 10.24 dB, 0.94.1 dB noise gure (NF), and a third-order input intercept point (IIP3) of
6.8 dBm at 6.3 GHz.
& 2015 Elsevier Ltd. All rights reserved.

Keywords:
Low Noise Amplier (LNA)
CMOS
High linearity
Chebyshev lter
Inverter

1. Introduction
The increasing demand for wireless communication has
resulted in many communication standards. In the broadband
systems the receiver chain has to be able to minimize/cancel the
adverse effects of large number in-band interferences and intermodulation/cross-modulation caused by transmitter leakage or
blockers. Such interference minimization/cancellation requires
diligent design considerations.
Linearity is the most crucial design specication which plays an
important role in RF systems. Special attention has to be paid to
the linearity performance of the LNA in a wireless transceiver
design. It is noteworthy to mention that the enhancement in
linearity performance should not compromise the desired power/
voltage gain or noise gure performance. Various LNA topologies
are reported using different techniques to achieve high linearity.
For instance [1] employed optimum biasing (OB) technique to null
the main source of nonlinearity (i.e., third-order derivation of
transconductance (g m
'' )) in common-source (CS) without any
additional device and used device bias at point which its IIP3 is
maximum. The main bottleneck of OB technique is that the
transistor must be biased at sweet point; thus, limiting the
transconductance which leads to reduced gain and increased NF.

E-mail addresses: hrastegar@pknu.ac.kr (H. Rastegar),

ryujy@pknu.ac.kr (J.-Y. Ryu).
1
Tel.: 82 51 629 6289; fax: 82 51 629 6229.
http://dx.doi.org/10.1016/j.mejo.2015.05.006
0026-2692/& 2015 Elsevier Ltd. All rights reserved.

Feed-forward technique is based on splitting the input into two

signals amplied by two ampliers with different transfer characteristics such that, upon combining their output signals, their
distortions cancel the other one.
In [2], feedforward technique was exploited in differential pair
transistors to improve IIP3 performance. This technique led to
obtain high linearity, but consumed much power consumption
and also degraded the gain and hence, NF. The Derivative Superposition (DS) technique is a special case of the feedforward
technique [312]. DS method consists of two parallel transistors.
Main transistor works in the strong inversion region and the
auxiliary transistor works in the weak inversion region. In DS
method, by tuning the sizes and bias conditions of the transistors,
gm
'' can be minimized or even canceled. The drawback of this
technique is that it is not able to eliminate the second-order
nonlinearity coefcient (g m
' ) which degrades the IIP3. In DS
technique the auxiliary transistor which is biased in the weak
inversion region connected to the main transistor and hence,
degrades the input matching (due to parasitic capacitances) and
NF (due to the gate-induced noise) of whole LNA. To overcome
these shortcomings, the modied DS (MDS) was proposed in [13
15]. Additionally, MDS method can eliminate the g m
' in order to
achieve high linearity.
In Post-Distortion (PD) method [1620], not only the auxiliary
transistor does not connect directly to the input of the main
device, but also connects to the output of the main transistor
which minimizes the degradation on the noise gure and input
impedance matching.

H. Rastegar, J.-Y. Ryu / Microelectronics Journal 46 (2015) 698705

2. Broadband input matching network

Z 1 Z 2 T Ls
Z 1 Z 2 T Ls

S11 (dB)

-10
Without Cex
Ct=0.15 pF
Ct=0.3pF

-15

-20
0

10

12

14

Frequency (GHz)

-5

-10

W1=75um
W1=82.5um
W1=90um

-20
0

10

12

14

Frequency (GHz)
Fig. 2. Input return loss for two conditions: (a) variable Ct with constant W1
(b) variable W1 with constant Ct.


where Z 1 sL1 j j sC11 ; Z 2 s Lg Ls sC1 t ; C t C gs C ex ; T gCmt
The Ls results in a real resistive value equals to gmLs/Ct to match
the source impedance to 50 (Rs 50 ).
The parasitic capacitances Cgs1 and Cex must follow the required
component value in the lter design and the size of the transistor
M1 must be selected carefully. It may be necessary to adjust the
lter corner frequency and choose a reasonable size in order to
meet all the specications. Fig. 2 shows the simulated input return
loss (S11) of the proposed LNA for two conditions: (a) variable Ct
with constant W1 (b) variable W1 with constant Ct. As expected,
the S11 improves by inserting external capacitance (Cex) in parallel
with gatesource capacitance (shown in Fig. 2(a)). This is due to
the fact that the Cex along with other parasitic capacitances
resonate with inductors in the input port to generate the real part
of the input impedance (Zin). On the other hand, as shown in Fig. 2
(b) the S11 degrades as W1 increases, because of non-zero imaginary part of Zin. In conclusion, there is a sever tradeoffs among S11,
noise gure (NF) and gain of LNA about existence of Cex that will
be discussed in the next sections.

Fig. 1. Small-signal model of the input port of LNA.

-5

-15

The lter design technique is employed for input impedance

matching. The lter actually makes use of the parasitic gate
source capacitance (Cgs). The small-signal model of the input
matching network is shown in Fig. 1.
The Ccoupling is used as a coupling capacitor. The values of
second-order Chebyshev lter elements are chosen to set the
corner frequencies in 3.1 GHz and 10.6 GHz. The combination of
M1 input parasitic capacitance (Cgs), external capacitance (Cex),
source degeneration inductor (Ls), series-gate inductor (Lg), L1 and
C1 form second-order Chebyshev ltering structure that can
achieve a wideband input matching. The input impedance can be
shown as follows:
Z in

S11 (dB)

In this paper, a second-order Chebyshev lter is employed in

the input common-source transistor to achieve wideband BW for
UWB applications. We propose a PMOSNMOS CG inverter to
minimize/cancel both the second- and third-order distortions,
simultaneously. Two inductors are also inserted in the drain of
CG transistors in the built-in linearizer to tune the magnitude and
phase of g m
'' in order to achieve high linearity. Shunt and series
techniques are utilized to extend the BW, increase the gain
response, and reduce the NF.
This paper is organized as follows. In Section 2, input impedance matching network will be described. Linearity analysis
will be presented in Section 3. In Section 4, the proposed circuit
and design considerations are presented and the simulation
results and a comparison with other published works are shown.
Section 5, summarizes and concludes this work.

699

Fig. 3. The Derivative Superposition circuit [11].

3. Linearity analysis
3.1. Linearity fundamentals and Derivative Superposition (DS)
technique drawbacks
The non-linearity of a MOSFET transistor arises from its
voltage-to-current (VI) conversion [13]:
iDS I dc g m1 vgs g m2 v2gs g m3 v3gs

where gm1 is the main transconductance of the MOSFET, gm2 is the

second-order non-linear coefcient obtained by the second-order
derivative of the DC transfer characteristic, and gm3 is the thirdorder non-linear coefcient obtained by the third-order derivative
of the DC transfer characteristic.
To determine IIP3 at low level signal, gm3 is the dominant
coefcient. The IIP3 of a non-linear device gives as follows:
s
4 g m1
j
IIP3
j
3
3 g m3
The DS method (shown in Fig. 3) nulls the negative third-order
derivative of the main eld-effect transistor's (FET's) dc transfer
characteristic (gm3) by paralleling the auxiliary FET biased near the
weak inversion region with the positive gm3 [14]. The DS method

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H. Rastegar, J.-Y. Ryu / Microelectronics Journal 46 (2015) 698705

0.012
0.01
0.008

gm1n
gm1p

0.006
0.004
0.002
0
0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

0.04
gm2n
gm2p

0.03

0.02

0.01

0
0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

0.5
gm3p
gm3n

0.4
0.3

Fig. 5. The proposed LNA circuit with built-in linearizer (bias circuit not shown).

0.2
0.1
0
-0.1
-0.2
0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

VGS(V)
Fig. 4. (a) Simulated gm1n and gm1p. (b) Simulated gm2n and gm2p. (c) Simulated
gm3n and gm3p.

has the following drawbacks. First, it is valid only at low frequencies at which the effect of circuit reactance is negligible [15].
Second, to obtain linearity in DS method, one transistor is biased
in weak inversion region so this transistor degrades noise gure of
the LNA due to its high gate induced current noise getting added to
the input [16]. Third, the auxiliary transistor which is biased in the
weak inversion region adds extra capacitance to the input node
and changes the input matching of the whole LNA. The secondorder non-linearity (gm2) (is generated through gatesource and
gatedrain capacitances) get mixed with fundamental components and hence, degrades linearity performance and less
improvement is obtained. To overcome these drawbacks, we
propose a CG PMOSNMOS inverter for the cascode LNA as a
built-in linearizer. The proposed linearization technique adopts
PMOS and NMOS transistors in common-gate conguration to
cancel out the second- and third-order nonlinearity simultaneously in order to enhance the linearity performance.
3.2. Theoretical concept of the proposed linearization technique
In this section, the proposed built-in linearizer structure and its
operating principle are presented. The analytical of the proposed
LNA with linearity enhancement will be elaboratively presented in
the next section. To achieve very low third-order distortion, it is
essential to consider both the second- and third-order nonlinearities. Therefore, our analysis is concentrated on cancelation/minimization of gm2 and gm3 in order to increase IIP3 or to
reduce the third-order intermodulation distortion (IMD3). The
inductors (LN and LP) and the parasitic capacitances at the drain
of MN, MP and M2 form a broadband network. Proper choice of

Fig. 6. Conceptual view of the proposed linearization technique.

inductor sizes leads to cancel the capacitive effects, yielding

effectively a short circuit over the whole BW. Under this condition,
non-linearity from M2 can be neglected. As shown in Fig. 5 the
non-linearity drain current of M1 moves toward the MN and MP
transistors which are utilized as CG conguration and hence,
operate as a current buffer. The main responsibility of built-in
linearizer stage (MN and MP) is to absorb the non-linearity of M1
drain current. Thus, the fundamental current component of M1 can
be delivered to output port. Fig. 6 illustrates the conceptual idea of
the linearization technique. Fig. 6 depicts that the drain current of
M1 (id1) can be expressed as the sum of the drain current of MN
(id,N) and MP (id,P) as follows:
id;N g m1;N vgs;N g m2;N v2gs;N g m3;N v3gs;N

id;P g m1;P  vgs;P g m2;P  vgs;P 2 g m3;P  vgs;P 3



id1 v1 id;N id;P g m1;N vgs;N g m2;N v2gs;N g m3;N v3gs;N


 g m1;P  vgs;P g m2;P vgs;P 2 g m3;P  vgs;P 3

H. Rastegar, J.-Y. Ryu / Microelectronics Journal 46 (2015) 698705

where cis are in general frequency dependent. In practice, the network cancels the effects of c2 and c3 at the frequency of interest
[21].
To nd the coefcient cis, we should solve the equation after
expanding id1 as a power series of vgs,P and replacing it with (7). By
using power series and replacing (7) in (6), the drain current id1
can be re-expressed as function of vgs,N as follows:






id1 id;N id;P gm1;N c1 g m1;P vN gm2;N  c21 g m2;P v2N gm3;N c31 g m3;P v3N

8
The gm3,N changes from positive to negative when the transistor moves from weak to strong inversion region. In other words, by
changing gate-bias voltage of PMOS transistor, the parameter c1
can be varied. It can be deduced from (8) that c1 has a positive
value from the bias circuit theory. As shown in Fig. 4(b) and (c), by
adjusting the gate-bias voltages and widths of main and auxiliary
transistors, both the gm2 and gm3 can be closed to zero and hence,
the IIP3 can be enhanced.
3.3. High frequency analysis of PMOSNMOS common-gate inverter
with Volterra series
The circuit of the built-in linearizer for high frequency distortion analysis is shown in Fig. 14 ( see Appendix A). The parasitic
capacitance associated with the drain of M1 and M2 are not
modeled here, because they are absorbed by the LC network.
We also neglect distortion due to nonlinear ro, because the passive
load resistance is much smaller than the transistor output resistance. The analysis is limited up to third order, assuming a weakly
nonlinear circuit (Appendix A).
The fundamental and third-order distortion of the output
voltage (Vo) can be expressed as follows:



9
V o;fund A1 so V s g m1;N B1 so V s g m1;P  Z L
V o;thirdorder







A1 s1 ; s2 ; s3 V 3s g m1;N B1 s1 ; s2 ; s3 oV 3s g m1;P


A1 s1 A2 s2 ; s3 oV 3s g m2;N


B1 s1 B2 s2 ; s3 oV 3s g m2;P  Z L
10

where ZL is the impedance that can be seen from the source

terminal of M2 transistor and acts as load for built-in
linearizer block.
The rst term in (10) is due to MP's and MN's third-order
distortions and cancels out by adjusting the phase and magnitude
of the third-order of non-linearity coefcients (gm3,N and gm3,P) as
shown in Eq. (A.22) by varying the bias voltage and sizes of PMOS
and NMOS transistors in built-in linearizer. The second term is
due to second-order interaction which mixes the rst- and
second-order voltages at VN and VP by gm2,N and gm2,P. Based on
Eqs. (A. 17), (A. 18) and (10), if gm2,N and gm2,P have the same
magnitude and phase, the second-order interaction can be
reduced or canceled. The linearity enhancement will be proved
by the simulation results in the next section.

4. Results and discussions of UWB-LNA

The whole schematic of the proposed LNA is illustrated in Fig. 5
which consists of two CG transistors to achieve high linearity and a
CS transistor with second-order Chebyshev lter to achieve wideband input matching with at power gain and low NF. Since the

5.1
5.05
IIP3 (dBm)

vgs;P c1 vgs;N c2 v2gs;N c3 v3gs;N

proposed LNA aimed for wideband applications, a second-order

Chebyshev lter is located in the input port of CS conguration to
achieve wideband input impedance matching. The components of
lter section are selected to resonate with parasitic capacitance of
M1 at 3 GHz to provide desired input return loss.
A built-in linearizer is placed at the second stage to eliminate
the distortions of M1 drain current and hence the current with
fundamental components ow toward the output stage. The builtin linearizer incorporates NMOS (MN) and PMOS (MP) transistors
in CG conguration in order to realize the minimization/cancelation of second- and third-order nonlinearities. By stacking MN on
the top of MP, the DC current is reused and hence, the power
consumption also can be saved. An AC capacitance (CNP) is utilized
to connect the drain of MP and MN. At high frequency (RF), CNP is
shorted out and connects the two drain nodes. For much low RF
frequencies, CNP breaks due to its high impedance and separated
the drain nodes. In Fig. 7(a), the variation of IIP3 is examined
versus different values of CNP capacitance. The result shows that
the IIP3 variation is only 0.25 dBm which is very small and can be
deduced that the built-in linearizer is robust against variations of
CNP. Two inductors are inserted in the drain nodes of main (LN) and
auxiliary (LP) to adjust the phase and magnitude of the third-order
nonlinearity coefcient. The effect of LN on the IIP3 characteristic is
carried out in Fig. 7(b). As result shows the simulation is done for
three distinct inductor values which the 0.32 nH is the best one for
highest value of IIP3.
Since CG conguration is linear than CS; thus, built-in linearizer is formed in CG conguration. The third stage is also used in
CG topology to act as a buffer and does not degrade the linearity
and BW.
The inductor Lx is placed as a load for rst stage for two
reasons. First, larger Lx is required to minimize NF and maximize
gain response in the rst stage output. Second, smaller Lx is
needed in order not to degrade IIP3. In short, this inductor should
be chosen to satisfy a good tradeoff among gain, noise gure and
linearity. The following results illustrate the inuence of Lx on the
gain, NF and IIP3. As shown in Fig. 8(a), by increasing the Lx, gain
response of the proposed conguration boosts and simultaneously
the NF response reduces. Meanwhile, large Lx degrades the IIP3

5
4.95
4.9
4.85
3

3.5

4.5

5.5

CNP (pF)

20
0
Pout (dBm)

Since vgs,P is a function of vgs,N, it can be expanded into power

series of vgs,N as follows:

701

-20
-40
-60
-80
-100
-30

-25

-20

-15

-10

-5

10

15

20

25

30

Pin (dBm)
Fig. 7. IIP3 characteristic with respect to variation of (a) capacitor CNP and
(b) inductor LN.

702

H. Rastegar, J.-Y. Ryu / Microelectronics Journal 46 (2015) 698705

NF (dB) / Gain (dB)

10
8
NF (dB)

6
4

2
0
0

10

12

Without Cex
Ct=0.15 pF
Cex=0.3 pF

14

10

12

14

Frequency (GHz)

20

15

10
5

-20

Gain (dB)

Pout (dBm)

Frequency (GHz)

-40

Without Cex
Ct=0.15 pF
Ct=0.3 pF

0
-5
-10

-60

-15

-80
-30

-20

-10

0
Pin (dBm)

10

20

-20

30

10

12

14

Frequency (GHz)

Fig. 8. Effect of Lx variation on the (a) gain and noise gure (NF) and (b) IIP3.

Fig. 10. Effect of Ct on the (a) noise gure (NF) and (b) gain.
15

12
10

5
-10

S22 (dB)
Gain (dB)
IIP3 (dBm)

Sxx (dB)

Desired area

-2
-6

S21(dB)
S11(dB)
S22(dB)
S12(dB)

-25
-40
-55

-10

-70
0

20

22

24

26

28

30

32

34

36

38

40

10

12

14

12

14

Frequency (GHz)

RL (Ohm)

Fig. 11. Two-port S-parameters of the LNA.

Fig. 9. Gain, output return loss and IIP3 characteristics with varying RL.

6
5
NF (dB)

performance (see Fig. 8(b)). Therefore, Lx is set to be 0.5 nH to

minimize noise and to meet the at gain, high IIP2 and IIP3.
Due to the intrinsic high linearity of this LNA, adding a
Common-Drain (CD) output buffer for good output return loss
would degrade the linearity performance. Therefore, resistor RL
was sized close to 30- and series LC tank (LL and CL) is adopted to
achieve reasonable output return loss. Because of the low value of
RL, simulation shows negligible IIP3 difference when the output is
checked as it is without 30- resistance. Fig. 9 shows the effect of
RL variation on the IIP3, S22 and gain response. As implied from
Fig. 9, the RL should be chosen in the marked area (28 oRL o32) to
satisfy the tradeoffs among IIP3, gain and S22. Furthermore, as
illustrated in Fig. 9, the gain response of the proposed LNA is
identical over the variation of RL and we can deduce that the
selected load resistance is only designed to achieve acceptable
output return loss for ultra-wideband frequency. Although, the
variation of IIP3 over entire RL is 11 dBm, but its variation in the
marked zone is approximately zero. Therefore, this indicates that
over the dashed area in Fig. 9, the IIP3 is robust against load
resistance variations.
Ultimately, the effect of parasitic and external capacitances
(Cex) is examined on the NF and gain responses. It should be noted
that Ct Cex Cgs. Although, adding Cex causes to increase NF
(Fig. 10(a)) and reduces gain from 2 GHz to 8 GHz (Fig. 10(b)),
but these deteriorations are very small and thus, can be neglected
in comparison with the improvement of input return loss (see

4
3
2
1
0

10

Frequency (GHz)
Fig. 12. Noise gure (NF) performance of the LNA.

Fig. 2(a)). Therefore, the Cex should be chosen 0.3 pF in order to

satisfy the tradeoffs between gain, noise gure (NF) and input
return loss.
The simulation results of the proposed LNA are shown in
Fig. 11. As can be seen, the well-matched input reection coefcient (S11), below  8 dB at the designed frequency band, demonstrates a successful design of band pass lter as the input matching
network. As shown in Fig. 11, a at power gain response with
maximum 10.24 dB from 3.1 to 10.6 GHz can be achieved. The at
power gain response is due to the series and shunt peaking
inductor techniques. Fig. 12 depicts that the proposed design
features a NF of 0.94.1 dB after linearization in the 3-dB

H. Rastegar, J.-Y. Ryu / Microelectronics Journal 46 (2015) 698705

703

20

Pout (dBm)

1st order
3rd order

-20
-40
-60
-80
-30

-20

-10

0
Pin (dBm)

10

20

30

Fig. 13. IIP3 characteristic of the LNA.

Fig. 14. Built-in linearizer circuit for high frequency Volterra series analysis.
Table 1
Comparison of the simulation results of the proposed LNA and other
published works.
Ref.

[10]

[11]

[16]

[21]

This work

Tech (mm)
Freq (GHz)
S21 (dB)
S12 (dB)
NF (dB)
Power (mW)
IIP3 (dBm)

0.18
0.9
15
NA
1.76
6.75
12.45

0.13
3.110.6
19.5 7 1.5
o  70.6
13.9
4.1
4.56

0.13
3.66
14
o  53.5
2
2.43
10.5

0.18
310
14.515.3
NA
NA
4.3
3.43

0.13
3.110.6
10.24
o  31.7
0.94.1
17.92
6.8

bandwidth range. The stability factor (K) of the proposed LNA is

more than 4.6 and resulting in an unconditional stable amplier.
The designed LNA power consumption is 17.92 mW from a 1.4 V
voltage supply. The built-in linearizer is robust versus the variations in the bias voltage of the common-gate transistors. It is
worthy mentioned that the maximum IIP3 is 6.8 dBm at 6.3 GHz
and is depicted in Fig. 13. In the end, the performance summary of
the proposed LNA and comparison with other high-linear LNAs are
shown in Table 1.

performance of the proposed LNA. The drain current of the CG

transistors shown in Fig. 14 can be expressed as the following
Volterra series:
V C A1 s1 V s A2 s1 ; s2 V s 2 A3 s1 ; s2 ; s3 V s 3

A:1

V N B1 s1 V s B2 s1 ; s2 V s 2 B3 s1 ; s2 ; s3 V s 3

A:2

V P C 1 s1 V s C 2 s1 ; s2 V s 2 C 3 s1 ; s2 ; s3 V s 3

A:3

By applying KCL at VN, VP, and VC nodes, the equations are

established as follows:
idN idp
idN

VC VN VC VP VC VS

VC

r O;N
r O;P
Z S s
Z C s

VN VC VN VP VN

r O;N
Z NP s Z L s

 idP

VP VC VP VN
VP

r O;P
Z NP s Z P s

where Z L 

5. Conclusion
A highly linearized UWB LNA has been proposed. A secondorder Chebyshev lter is utilized to achieve wideband input
matching as well as good input return loss. At the second stage,
a built-in linearizer which consists of two PMOS and NMOS
common-gate transistors is exploited to absorb both second- and
third-order non-linear currents of LNA over wide frequency range.
The proposed built-in linearizer stage used two inductors in the
drain terminals of common-gate transistors to adjust magnitude
and phase of the third-order non-linearity coefcient. A commongate transistor with shunt peaking inductor technique is utilized
as the third stage to extend the bandwidth, atten and improve
the power gain response in the band of interest. Due to wide
bandwidth and high linearity, the proposed LNA is a good
candidate for high-linearity UWB applications.

1 gm;M2
Z s r O 1 L2 Z s'
Z s' 

This work was supported by the Basic Research of NRF, Korea

(2010-0021768, Development of Dual-Band 24GHz/77GHz CMOS
System-on-Chip for Advanced Safety Vehicle Radar).

A:5
A:6

r O;M2 sLL RL
LN
rO;M2 sC gs;M2 r O;M2 RL s2 cgs;M2 LL

1
1
1

sL2 J
sL1
sC gs;M1 C ex sC 1
sC 1

Z P  LP J 1=sC p and Cp is the parasitic capacitances at source of the

PMOS transistor.
Z c s  1=sC c and Cc is the parasitic capacitances at node VC.
where id,N and id,P are the small-signal currents moving into the
common-gate transistor sources.


idN  g m1;N  V C gm2;N  V C 2 gm3;N  V C 3 g m1;N V C  g m2;N V C 2 gm3;N V C 3

A:7
idP g m1;P V C g m2;P V 2C g m3;P V 3C

Acknowledgement

A:4

A:8

The rst-order Volterra kernel can be derived by substituting id,

and id,P with their gm polynomial.

g m1;N A1 s g m1;P A1 s

A1 s  B1 s A1 s  C 1 s A1 s  1 A1 s

r O;N
r O;P
Z S s
Z C s

A:9
g m1;N A1 s

B1 s  A1 s B1 s  C 1 s B1 s

r O;N
Z NP s
Z L s
C 1 s  A1 s C 1 s  B1 s C 1 s

r O;P
Z NP s
Z P s

A:10
A:11

Appendix A

 g m1;P A1 s

In this section, we plan to nd the kernels of Volterra series of

built-in linearizer circuit in order to explain the linearity

At high frequency (band of interest, i.e. 3.110.6 GHz), the

impedance of ZNP(s) which includes capacitance CNP is negligible;

704

H. Rastegar, J.-Y. Ryu / Microelectronics Journal 46 (2015) 698705

thus we can say that B1(s) C1(s). By utilizing the abovementioned assumption and after complex calculation, the precise
A1 and B1 results are as follows:



Z L s J Z P s r O;N J r O;P
A:12
A1 s
Ks
where








Z s s
K s Z s s 1 g m;N g m;P r O;N J r O;P Z L s J Z P s rO;N J r O;P  1

Z C s

Z L s J Z P s

B1 s 

A1 s

A:13

Z L s J Z P s r O;N J rO;P
1 gm;N gm;P rO;N J rO;P

At the second step, we want to nd the second-order Volterra

Series Kernels as following procedure:
g m1;N A2 s1 ; s2  g m2;N A1 s1 A1 s2 g m1;P A2 s1 ; s2
g m2;P A1 s1 A1 s2

A2 s1 ; s2  B2 s1 ; s2 A2 s1 ; s2  C 2 s1 ; s2

r O;N
r O;P

A2 s1 ; s2  0 A2 s1 ; s2

0
Z S s1 s2
Z C s1 s2

A:14

B2 s1 ; s2  C 2 s1 ; s2
Z NP s1 s2
B2 s1 ; s2  A2 s1 ; s2
B2 s1 ; s2

r O;N
Z L s1 s2

A:15

C 2 s1 ; s2 B2 s1 ; s2
Z NP s1 s2
C 2 s1 ; s2  A2 s1 ; s2
C s1 ; s2
0
A:16

r O;P
Z P s1 s2

g m1;P A2 s1 ; s2  g m2;P A1 s1 A1 s2

By the assumption that ZNP(s1 s2) is negligible at the frequency band we nd the following results:




1=2 g m2;N  g m2;P r O;N J r O;P Z S s1 s2 A1 s1 A1 s2 A2 s1 ; s2
K s1 s2 K s1 ; s2

A:17

B2 s1 ; s2

1
 ZZLc s
s1

s2 J Z P s1 s2
s2 J Z s s1 s2 1=2

g m2;N  g m2;P



B2 s1 ; s2  1=2Z 12 s1 s2 A1 s1 A1 s2
Z L s1 s2

Z L s1 s2 Z P s1 s2 r O;N r O;P



Z s s1 s2

 g m2;N r O;N Z P s1 s2 r O;P 1

Z C s1 s2



Z s s1 s2 g m2;P r O;P 1 g m1;N r O;N g m2;N r O;N 1 g m1;P r O;P
It is noteworthy to mention that if we apply the assumption
(ZNP(s1 s2) is zero at high frequency) to equations (A. 17) and (A.
18), then B2 (s1, s2), A2 (s1, s2) and K (s1, s2) parameters have
negligible value and hence, drop out. Due to the circuit duality, the
C2 (s1,s2) can be found by interchanging the element notation in B2
(s1,s2). By the above explanation and precise observation into Eq.
(A. 18), we can understand that if gm2,N and gm2,P have the same
magnitude and phase, the second-order non-linearity of the circuit
can be canceled.
Finally, the third-order Volterra Series Kernels can be found as
follows:
g m1;N A3 s1 ; s2 ; s3  g m2;N A1 s1 A2 s2 ; s3
g m3;N A1 s1 A1 s2 A1 s3 g m1;P A3 s1 ; s2 ; s3
g m2;P A1 s1 A2 s2 ; s3 g m3;P A1 s1 A1 s2 A1 s3

g m1;N A2 s1 ; s2  g m2;N A1 s1 A1 s2

A2 s1 ; s2

where

A3 s1 ; s2 ; s3  B3 s1 ; s2 ; s3 A3 s1 ; s2 ; s3  C 3 s1 ; s2 ; s3

r O;N
r O;P

A3 s1 ; s2 ; s3
A3 s1 ; s2 ; s3

0
Z s s1 s2 s3 Z c s1 s2 s3

g m1;N A3 s1 ; s2 ; s3  g m2;N A1 s1 A2 s2 ; s3 g m3;N A1 s1 A1 s2 A1 s3

B3 s1 ; s2 ; s3  C 3 s1 ; s2 ; s3 B3 s1 ; s2 ; s3 A3 s1 ; s2 ; s3

Z NP s1 s2 s3
r O;N
B3 s1 ; s2 ; s3
0
A:20

Z L s1 s2 s3
g m1;P A3 s1 ; s2 ; s3 g m2;P A1 s1 A2 s2 ; s3
C 3 s1 ; s2 ; s3  B3 s1 ; s2 ; s3
g m3;P A1 s1 A1 s2 A1 s3
Z NP s1 s2 s3


r O;N J r O;P Z S s1 s2 A1 s1 A1 s2 B2 s1 ; s2

K s1 s2 K s1 ; s2

where
A2 s1 ; s2 1=2Z 12 s1 s2 A1 s1 A1 s2
Z S s1 s2

Z L s1 s2 Z P s1 s2 r O;N r O;P

A3 s1 ; s2 ; s3

C 3 s1 ; s2 ; s3 A3 s1 ; s2 ; s3 C 3 s1 ; s2 ; s3
0

r O;P
Z P s1 s2 s3










 Z s r O;N J r O;P  g m2;N g m2;P A1 s1 A2 s2 ; s3 1=6 g m3;N g m3;P A1 s1 A1 s2 A1 s3
K s1 s2 s3

g m2;N r O;N Z P s1 s2  g m2;P r O;P Z L s1 s2

r O;N r O;P

Z s s1 ; s2
Z 1 s1 ; s2 Z 2 s1 ; s2 r O;N r O;P





r O;N Z L s1 s2 r O;P Z P s1 s2

Z C s 1 s 2 J Z s s 1 s 2










1 g m1;N r O;N r O;P Z P s1 s2 1 g m1;P r O;P r O;P Z L s1 s2

K s1 ; s2 Z NP s1 s2

A:18

A:21

We assume ZNP(s1 s2 s3) 0 at RF frequency and then nd

the A3(s1 s2 s3) and B3(s1 s2 s3) as follows:




 g m2;N  g m2;P r O;N J r O;P

A:19

B3 s1 ; s2 ; s3

 Z L s1 s2 s3
A3 s1 ; s2 ; s3
Z C s1 s2 s3 J Z s s1 s2 s3

A:22

A:23

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