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03 - VCI - and - AMBA
03 - VCI - and - AMBA
Outline
Institute of Electronics, National Chiao Tung University
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Outline
Institute of Electronics, National Chiao Tung University
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What is VCI
A request-response protocol, contents and coding, for
the transfer of requests and responses
Why VCI
Other IP blocks not available wrapped to the on-chip
communications may work with IP wrappers. VCI is the
best choice to start with for an adaptation layer
VCI specifies
Thee levels of protocol, compatible each other
Advanced VCI (AVCI),
Basic VCI (BVCI)
Peripheral VCI (PVCI)
Transaction language
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Star topology
Request
Initiator
Target
Response
Point-to-point usage
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Initiator VC
Target VC
VCI Initiator
VCI Target
VCI Initiator
Initiator
Wrapper
Target
Wrapper
Bus Master
Bus Slave
Any Bus
Split Protocol
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order kept
request tagged with identifiers, allow different order
no split protocol
each request must be followed by a response
before the initiator can issue a new request
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Control Handshake
Synchronous
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Asynchronous
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RESETN
System Signals
VAL
EOP
Handshake
ACK
Initiator
Target
ADDRESS[n-1:0]
BE[b-1:0 | 0:b-1]
Contents
WDATA[8b-1:0]
RERROR[E:0]
RDATA[8b-1:0]
Up to 32-bit Address
Up to 32-bit Read Data
Up to 32-bit Write Data
Synchronous
Allows for 8-bit, 16-bit, and
32-bit devices
8-bit, 16-bit, and 32-bit
Transfers
Simple packet, or burst
transfer
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PVCI Protocol
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Transfer Request
Read8, Read16, Read32, Read N cells
Write8, Write16, Write32, Write N cells
Transfer Response
Not Ready
Transfer Acknowledged
Error
Packet Transfer
The packet (burst) transfer makes is to transfer a block of
cells with consecutive addresses
While the EOP signal is de-asserted during a request, the
address of the next request will be ADDRESS+cell_size
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BVCI Signals
CLOCK
RESETN
System Signals
CMDVAL
CMDACK
Request Handshake
ADDRESS[n-1:0]
BE[b-1:0 | 0:b-1]
CFIXED
CLEN[q-1;0]
Initiator
Request Contents
CMD[1:0]
CONTIG
Target
WDATA[8b-1:0]
EOP
CONST
PLEN[k-1:0]
WRAP
RSPACK
Response Handshake
RSPVAL
RERROR[E:0]
Response Contents
REOP
RDATA[8b-1:0]
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BVCI Protocol
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Packet Layer
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Packet
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Cell Layer
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BVCI Operations
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Transfer Responses
Read/Write cell/packet
successful
Read/Write packet general
error
Read/Write bad data error
Read/Write Abort
disconnect
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Advanced VCI
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Arbitration hiding
pipelines of both the request and response packets
Source Identification
a unique identifier for each initiator
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AVCI Protocol
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Cell layer
AVCI cell layer differs from BVCI with some additional
fields, with side band signals for arbitration hiding
Arbitration hiding signals are separately handshaken
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Outline
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On-Chip
RAM
AHB/ASB
DMA
Master
UART
PIO
APB
Bridge
Timer
Keypad
Features of AMBA
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Split transactions
single-cycle bus master handover
single-clock edge operation
non-tristate implementation
wider data bus configurations (8/16/32/64/128 bits)
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Technology independence
The specification only details the bus protocol at the
clock cycle level
Electrical characteristics
No information regarding the electrical characteristics is
supplied
Timing specification
The system integrator is given maximum flexibility in
allocating the signal timing budget amongst the various
modules on the bus
More free, but may also be more danger and timeconsuming
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Split transaction
NOT truly split transaction - the arbiter only masks the access of
the master which gets a SPLIT transfer response
Master does not need extra slave interface
Only allows a single outstanding transaction per bus master
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DMA channels
Use AHB protocol
E.g. PrimeCell SDRAM Controller
Easy to connect to another AHB bus
Wipros
SOC-RaPtorTM
Architecture
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AHB Interconnect
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address
direction
width
burst forms
Incrementing burst: not wrap at address boundaries
Wrapping burst: wrap at particular address boundaries
0x14
0x18
0x1C
0x20
0x24
INCR4
Address
wrap in 4word
boundary
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Address Decoding
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AHB Master
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AHB Slave
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HPROT[3:0]
HREADY_in
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Basic Transfer
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Master action
Slave action
Drive action
Sample action
Address &
Control
Data &
Response
Multiple Transfers
Three transfers to run related address A, B, and C
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Address &
control
Data &
Response
B
A
C
B
C
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HTRANS[1:0]
00
Type
IDLE
Descripton
01
BUSY
10
11
SEQ
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During T2-T3, master is unable to perform the second transfer of burst immediately
and therefore the master uses BUSY transfer to delay the start of the next transfer.
During T5-T6, slave is unable to complete access immediately, and uses HREADY
to insert a single wait state.
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Burst Operation
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Type
Descripton
000
SINGLE
Single Transfer
001
INCR
010
011
WRAP4
INCR4
100
WRAP8
101
INCR8
110
WRAP16
111
INCR16
WRAP4
0x30
0x34
0x38
0x3C
0x40
0x44
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Control Signals
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: Transfer direction
: Transfer size
: Protection control
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HPROT[3:0]
HREADY_in
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Transfer Responses
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HREADY
HRESP[1:0]
00
01
10
11
Response
OKAY
ERROR
RETRY
SPLIT
Two-cycle response
ERROR & RETRY & SPLIT
To complete current transfer, master can take following
action
Cancel for RETRY
Cancel for SPLIT
Either cancel or continue for ERROR
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Cancel
Error response
Wait
Error
Error
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Data Buses
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9
9
HWDAA
: 32 bits
RDATA
: 32 bits
Endianness : fixed, lower power; higher performance
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Arbitration
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Last Transfer of
last bus owner
Wait
Wait
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Arbiter
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Split Transfer
HREADY_in
HPROT[3:0]
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Split Transfer
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AHB-Lite
Requirement
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No arbiter
No Master-to-slave mux
Allows easier module design/debug
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AHB-Lite Interchangeability
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AHB-Lite Master
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AHB-Lite Slave
HREADY_in
HPROT[3:0]
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Master
#1
Interconnect
Matrix
Slave
#1
Slave
#2
Master
#2
Slave
#3
Master
#3
Slave
#4
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Local slaves
Multiple slaves on one slave port
Multiple masters on one layer
Mixed implementation of
AHB and AHB-Lite in a
multi-layer system.
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Width (bits)
PLB
APB
ASB
Mbus
PalmBus FISPbus
8, 16, 32 8, 16,
32,64
8, 16,
32,64
8, 16, 32
1 Data
Tranfer
1 Data
Tranfer
Data
Bus
Width
Data
Bus
Width
early,
middle.
late
AHB
8, 16, 32 32
2.9 GB/s, up to 32 8, 16, 32 2n,
183 MHz bit
n=3~10
128 bit
Peak
Bandwidth
(size/per cycle)
1 Data
Tranfer
Timing
Guidelines
2 Data
Tranfer
Synchronous
Data Bus
Distribu Multiple
Implementation ted And- xor
Or/
Multiple
xor
4 bytes
4 bytes
0.5 bus
width
1 bus
width
rising
clock
edge
falling
clock
edge*
PIbus
Plbus2
1 bus
width
rising
clock
edge
rising
clock
edge
Multiple Tristate
xor
0.5/1
Data
Tranfer
(v1/v2 )
rising
clock
edge
Tristate
Source - Black
: OCB 1 1.0
- Other colors : Update
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ARM
ARM7TDMI
ARM8
ARM9
ARM1020E
Transistors
74,209
124,554
111,000
7,000,000
0.5u
0.25u
0.18u
Clock Rate
66MHz
72MHz
200MHz
400MHz
Vdd
3.3V
2.5V
1.5
MIPS
60
220
500
Data Bus
32bits
32bits
32-bit A
64bit W
64-bit R
External memory bus
interface is AMBA AHB
compliant
32bits
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Outline
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Design Trends
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AHB/AXI Timing
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Introduction to AXI
Institute of Electronics, National Chiao Tung University
AMBA 3.0
AXI
AHB
NEC Electronics
(Europe)
OKI Electric
Industry
Philips
Semiconductors
Agere Systems
Fujitsu
Agilent
Hewlett-Packard
Company
ARM
Infineon
Atmel
LSI Logic
QUALCOMM
Cadence
Mentor Graphics
Samsung
Conexant
Systems
Matsushita
STMicroelectronics
CoWare Inc.
Micronas
Synopsys
Epson
Motorola
Toshiba
Corporation
Ericsson Mobile
Platforms
NEC Electronics
Corporation
Verisity
APB
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Channel Architecture
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Address
Read
Write
Write Response
ADDRESS
READ DATA
WRITE DATA
RESPONSE
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To read ...
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1. Master issues
address
ADDRESS
WRITE DATA
2. Slave
returns data
READ DATA
RESPONSE
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To write ...
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1. Master issues
address
ADDRESS
2. Master
gives data
WRITE DATA
3. Slave
acknowledges
READ DATA
RESPONSE
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AVALID
ADDR
AWRITE
ALEN
ASIZE
ABURST
ALOCK
ACACHE
APROT
AID
AREADY
WVALID
WLAST
WDATA
WSTRB
WID
WREADY
RVALID
RLAST
RDATA
RRESP
RID
RREADY
BVALID
BRESP
BID
BREADY
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Master
#1
Isolate address
timing
A
R
Master
#2
Slave
#1
Slave
#2
Slave
#3
Break long
interconnect path
Slave
#4
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ADDRESS
A11
DATA
A12
A22
A23
D31
D11
D21
D22
D23
D31
AHB Burst
Address and Data are locked together
Single pipeline stage
HREADY controls intervals of address and data
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ADDRESS
A11
DATA
A21
D11
D31
D21
D22
D23
D31
AXI Burst
One Address for entire burst
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ADDRESS
A11
DATA
A21
D31
D11
D21
D22
D23
D31
AXI Burst
One Address for entire burst
Allows multiple outstanding addresses
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ADDRESS
A11
A12
A22
A23
DATA
D31
D11
D12
With AHB
If one slave is very slow, all data is held up.
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ADDRESS
DATA
A11
A21
D31
D21
D22
D23
D31
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ADDRESS
DATA
A11
A21
D31
D21
D22
D11
D14
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AXI Multi-layer
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Master
Master
#1
#1
Master
Master
#2
#2
Bus
Bus
Matrix
Matrix
Slave
Slave
#1
#1
Slave
Slave
#2
#2
Slave
Slave
#3
#3
Master
Master
#3
#3
Slave
Slave
#4
#4
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Summary
Institute of Electronics, National Chiao Tung University
Channel architecture
Registers Slices
Burst addressing
Multiple outstanding bursts
Out of order completion
Interconnect Options
Shared bus, multi-layer and mixed
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