www.vidyarthiplus.com1 of 14.

UNIT 1 INTRODUCTION

Functional unit of a computer.

Digital computer systems consist of three distinct units. These units are as follows: Input
unit central processing unit Output unit these units are interconnected by electrical cables to
permit communication between them. This allows the computer to function as a system. Input
Unit A computer must receive both data and program statements to function properly and be
able to solve problems. The method of feeding data and programs to a computer is
accomplished by an input device. Computer input devices read data from a source, such as
magnetic disks, and translate that data into electronic impulses for transfer into the CPU.
Some typical input devices are a keyboard, a mouse, or a scanner. Central Processing Unit
The brain of a computer system is the central processing unit (CPU). The CPU processes data
transferred to it from one of the various input devices. It then transfers either an intermediate
or final result of the CPU to one or more output devices. A central control section and work
areas are required to perform calculations or manipulate data. The CPU is the computing
center of the system. It consists of a control section, an arithmetic-logic section, and an
internal storage section (main memory). Each section within the CPU serves a specific
function and has a particular relationship with the other sections within the CPU.
CONTROL SECTION The control section directs the flow of traffic (operations) and data.
It also maintains order within the computer. The control section selects one program
statement at a time from the program storage area, interprets the statement, and sends the
appropriate electronic impulses to the arithmetic-logic and storage sections so they can carry
out the instructions. The control section does not perform actual processing operations on the
data. The control section instructs the input device on when to start and stop transferring data
to the input storage area. It also tells the output device when to start and stop receiving data
from the output storage area. ARITHMETIC-LOGIC SECTION The arithmetic-logic
section performs arithmetic operations, such as addition, subtraction, multiplication, and
division. Through internal logic capability, it tests various conditions encountered during
processing and takes action based on the result. At no time does processing take place in the
storage section. Data may be transferred back and forth between these two sections several
times before processing is completed.

m
o

c
.
s

e
t
a
d

Addressing mode

p
u
u
a

Each instruction of a computer specifies an operation on certain data. The are various ways of
specifying address of the data to be operated on. These different ways of specifying data are
called the addressing modes. The most common addressing modes are:
Immediate addressing mode
Direct addressing mode
Indirect addressing mode
Register addressing mode
Register indirect addressing mode
Displacement addressing mode
Stack addressing mode
To specify the addressing mode of an instruction several methods are used. Most
often used are :
a) Different operands will use different addressing modes.
b) One or more bits in the instruction format can be used as mode field. The value of the
mode field determines which addressing mode is to be used.

Footer Page 1 of 14.

www.vidyarthiplus.com2 of 14.
The effective address will be either main memory address of a register.
Immediate Addressing:
This is the simplest form of addressing. Here, the operand is given in the instruction itself.
This mode is used to define constant or set initial values of variables. The advantage of this
mode is that no memory reference other than instruction fetch is required to obtain operand.
The disadvantage is that the size of the number is limited to the size of the address field,
which most instruction sets is small compared to word length.

m
o

Direct Addressing:
In direct addressing mode, effective address of the operand is given in the address field of the
instruction. It requires one memory reference to read the operand from the given location and
provides only a limited address space. Length of the address field is usually less than the
word length.
Ex : Move P, Ro, Add Q, Ro P and Q are the address of operand.

c
.
s
e
t

Indirect Addressing:
Indirect addressing mode, the address field of the instruction refers to the address of a word
in memory, which in turn contains the full length address of the operand. The advantage of
this mode is that for the word length of N, an address space of 2N can be addressed. He
disadvantage is that instruction execution requires two memory reference to fetch the operand
Multilevel or cascaded indirect addressing can also be used.

a
d
p
u
u
a

Register Addressing:
Register addressing mode is similar to direct addressing. The only difference is that the
address field of the instruction refers to a register rather than a memory location 3 or 4 bits
are used as address field to reference 8 to 16 generate purpose registers. The advantages of
register addressing are Small address field is needed in the instruction.

Register Indirect Addressing:

This mode is similar to indirect addressing. The address field of the instruction refers to a
register. The register contains the effective address of the operand. This mode uses one
memory reference to obtain the operand. The address space is limited to the width of the
registers available to store the effective address.

Displacement Addressing:
In displacement addressing mode there are 3 types of addressing mode. They are :
1)
Relative addressing 2) Base register addressing 3) Indexing addressing.
This is a combination of direct addressing and register indirect addressing. The value
contained in one address field. A is used directly and the other address refers to a register
whose contents are added to A to produce the effective address.
Stack Addressing:
Stack is a linear array of locations referred to as last-in first out queue. The stack is a reserved
block of location, appended or deleted only at the top of the stack. Stack pointer is a register
which stores the address of top of stack location. This mode of addressing is also known as
implicit addressing.

Footer Page 2 of 14.

www.vidyarthiplus.com3 of 14.
Organization of IAS computer with its instruction set.

m
o

c
.
s
e

t
a

Instruction Set Architecture (ISA)

The Instruction Set Architecture (ISA) is the part of the processor that is visible to the
programmer or compiler writer. The ISA serves as the boundary between software and
hardware. We will briefly describe the instruction sets found in many of the microprocessors
used today. The ISA of a processor can be described using 5 catagories:

u
u

d
p

Operand Storage in the CPU

Where are the operands kept other than in memory?
Number of explicit named operands
How many operands are named in a typical instruction?
Operand location
Can any ALU instruction operand be located in memory? Or must all operands be kept
internaly in the CPU?
Operations
What operations are provided in the ISA?
Type and size of operands
What is the type and size of each operand and how is it specified?
Of all the above the most distinguishing factor is the first.

a
.

The 3 most common types of ISAs are:

1. Stack - The operands are implicitly on top of the stack.

2. Accumulator - One operand is implicitly the accumulator.
3. General Purpose Register (GPR) - All operands are explicitely mentioned, they are either
registers or memory locations.
Lets look at the assembly code of
A = B + C;
in all 3 architectures:
Stack

Footer Page 3 of 14.

Accumulator

GPR

www.vidyarthiplus.com4 of 14.
PUSH A
PUSH B
ADD
POP C

LOAD A
ADD B
STORE C
-

LOAD R1,A
ADD R1,B
STORE R1,C
-

Not all processors can be neatly tagged into one of the above catagories. The i8086 has many
instructions that use implicit operands although it has a general register set. The i8051 is
another example, it has 4 banks of GPRs but most instructions must have the A register as
one of its operands.

m
o

What are the advantages and disadvantages of each of these approachs?

c
.
s
e

Stack
Advantages: Simple Model of expression evaluation (reverse polish). Short instructions.
Disadvantages: A stack can't be randomly accessed This makes it hard to generate eficient
code. The stack itself is accessed every operation and becomes a bottleneck.

t
a

Accumulator
Advantages: Short instructions. Disadvantages: The accumulator is only temporary storage
so memory traffic is the highest for this approach.

d
p

GPR
Advantages: Makes code generation easy. Data can be stored for long periods in registers.
Disadvantages: All operands must be named leading to longer instructions.

u
u

Earlier CPUs were of the first 2 types but in the last 15 years all CPUs made are GPR
processors. The 2 major reasons are that registers are faster than memory, the more data that
can be kept internaly in the CPU the faster the program wil run. The other reason is that
registers are easier for a compiler to use.
Basic operational concept of a computer
Most computer operations are executed in the ALU (arithmetic and logic unit) of a processor.
Example: to add two numbers that are both located in memory.
Each number is brought into the processor, and the actual addition is carried out by the
ALU.
The sum then may be stored in memory or retained in the processor for immediate use.

a
.

Registers
When operands are brought into the processor, they are stored in high-speed storage
elements (registers).
A register can store one piece of data (8-bit registers, 16-bit registers, 32-bit registers, 64-bit
registers, etc)
Access times to registers are faster than access times to the fastest cache unit in the memory
hierarchy.

Instructions
Instructions for a processor are defined in the ISA (Instruction Set Architecture) Level 2
Typical instructions include:
Mov BX, LocA
Fetch the instruction

Footer Page 4 of 14.

www.vidyarthiplus.com5 of 14.
Fetch the contents of memory location LocA
Store the contents in general purpose register BX
Add AX,BX
Fetch the instruction
Add the contents of registers BX and AX
Place the sum in register AX
How are instructions sent between memory and the processor?

m
o

c
.
s
e

d
p

t
a

The program counter (PC) or instruction pointer (IP) contains the memory
address of the next instruction to be fetched and executed.
Send the address of the memory location to be accessed to the memory unit
and issue the appropriate control signals (memory read).
The instruction register (IR) holds the instruction that is currently being
executed.

a
.

u
u

Timing is crucial and is handled by the control unit within the processor.
MAR memory address register holds the address of the location to be
accessed.
MDR memory data register Contains data to be written into or read out of the
address location
General-purpose register (R0 Rn-1)
Typical Operating Steps:
Programs reside in the memory through input devices

PC is set to point to the first instruction

The contents of PC are transferred to MAR

A Read signal is sent to the memory

The first instruction is read out and loaded into MDR

The contents of MDR are transferred to IR

Decode and execute the instruction
Generation of computer.
Electronic Computers
The advance of semiconductor technology has made computing affordable.
The reduction in price and improvement in performance has made computer much more
affordable and powerful. The first important improvement of so-called computer is from

Footer Page 5 of 14.

www.vidyarthiplus.com6 of 14.
mechanical to electronic in 1930s. The first large-scale digital computer ENIVAC was built
in 1946 by University of Pennsylvania.
The first generation computer, built between 1939 and 1957, used vacuum tubes, which
consumed a lot of power and space. They tend to overheat and burn out quickly; as a result
they were expensive and unreliable. They are mainly for scientific use due to its high costs.
The second-generation (1956-1963) computers use transistors instead of vacuum tubes.
They use less power, take up less space, and become more reliable and less expensive. Now
the computers become more affordable and more business can use them.
The third-generation (1964-1971) computers use integrated circuit (IC) technology that
integrates many electronic components into a single silicon chip, to make computers faster,
smaller, and cheaper.
The forth generation (1971-Present) computers take one step further and introduce Largescale integration (LSI) and Very Large Scale Integration (VLSI) so that we can package an
entire processor into a single chip.
Programming has evolved from a tedious error-prone job to machine-assisted, semiautomatic process.
Computers are classified according to their sizes and speed. They are microcomputer,
minicomputers, mainframe computers, and super computers.
Fifth Generation (Present and Beyond) Artificial Intelligence, based on artificial
intelligence, are still in development, though there are some applications, such as voice
recognition, that are being used today. The use of parallel processing and superconductors is
helping to make artificial intelligence a reality. Quantum computation and molecular and
nanotechnology will radically change the face of computers in years to come. The goal of
fifth-generation computing is to develop devices that respond to natural language input and
are capable of learning and self-organization.

m
o

t
a

d
p

u
u

c
.
s
e

Design Methodology
A computer is an example of system. It is a large and complex system in which objects are
called components. These components are interconnected to perform a specific function. The
function of the system is determined by the function of the components and how components
are connected.
Gate Level:
A useful way of modelling a system is a graph contains set of objects called nodes and set of
edges. The edges connect node to node. Nodes are represented by circle and edges are
connecting by lines. Resultant graph is often called Block Diagram
(Diagram refer text book)
Draw a Block Diagram representing an Exclusive OR logic circuit---- refer text book
A system has its own structure and behaviour. The structure of a system is defined as the
abstract graph consists of its block diagram with no functional information. In general, a
structural description the component and define their interconnection and a behaviour
description describes the function of each component and thus the function of the system.
The system behaviour of the logic circuit is Truth Table. Include truth table of Exclusive
OR functions.
Design Level
Component
IC density
Information units Time units
CPU, Memories VLSI
Process
Block of words 10-12 to 10-9 s
& IO devices
Register, counter, MSI
Register
Words
10-9 to 10-8 s
combination
circuits,
small
sequential

Footer Page 6 of 14.

a
.

www.vidyarthiplus.com7 of 14.

Gate

circuits
Logic gates and SSI
filp flops

10-12 to 10-9 s

Bits

Register Level:
At register level, related information bits are grouped into ordering sets called Word or
Vector. The primitive components are small combination circuits intended to store words.
Register level design steps:
The general approach to design registers level system.
1. Define the desire behaviour of the system.
2. Analyse the algorithm, to determine the types of the components and number of each
type queried for the data path.
3. Construct block diagram for the data path using the component identified in step 2.
4. Analyse algorithm and data path to identify the control signals needed. Introduce the
logic control points necessary to apply these signals into data path.
5. Design a control path that meets all the requirements of algorithm.
6. Check whether the final design operates correctly and meet all performance cost goal.
Type
Component
Function
Combinational
Word gate
Boolean operations
Multiplexer and de
Data routing, general
multiplexer
combinational functions
Decoder and encoder
Code checking and
conversion
Adder
Addition and subtraction
Numerical and logical
ALU
operation
Programmable logic devices Numerical and logical
operation
Sequential
Register
Information storage
Shift register
Information storage and
serial parallel conversion
Counters
Control and timing signal
generation
Programmable logic devices General sequential function

a
.

t
a

d
p

u
u

m
o
c
.
s
e

Processor Level (System Level)

Processor level is the highest hierarchy in the computer design. Main objective of this level is
processing in the digital information and storage of block of information such as program and
data file. Designing of this level is very complex and usually constructed by sequential
circuits based on VLSI technology.
The 4 major components are generally used are:

Processors

Memories

IOdevices

Interconnection network

Footer Page 7 of 14.

www.vidyarthiplus.com8 of 14.

m
o

c
.
s
e
t

CPU: Is a general purpose, instruction set processor has overall responsibility for
program interpretation and execution in a computer system. The primary function of CPU is
to execute the instruction sequentially which is stored in an external memory.The processor
contains necessary logic circuits to execute instruction set and is divided into data path and
control units.

Footer Page 8 of 14.

a
d
p
u
u
a

www.vidyarthiplus.com9 of 14.

m
o

c
.
s
e
t

I-Unit: The function of the control unit generates the addresses of instruction and data
stored in external memory.
-A cache memory is placed between the main memory M and the CPU.The cache is
afast memory designed to hold temporary data which is currently used by the CPU.
- Each memory access, the CPU is first directed to the cache. If the required
information is not currently assigned to the cacher,the request is redirected to Main memory
M and the cache is automatically updated from M.
- The I-unit fetches instruction from the cache (or) memory M and decodes them to
generate necessary control signal needed for their execution.
E-Unit:
The data path has the arithmetic-logic circuits that execute the most instructions & set
of registers for temporary storage.
The CPU manages a system bus,which is the communication path between
cache,M,CPU & IO devices.
To execute the program from memory the following steps to be carried out by the
processor:
1. The CPU fetches instruction from cache or M.
2. Loaded into the instruction register.
3. Then decode the instruction to determine what operation to be carried out by the
processor.
4. Generate necessary control signals to enable execution of the instruction.
5. Mean while the program counter(PC) point the address of next memory location to be
execute by the processor.
The entire process Fetching(F),Decoding(D) and Execution (E) constitutes the CPU s
Instruction Cycle.

a
d
p
u
u
a

Memories:
Cpus operate in conjunction with external memories that store the programs and data
required by the processors.The cost of a memory device generally increases rapidly with its
speed of operation. The computer memories can be divided into several sub systems:
- Memory(M)
- Secondary Memory
- Cache Memory
Main Memory(M):
- Fast storage memory connected directly to & controlled by the CPU.
Is a random-access memory (RAM).The access time for every location in M is the
same.Wheras in serial access, the memory access times vary with the location being accessed.

Footer Page 9 of 14.

www.vidyarthiplus.com10 of 14.
- Serial access memory is slower and less expensive than RAM.
Secondary Memory:
- Slow, Low cost & have very high storage capacity.
Use some form of serial access. Because of the serial access the operating speed of the
device is slow.
- Slow memory than M because the device involve mechanical motion.
- Connected indirectly to CPU.

m
o

Cache:
- Fast memory, Expensive placed between CPU and M.
Objective of this memory is to reduce the average time taken by the CPU to access the
Memory System.
- Uses Random access method called associative or content addressing.
IO devices:
The computer can communicate with outside world with help of input-output devices.
The IO devices act as a data transducers,i.e to convert information media they involved. The
speed of operation of these devices is slow compared with the processor & M because the
devices use electro-mechanical technologies.
- The CPU take direct control of an IO device through special purpose processor or control
unit that directs the flow of information between the IO device and main memory.
Interconnection Networks:
The processor level components communicate via the system bus. If many components
are used, communication between these components may be controlled by a subsystem called
an Interconnection network.
The primary function of this network is to establish communication paths among the
components via the buses under its control.
The multiplexed bus is commonly used among the devices to reduce the cost i.e. only
two communicating devices can access and use a shared bus at any time, so contention result
when many devices request to use of the system bus.
The interconnection network resolves such contention by selecting one of the requesting
devices on some priority basis and other requesting devices.

c
.
s
e

t
a

d
p
u
u
a
.

Instruction formats.
An instruction format defines the layout of the bits of an instruction. It must include opcode,
zero or more operand and addressing mode for each operand. The instruction length is
usually kept in multiple of the characters length. or memory transfer length which is usually 8
bits. Once the instruction length is fixed, it is necessary to allocate numbers of bits for
opcode, operands and addressing mode. For an instruction format of a given length, if one
number of m bits is allocated for addressing can be determined by the following factors,
which simplifies the task of allocating bits in the instruction.
Number of addressing mode.
Number of operand
Number of CPU registers.
Number of register sets.
Address range or number of address lines.
Address granularity
Opcode
Addressing mode
Displacement
immediate
1 or 2 bytes
1 or 2 bytes
1 or 4 bytes
1 or 4 bytes
Figure shows General IA 32 instruction formats

Footer Page 10 of 14.

www.vidyarthiplus.com11 of 14.

It contains 4 fields. Opcode field/ address mode consists of one or two bytes. For instruction
that involve the use of only one register in generating the effective address of an operand,
only one byte is needed in the addressing mode. The addressing mode, base with the index
and base with index and displacement requires two registers to generate the effective address
of an operand. Hence addressing mode field for these two addressing mode is two bytes.
If a displacement value is used in computing an effective address for a memory operand, it is
encoded into either one or four bytes in a field that immediately follows the addressing mode
field.

c
.
s
e
t

m
o

If one the operand is an immediate value, then it is placed in the last field of an
Instruction and it occupies either one or four bytes. Instruction format of a processor also
changes accordingly to the address
How many bits are needed to specify 32 distinct operations?
Solution: 25 = 32. Therefore, 5 bits are needed for specify 32 distinct operation.

Instruction Formats
It is the function of the control unit within the CPU to interpret each instruction
Code
The bits of the instruction are divided into groups called fields
The most common fields are:
Operation code
Address field memory address or a processor register
Mode field specifies the way the operand or effective address is
determined
A register address is a binary number of k bits that defines one of 2k registers in
the CPU
The instructions may have several different lengths containing varying number
of addresses
The number of address fields in the instruction format of a computer depends
on the internal organization of its registers
Most computers fall into one of the three following organizations:
Single accumulator organization
General register organization
Stack organization
Single accumulator org. uses one address field
ADD X : AC AC + M[X]
The general register org. uses three address fields
ADD R1, R2, R3: R1 R2 + R3
Can use two rather than three fields if the destination is assumed to be one of
the source registers
Stack org. would require one address field for PUSH/POP operations and none
for operation-type instructions
PUSH X
ADD
Some computers combine features from more than one organizational structure
Example: X = (A+B) * (C + D)
Three-address instructions:

Footer Page 11 of 14.

a
d
p
u
u
a

www.vidyarthiplus.com12 of 14.
ADD R1, A, B R1 M[A] + M[B]
ADD R2, C, D R2 M[C] + M[D]
MUL X, R1, R2 M[X] R1 * R2
Two-address instructions:
MOV R1, A R1 M[A]
ADD R1, B R1 R1 + M[B]
MOV R2, C R2 M[C]
ADD R2, D R2 R2 + D
MUL R1, R2 R1 R1 * R2
MOV X, R1 M[X] R1
One-address instructions:
LOAD A AC M[A]
ADD B AC AC + M[B]
STORE T M[T] AC
LOAD C AC M[C]
ADD D AC AC + M[D]
MUL T AC AC * M[T]
STORE X M[X] AC
Zero-address instructions:
PUSH A TOS A
PUSH B TOS B
ADD TOS (A +B)
PUSH C TOS C
PUSH D TOS D
ADD TOS (C + D)
MUL TOS (C + D) * (A + B)
POP X M[X] TOS
RISC and CISC architectures
No
Characteristics
CISC
RISC
1
Instruction size
Various
Fixed
2
Instruction length 1,2,3 or 4 bytes
4 bytes
No of instructions More
3
Less
4
Instruction decoding Serial to decode
Easy to decode
Varies from simple Almost always one simple
5
Instruction
semantics
to complex
operation
complex Complex addressing modes
6
Addressing modes Support
addressing modes
are synthesized in software
7
Instruction
Slow
Medium
execution speed
8
Instruction
By micro program By hardware
execution
9
Registers
Few
Many
with Not combined with operation
10
Memory references Combined
operation
11
Hardware
Complicated
Simple
12
Memory access
Frequently
Rarely
13
Pipeline
Less pipelined
Highly pipelined
14
Compiler
Simple
Complicated
15
Examples
ARM, 8051 etc
Intel X86, Motorola 68000

c
.
s
e
t
a
d
p

Footer Page 12 of 14.

u
u
a

m
o

www.vidyarthiplus.com13 of 14.

Bus Structure

There are many ways to connect different parts inside a computer together. A group of lines
that serves as a connecting path for several devices is called a bus. Bus must have additional
lines for Address/data/control.
Simplest way:
Interconnect functional units to a single bus. Only two units can actively use the bus. Control
units arbitrate multiple requests for the use of bus.
Advantage of using Single bus
Low cost,
Flexibility to attach many peripherals.
Multiple bus: Better performance, Cost is high.
Bus structure and multiple bus structures are types of bus or computing. A bus is basically a
subsystem which transfers data between the components of Computer components either
within a computer or between two computers. It connects peripheral devices at the same time.

m
o

c
.
s
e

t
a

- A multiple Bus Structure has multiple inter connected service integration buses and for each
bus the other buses are its foreign buses. A Single bus structure is very simple and consists of
a single server.
- A bus cannot span multiple cells. And each cell can have more than one buses. - Published
messages are printed on it. There is no messaging engine on Single bus structure

d
p
u
u
a
.

(i)
In single bus structure all units are connected in the same bus than connecting
different buses as multiple bus structure.
(ii)
Multiple bus structure's performance is better than single bus structure. Iii)single bus
structure's cost is cheap than multiple bus structure.
Note:Refer Diagram from Text Book for Single and multiple bus.
Floating point number and operation
B = b0.b-1b-2.b-(n-1)
0
F(B) = -b0*2 +b1*2-1+ b2*2-2 . b-(n-1)*2(n-1)
Where the range of the F is:
-1F1-2(n-1)
The position of the binary point is variable and is automatically adjusted as computation
proceeds.
What are needed to represent a floating-point decimal number?
1. Sign
2. Mantissa (the significant digits)
3. Exponent to an implied base (scale factor)
4. Normalized the decimal point is placed to the right of the first (nonzero) significant
digit.
IEEE Standard for Floating-Point Numbers
Think about this number (all digits are decimal): X1.X2X3X4X5X6X7x10Y1Y2
It is possible to approximate this mantissa precision and scale factor range in a binary
representation that occupies 32 bits: 24-bit mantissa (1 sign bit for signed number), 8-bit
exponent.
Instead of the signed exponent, E, the value actually stored in the exponent field is an
unsigned integer E=E+127, so called excess-127 format

Footer Page 13 of 14.

www.vidyarthiplus.com14 of 14.

For excess-127 format, 0 E 255. However, 0 and 255 are used to represent special
value. So actually 1 E 254. That means -126 E 127.
Single precision uses 32-bit. The value range is from 2-126 to 2+127.
Double precision used 64-bit. The value range is from 2-1022 to 2+1023
As computations proceed, a number that does not fall in the representable range of normal
numbers might be generated.
It requires an exponent less than -126 (underflow) or greater than +127 (overflow). Both
are exceptions that need to be considered.
The end value 0 and 255 are used to represent special values.
When E=0 and M=0, the value exact 0 is represented. (0)
When E=255 and M=0, the value is represented. ( )
When E=0 and M0, decimal numbers are represented. The value is 0.M2-126
When E=255 and M0, Not a Number (NaN).

c
.
s

m
o

Exception:
A processor must set exception flags if any of the following occur in performing
operations: underflow, overflow, divide by zero, inexact, invalid.

e
t
a
d

When exception occurs, the results are set to special values.

For 2 marks:
1. speed enhancing features used to improve system performance, underflow and
overflow, Big Endian and Little Endian, sequence of operation in instruction execution,
CPI, straight line sequencing, Register transfer, addressing modes, auto increment and
auto decrement addressing mode, priority encoder.

Footer Page 14 of 14.

p
u
u
a