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Introduction To Low Power Rf-Ic Design Rfdr.
Introduction To Low Power Rf-Ic Design Rfdr.
POWER RF-
RF-IC DESIGN
Dr. T K Bhattacharyya PART – I
E & ECE Dept.
Basics of RF Design
Advanced VLSI Design Lab.
IIT Kharagpur..
• Kirchoff's to Maxwell’s…….
Automobile and Highways
Sensors:
• Failure of two port circuit parameter (Z, Y,ABCD) ……..
Medical
• Scattering parameter( S-parameter) on the basis of Maxwell equation Radio- astronomy and space exploration
comes in …
Ceramic
No net current build Capacitor Thin Film
SMD comp.
up at any node(KCL)
•If ε & μ =0, (c α ) i.e infinitely fast wave
Resistor Carbon
propagation of wave gives KVL and KCL Thin Film
SMD comp.
•As the physical dimension of circuit element & sub-circuit in a IC chip is very less
(even less than 1/10th of λ [ 30 cm in air at 1 GHz] ) , so finiteness of the speed of Inductor Wire Thin Film
light is not noticeable inside chip, so a full transmission line ( Microwave) for on- Wound SMD comp.
chip design and analysis is generally unnecessary. Kirchoff’s law is well suited for on-
chip design
•But for interfacing the RF signals in / out of the chip, we need connectors,
boards, cables etc. Where transmission-line effects cannot be ignored
Comparison of Analog and RF/MW Comparison of MMIC/RFIC
1. On Performance Based
( Analog [Low frequency<100MHz] ) ( RF/MW [High frequency>100MHz] ) Parameter MMIC( Discrete) RFIC( integrated)
Development Cost Moderate Very high
A. Small signal AC equivalent circuit A. Small signal AC equivalent circuit
Modifications Relatively easy & inexpensive Expensive ,generally one or
analysis analysis with parasitic i.e. Good circuit more new mask
Modeling
BOM cost Low Depends on volume , die sized
B. Linearity B. Matching and process used
Mixing Technologies Optimum device technology can Limited scope
C. Stability C. Noise be used through out ( combined
GaAs, BJT, MOS)
D. Noise (on few cases) D. Stability
Parts Count High Low to very low
E. Linearity Size Small to medium Smallest
F. Sensitivity Weight Light Lightest
1. Phase shift of the signal is significant over the extent of the component because it’s size is
comparable with the wavelength.
2. The reactance of the circuit must be accounted for, particularly those associated with the
parasitic of the active devices.
3. Circuit losses causes degradation of Q, reduction of frequency selectivity and noise
performance.
• Disciplines required in RF design 4. Noise especially arising from the circuit can be significant and it’s effect needs to be modeled.
5. Electromagnetic radiation capacitive coupling and substrate coupling significantly alter the
performance of the circuit.
6. Reflection issues, because circuit size is of the order of a wavelength.
7. Circuit design should take care to ensure reflections do not cause any loss of gain, power, or
failure of components.
8. Nonlinearity which causes distortion and unwanted frequency components is undesirable, but
it may become essential part of the circuit operation, as in mixing or local oscillators.
Thermal agitation of channel charge cause fluctuation of channel potential. This couples
Significance :The significance of noise performance of a circuit is the limitation it places on the
capacitively with gate terminal, leading to gate noise
smallest input signals(MDS) the circuit can handle before the noise degrades the quality of output signal.
• this noise is negligible at low frequency, but can dominate at RF
• Thermal Noise
-Brownian motion of thermally agitated charge carriers - generated in every physical resistor
Shot Noise
- pure reactive components generate no thermal noise
-Gaussian white process associated with the transfer of charge across an energy barrier
Thermal Noise in MOSFET - due to DC current through p-n junction, gate channel
Th most significant source of noise
Channel Noise:
Flicker noise in MOSFET
In2 = 4kTγgm
• γ ~1 at a zero VDS for long channel device, 2/3 at saturation, 2-3 for short channel transistor -random trapping of charge at oxide interface
- modeled as a voltage source in series with gate
Noise figure Noise figure (cont..)
• Limitation : Noise figure is definable only when input source is resistive ------
important parameter on communication system as the source impedance in this
system is often resistive - NF is minimized by maximizing Rp
- Maximum power transform possible
•Definition : when Rs =Rp
For m- stages
• NF of each stages is calculated with respect to the output impedance of previous stages
• The noise is contributed by each stage decreases as the gain preceding the stages increase
•That’s why the first stage of any system should have higher gain with low noise figure ( PRIME
CRITERION FOR LOW NOISE AMPLIFIER (LNA) DESIGN OF A RECEIVER)
Examples
V 2 nR s = 4kTR s Δf
LINEARITY ISSUES
i 2
n1 = 4kTγg d0 Δf
4kT
i2 nR D = Δf
R D
sL
Vgs = Vns
R s + sL
{(R / ωL)2 + 1}γg d 0 1 + (R / ωL) 2
NF = 1 + + 2
g 2m R s g mRsR D
Linearity Issues Cont… Linearity Issues Cont…
MOSFET current :
1 dB compression point
IIP3 value
g(Vo), g(V+), g(V-) are the Transconductance value, Where
V0 is the dc-bias voltage, V+ is slightly higher and V- is
slightly lower
CG -stage
Cds gives positive feed back, so stability reduce
•As real circuit are complex, proper analysis of transfer function is required and
compensation technique is used to obtain good stability (such as OPAMP)
Dynamic Range
High Frequency Device modeling
Silicon Technologies
RF CMOS MODELLING
“Standard” (digital oriented) MOS models do not allow for RF
Maximum unit power gain
frequency
Maximum Cut-
Cut-off frequency
Rpoly R Csub
Cgs Cgd Cds
•To calculate magnetic coupling between two adjacent metal line, interlayer capacitance ,
EMI between subcircuits & on-chip passive component (such as inductor and MIM In RF, Cgs ( whose effect negligible in low frequency analog) affects the matching with
capacitor) , the Maxwell EM equation is required ( Challenging issue !!!) successive blocks . Frequency dependence of Transconductance(gm )
RF CMOS MODELLING
Long channel effect
ON-
ON- CHIP PASSIVE COMPONENT
1 W On-Chip inductor realization
I
d
= μ n C ox ( Vgs − V t ) 2
2 L
3 μn
At RF frequencies, matching network consists of number
f
T
= ( V gs − V t ) of inductors. Therefore on-chip realization of inductors is
2 2 π L2
Sort channel effect
d v
important for RF IC design.
μ ε ε =
V = n
d y
d
ε
1 +
,
ε c Three kind of inductors :
1 dv dv
Id = Q I WVd (y) I d (1 + . ) = W Q I ( y )μ n
εc dy dy ¾ ACTIVE INDUCTOR → More noisy, highly non-linear, High Q with large L
I =
μ n C W o x
(V − V ) 2 value possible , frequency dependent, higher power consumption.
d
− V t
V L
g s t
2 (1 + g s
)
ε cL
μ n C ox
¾ BOND WIRE INDUCTOR → Depends on curvature, High Q(~60), Typical
=
W
( V gs − V t ) 2 Vscl = μ n ε c
2[1 + θ ( V g s − V t )] L value : 1nH/mm, series resistance : 0.2 Ω/mm(1mm φ).
2 ( V gs − V t )
1+
εcL
−1 ¾ ON-
ON- CHIP SPIRAL INDUCTOR → Less Q (3-6), In CMOS process
g = W C V scl
m ox
2 ( V gs − V t ) maximum 10nH value possible with reasonable Q values, very small DC power
1+ ,
c.f Lee P-68,70 Cgc = Cox Ccb = Csi ε cL consumption….At very low (<0.5nH) L value → interconnect parasitics dominate…
C sbo C dbo
At high (>10nH) L values → Large area, Higher losses.
C jsb = C =
V jd B
V db 1/ 2 • fT independent of overdrive voltage (Vgs − Vt )
(1 + sb )1 / 2 (1 + )
ψ0 ψ0
• fT inversely proportional to L
PART – II
Transceiver Design
T/R
• Power efficiency • Sensitivity
Frequency
Synthesizer
Switch • Modulation accuracy • Selectivity
• Carrier leakage • Noise
IF or Up PA • Power consumption • Dynamic Range
baseband Converter
• Linearity
Simplified Diagram
• Power consumption
Standards
Transmitter Architecture
GSM Bluetooth Zigbee
Transmission TDMA & FDD FHSS(Frequency DSSS(Direct Sequence
scheme Hopping Spread Spread Spectrum) Modulation and upconversion
Sprectrum) are done in the same circuit
Frequency Band Tx : 890 – 915 MHz 2.4 GHz 2.4 GHz, 915 MHz, 868
Rx : 935 – 960 MHz MHz Simplicity lends it to high
degree of integration
Modulation scheme GMSK(Gaussian GFSK(Gaussian QPSK(Quadrature Phase
Minimum Shift Keying) Frequency Shift Keying) Shift Keying) or BPSK
depends on the freq band Direct Conversion Transmitter
Sensitivity -102 dBm -70 dBm for 0.1% BER -85 dBm (2.4GHz) or -92
dBm (915/868 MHz) for
packet error rate < 0.1%
0.8 – 20 W Maximum 100 mW, Minimum capability
Important drawback: Output of
Transmitted power
2.5mW or 1 mW 0.5mW, Maximum as the PA tends to shift the LO
depending on class allowed by local output as its spectrum lies
regulations around LO frequency.
Data Rate 270 KBPS 1 MBPS 250 KBPS, 40 KBPS or
20 KBPS ( depending on LO Pulling by PA
frequency band)
Transmitter Architecture (contd.) Wide-band Transmitter Architecture
LO pulling is avoided by
having the PA output
spectrum sufficiently away
from that of LO
Homodyne Receiver
Problem of Image
Images can be several
times larger than the Simplicity lends it to
wanted signal mandating efficient on-chip
an Image Rejection Ratio Simple Homodyne or Direct Conversion Receiver implementation
(IRR) of at least -70 dB.
Problem of image is not
Problem of Image
Very high Q requirement there.
is usually placed on the
Image Reject Filter To be more precise
“images” in this case comes
from the same channel and
High IRR or Facilitates hence are of comparable
High IF
Image Rejection magnitude as of the desired
Facilitates Channel signal. Hence IRR of around
Low IF -40 dB is typically sufficient.
Selection
Quadrature Downconversion in DCR
Optimum Value of IF needs to be chosen
Use of image reject filter
Demerits of DCR Image Reject Architectures
Final Block
Image Rejection using Polyphase Filter Level Specs
Given
•SNRout Required = 14 dB
•Sensitivity Required( Pin,min) = -90 dBm
•Bandwidth = 2 MHz
The required Noise Figure of the receiver front-end is calculated
Block Diagram of the Receiver System from the sensitivity eqn.
Ap = A p1 × A p2 × L × A pk
Total Noise Factor
NF2 − 1 NF3 − 1 N Fk − 1
NF=NF1 + + + ..... +
A p1 A p1 A p2 A p1 A p2 ...A p(k-1)
Total IIP3
1 1 A A A A A ...A p(k-1)
= + p1 + p1 p2 + ..... + p1 p2
IIP3 IIP3,1 IIP3,2 IIP3,3 IIP3,k
Where NFi, Api and IIP3,i are respectively Noise Factor ,
Available Power Gain and input 3rd order intercept point of the
i-th stage
WHY ON-CHIP ?
¾ 4 P-words :
Price : Mass volume production reduces price
Package : Integration reduces No of total pin count
ON-CHIP GHz Performance : Improves except few cases
Power : On-chip components dissipate lesser power
CMOS LOW NOISE AMPLIFIER ¾ Challenges :
Poor quality of passive components (inductor etc.)
Device modeling at RF frequencies
Realizing good analog circuits in digital technology
Meeting stringent performance requirements in digital
environment. Substrate noise coupling is more critical in
mixed signal
Differential LNA
Other LNA Structures
¾ The single ended LNA (especially for source degeneration topology), the
¾This is a common gate topology. the impedance
ground parasitic inductor is a crucial since degeneration inductor value is
looking from source end is 1/(gm+gm-bulk). This should be
small → parasitic dominates in operation
made 50ohm for matching (active matching).
¾ The ground inductor can be tuned by putting extra cap across ground line
¾The Ls cancels the Cgs value. inductor, but any cap in source line produces a negative resistance in input.
¾The noise figure is poor. This causes stability problem.
Center Frequency; ωo (GHz) Oscillators are autonomous circuits that produce periodic
Tuning Range (MHz) output without any periodic input.
Tuning Sensitivity; KVCO (Hz/volt) Three main topologies and their Comparison:
Spectral Purity or Phase Noise (dBc/Hz @ Hz offset)
Power Consumption (mW) TYPE Principle On-chip? GHz ? PN
Output Power (mW)
Ring Cascaded inverters YES YES POOR
Harmonic Suppression (dBc)
Load Pulling : Frequency changes with Load changes Relaxation Cap is charged and YES YES POOR
Supply Pulling : Frequency change with VDD (Hz/volt) discharged
LC-Tuned LC resonance YES YES GOOD
(difficult)
QVCO Architecture VCO Core: LC negative
Resistance Oscillator
I Common Mode Feedback
LC VCO Capacitive Cross-
Worse Phase coupling of PMOS pair
+ - + - + - + - Noise as The Complementary Cross-coupled VGS
VGS
compared to 900 structure is chosen as it V PMOSVDS
- + - + - + - + LC oscillator MHz provides more energy to
DS
Our
Parameters [1] [2] [3]
work
Technology 0.25 μm 0.18 μm 0.18 μm 0.18μm
Supply (Volt) 2.5 1.8 1.5 1
Phase noise Tuning Range 0.667- 0.825–
Output waveform of VCO and QVCO 1.71–1.99 1.05–1.39
(GHz) 1.156 0.975
KVCO(MHz/V) -- -- -- 50
-143@ 3 -137@ 3 -124@ -136@ 3
Phase Noise
MHz MHz 600KHz MHz
KVDD(MHz/V) -- -- -- 6
Power (mW) 20 5.4 30 3.5
FOM (dBc/Hz) -185.5 -180.96 -- -180.1
2
⎛ Δf ⎞
Variation of frequency and KVDD(Δf/ΔVDD) F O M = S SSB ⎜ ⎟ PV C O / m W
Tuning curves ⎝ f0 ⎠
with supply voltage
System simulation results Measurement Results
(VCO)(contd.)
MIXER
MIXERS
Block diagram representation of Mixer Basic Mixer operation and its MOS equivalent
Current reuse
+ -
0 1.7-1.9 GHz
850 – 950 MHz LNA gain stage
- + - +
- +
180
850 – 950 MHz
90
+ -
+ - + - - +
270
850 – 950 MHz
LO (VCO+Div2+Buffer)
DOUBLED BALANCED EVEN-HARMONIC MIXER PCB matching components
The circuit is a "three level multiplier", composed of two PCB 50 ohm Transmission line 1 MHz
Q
stages, a double-balanced switching cell and a differential
transconductance stage. Gilbert Cell
Layout of the complete RF Front-End
(KGPLPRX)
System QVCO
FREQEUNCY
LNA
SYNTHESIZERS
LNA &Mixer
System
Frequency Synthesizer
Building blocks of frequency Synthesizer
¾ Motivation-
¾ All frequencies in the band of interest from the reference frequency
¾ PLL based frequency synthesizer is a negative feedback system that locks ¾ High degree of purity due to the ever decreasing channel spacing
¾ Low power consumption
both phase & frequency
¾ Low cost
¾ Basic building blocks of PLL based frequency synthesizer are ¾ High integration
¾ Phase Frequency Detector (PFD) Æ Sequential tri-state dual DFF PFD ¾ Explosive growth in demand for wireless communication services
¾ Charge Pump Æ Constant UP/DOWN Current sources with Switches
on Drain ¾ Direct Analog/Digital Synthesis-
¾ Fine frequency resolutions and fast switching times
¾ Loop filter Æ Passive 3rd order low pass filter ¾ Not suitable for high frequency and low phase noise synthesis
¾ Voltage Control Oscillator (VCO) Æ Low KVCO, low KVDD, low phase
noise LC VCO with on-chip inductor ¾ Indirect PLL based Synthesis-
¾ Programmable Integer N Frequency Divider Æ Divide by 2/3 pre- ¾ Fine frequency resolutions and fast switching times
¾ Suitable for high frequency stability and accuracy, low phase noise and high frequency
scalar structure with both Current Mode Logic (CML) structure for high (even in giga-hertz frequency range) synthesis
frequency division and digital logic structure for low frequency division ¾ Amenable to full integration on a standard CMOS technology
¾ > FREF; Down Exact PLL ¾ Gives difference between Reference and output phases.
locking is nonlinear ¾ Usually implemented digitally.
phenomena. ¾ Most widely used topology → Sequential tri-state dual DFF
¾ If FVCO/N output of PFD PFD.
will turn enable more often
than Up.
¾ Loop filter control voltage
→ goes down → FVCO
goes down.
¾ Typically; ts = 25/FREF.
ts : settling time.
Loop Filter
Charge Pump
¾ Gives infinite DC gain with passive filters → Needed for zero ¾ Usually a Low pass filter.
phase error. ¾ Provides a stabilizing zero for the loop (C2, R2).
¾ Consists of two or more Current sources, switched ON/OFF ¾ Determines loop’s transient behavior.
by PFD outputs. ¾ Active or passive implementation possible.
¾ Mismatches & Leakage in charge pump → Spurious ¾ Passive filter → No active device noise, easy on-chip
component in PLL output. implementation.
¾ Three main topologies: ¾ Filter order → decides spurious
Switch at Drain suppression (typically 2-3).
Switch at Source
Switch at Gate
¾ Filter Design parameters:
Divider output
when no input is
given; Unlocked
condition
Divider output
when 5MHz input
is given; locked
Die area: 1812.4um x 1965.04um Snapshot of the PCB condition
References
Comparison of performance (cont ..) • [1] B. Razavi, RF Microelectronics, NJ: Printice Hall, Upper Saddel River, 1998.
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4) 2.4-2.5GHz
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