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Mixed VHDL-Verilog Tutorial

Table Of Contents
Mixed VHDL-Verilog Tutorial ........................................................................................................... 1
Introduction .................................................................................................................................. 1
VHDL Model................................................................................................................................. 2
Verilog Module ............................................................................................................................. 5
Top-Level Schematic ................................................................................................................... 6
Simulation .................................................................................................................................. 11

Mixed VHDL-Verilog Tutorial

Introduction
The focus of this tutorial is to get you acquainted with Active-HDL's ability to mix VHDL and
Verilog descriptions in a single project.
1. After starting the Active-HDL environment, the Getting Started window appears. Select the
Create new workspace option and click the OK button. The New Workspace wizard will start.
The wizard consists of one dialog in which you should provide a name and location for the new
workspace.

Make sure that the Add New Design to Workspace checkbox is selected and click the OK
button. As a result, the New Design Wizard will be invoked.
2. In the first window of the wizard select the design sources creation method, choose the Create
an empty design option and click the Next button.
3. The subsequent wizard window allows selecting synthesis and implementation tools,
programmable device vendor and family, Block Diagram configuration, and target language. In
this window, choose Verilog as the default HDL language and click the Next button.
4. As a result, the New Design Wizard window is opened. To create a new design, type
mixed_tutorial as a name for the design in the Type the design name field.

Mixed VHDL-Verilog Tutorial

Advance to the next window by clicking the Next button.

5. To complete the wizard process click the Finish button in the last wizard window.
6. The Design Browser window contains an empty mixed_tutorial project along with a working
library named by default after the design.

VHDL Model
7. Double-click the Add New File label in the Design Browser window. This will open the Add
New File window where you need to switch to the Wizards tab and select the VHDL Source
Code Wizard.
Accept your choice with the OK button.
8. As a result, the New Source File Wizard window appears. Make sure that the Add the
generated file to design field is checked and click the Next button.
9. Now you have to enter the name of the file and optionally enter the entity and architecture
names as well. In the Type the name of source file to create field type counter and advance to
the next step by clicking the Next button.

Mixed VHDL-Verilog Tutorial

10. The next window lets you specify the ports of the model being generated. To add a new
model port, click the New button and type its name in the Name field. To choose the port
direction, select the appropriate one in the Port part of the window. Then, create the following
ports:

clk - 1-bit input

reset - 1-bit input
Q[3:0] - 4-bit output

When creating buses you can set their width by clicking on the Array Indexes arrows.
The figure below shows all created ports.

When you finish adding the model's ports, click the Finish button to end the wizard process.
11. The generated VHDL source is automatically loaded to the HDL Editor window.

Before you complete the next step, place the editing cursor below the -- enter your
statements here -- line.

Mixed VHDL-Verilog Tutorial

12. Active-HDL comes with a Language Assistant, which is a tool for inserting templates and
language constructs into the source code. To open the Language Assistant window click the
button located in the main toolbar.

In the Language Assistant window, expand the Tutorial branch and choose the Counter
template as shown in the figure. To place the selected template in your code, click the Use
template

button.

13. As you can see in the following figure, a process with a counter description has been
automatically inserted in the HDL Editor window.

14. To compile the prepared source without any error messages, you need to add the following
clause after the IEEE library declaration:
use IEEE.std_logic_unsigned.all;
After completing this operation, the HDL Editor contents should look as shown below.

Mixed VHDL-Verilog Tutorial

15. Now the source code is complete and ready for compilation. To compile any source code,
click the Compile
button located in the main toolbar. Successful compilation is indicated in
the Design Browser by a green check mark next to the file name. As you can notice in the figure
below, a successfully compiled file can be expanded and has an entity-architecture pair attached
to it. Additionally, the elaborated code is placed in the working library.

Verilog Module
16. At this stage you will expand your design by a code converter written in Verilog. To do so,
double-click the Add New File label in Design Browser. In the opened window, choose the
Verilog Source Code option and type hex2led name in the Name field. Accept the choices with
the OK button.

17. This will open an empty HDL Editor window. The complete converter's code is located in the
Language Assistant window. To open it, click the
button located in the main toolbar. Select
Verilog Language to view templates written in Verilog. Expand the Synthesis templates branch
and locate the HEX2LED Converter as shown in the figure below.

Mixed VHDL-Verilog Tutorial

Click the Insert template

button to place the selected template in the source file. Then add
the `timescale 1ps / 1ps directive at the beginning of the code.
18. The contents of the HDL Editor window after the converter's code insertion should look as
follows.

19. Now, compile the file using the Compile

button.

20. Successful compilation is marked by a green check mark next to the hex2led.v file in the
Design Browser and the appropriate message is displayed in the Console window. The
elaborated source is also placed in the design library.

Top-Level Schematic
21. To bind the VHDL and Verilog descriptions together you will utilize the Block Diagram Editor.
To add a new file to the project, double-click the Add New File label in Design Browser. In the
Add New File window, choose the Wizards tab and select the Block Diagram Wizard option.
Accept your choices with the OK button.
22. This will launch the New Source File Wizard. Make sure that the Add the generated file to
the design field is checked and click the Next button.
23. Choose the VHDL as the target language and click the Next button.

Mixed VHDL-Verilog Tutorial

24. In the next window, type top in the Type the name of the source file to create field and
select Next.

25. The next window lets you specify the ports of the model being generated. To add a new
model port, click the New button and type its name in the Name field. To choose the port
direction, select the appropriate one in the Port part of the window.
With this in mind, create the following ports:

CLK - 1 bit input

RESET - 1 bit input
Output[6:0] - 7 bit output

When creating buses, you can set their width by clicking on the Array Indexes buttons.
The figure below shows all created ports.

26. After clicking the Finish button, the Design Browser window displays a new top.bde file.

Mixed VHDL-Verilog Tutorial

27. This file is also automatically opened in the Block Diagram Editor. As you can see, all created
ports have already been placed on the diagram.

28. First, you will place the symbols of the previously created components. Each compiled source
file is given a symbol representation for its usage with block diagrams. To open the Symbol
button located in the main toolbar. As
Toolbox window, use the Show Symbols Toolbox
you can see in the figure below, this window contains symbols for the VHDL counter and Verilog
converter.

29. To place the symbol on the schematic, drag it from the Symbol Toolbox and drop it within
the diagram area. Using this technique, place the counter and converter symbols as shown in the
figure below.

Mixed VHDL-Verilog Tutorial

30. To draw a single connection between components, use the Wire

button located in the
Block Diagram Editor toolbar. Click this button and draw the wires between the CLK and RESET
pins of the counter and input terminals. To draw a wire, anchor one of its ends at the source pin
and drag it to the desired location by clicking the remaining pin. The connections of the symbols
are shown below.

31. To draw buses, use the Bus

button located in the Block Diagram Editor toolbar. After
clicking it, draw the connection between the converter and counter symbols. Next create a
connection between the converter's output and output terminal as shown in the figure.

32. In this step, you will name the drawn connections. To do so switch to the Select mode,
double click the bus connecting the converter and the OUTPUT(6:0) terminal. In the Bus
Properties window type the bus1 name in the Segment field. In the Index range field, set the
width to 6 downto 0.

Mixed VHDL-Verilog Tutorial

Accept the changes with the OK button.

33. As you can see in the figure below, a new bus1(6:0) name appears above the bus
connection.

34. Similarly, name the bus connecting the counter and converter. Type the bus0 in the Segment
field. Next, change the names of the wires connecting the input terminals and the counter to
CLK_IN and RESET_IN, respectively.

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35. At this point, the diagram is ready for compilation. Click the Compile
toolbar.

button in the main

As you can see in the Design Browser window, a corresponding VHDL file has been generated
for the block diagram description.

Simulation
36. Before you can simulate the design, you need to set the top-level unit. To do so, expand the
top.bde branch until you see the top(top) entity/architecture pair. Right-click its name and choose
the Set as Top-Level option from the pop-up menu.

As a result, the selected top-level pair is displayed in bold.

37. To start the simulation, choose Initialize Simulation from the Simulation menu. Now, open a
new Waveform window by clicking the New Waveform

button in the main toolbar.

38. To add signals for simulation, go to the Design Browser window and click the top branch as
shown in the figure.

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Mixed VHDL-Verilog Tutorial

Notice that the lower part of the window lists all signals visible from the highest hierarchy level.
39. To place them in the Standard Waveform Editor window, click the top branch and while
holding down the left mouse button drag them over the Waveform Editor. Drop them anywhere
within the window. This will add all signals as shown in the following figure.

40. To force the signals with the defined test vectors, right-click the CLK signal and choose the
Stimulators option from the pop-up menu.

41. In the Stimulators window, choose the Clock stimulator type in the Type list. After entering
the 10MHz value in the Frequency field click the Apply button.

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Mixed VHDL-Verilog Tutorial

42. Leaving the window open, click the RESET signal in the Waveform Editor window. Assign the
Formula stimulator for this signal in the Type list. Next, type the following line in the Enter
formula filed:
1 0, 0 50 ns
Apply changes using the Apply button.

Close the window with the Close button.

43. Type the 1000ns in the simulation duration field located next to the Run For button.

44. After advancing the simulation with the Run For

resemble the ones shown in the figure below.

button, the simulation results should

45. The design created in the Block Diagram has been compiled and simulated based on the
VHDL language. It is also possible to recompile it into Verilog code.
To do so switch back to the top.bde file either by clicking the top.bde tab or double-clicking the
top.bde name in the Design Browser window. Next, choose the Set Target HDL option from the
Diagram menu. Choose the Verilog option in the open window and accept it with the OK button.

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Mixed VHDL-Verilog Tutorial

46. Recompile the diagram using the Compile

button or use the F11 function keyboard key.
The result of compilation is shown below. Notice that there is a new top.v Verilog file attached to
the top.bde branch.

47. This time choose the top module as the Top-Level unit. To do so right-click its name and
choose the Set as Top-Level option from the pop-up menu.

48. After selecting the Initialize Simulation option from the Simulation menu, switch to the
Waveform Editor window by clicking the appropriate tab. Right-click the CLK signal and choose
the Stimulators option from the pop-up menu.

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49. In the Stimulators window, click the Apply button to accept the default settings and click the
RESET signal without closing the window. Hit the Apply button once again and click the Close
button to finish assigning stimulators.

50. Observe the simulation results by clicking the Run For

button several times. Notice that
there are no differences between the VHDL and Verilog simulation runs.

51. Simultaneously, the Block Diagram Editor displays the simulation results next to the names
of all signals added for the simulation.

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Thank You for using Active-HDL!

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