ICGST-PDCS Journal, Volume 9, Issue 1, October 2009
A DESIGN FOR AN FPGA IMPLEMENTATION OF RIJNDAEL
CIPHER
M.B. Abdelhalim*, H. K. Aslan**, A. Mahmoud** and H. Farouk**
* Arab Academy of Science and Technology and Maritime Transport, Cairo, Egypt,
** Electronics Research Institute, Cairo, Egypt.
m_bakr@aucegypt.edu, hebaaslan@yahoo.com, tobal51000@yahoo.com, heshamali68@hotmail.com
Abstract
Our aim is to simulate the Rijndael cipher using Field
Programmable Gate Array (FPGA) to achieve low
cost, ease of implementation, availability “FPGAs
can be bought off the shelf“, high flexibility including
capability of frequent modifications of hardware, and
low cost of the final product. We propose a modified
implementation of Rijndael, the Advanced
Encryption Standard (AES) based on the fact that any
FPGA includes built in memory block where we store
all the results of the fixed operations. The
modification gives an 11% reduction in area and 25%
increase in speed (throughput) compared with the
original design. Our design gives the highest
throughput and area utilization over all the Iterative
Looping (IL) based FPGA implementations. In the
original design, the decryption algorithm was not
implemented. Our implementation of the decryption
algorithm gives better results than the other IL based
FPGA implementations.
Keyword: Rijndael cipher, FPGA, memory block,
encryption, decryption.
1. Introduction
For a long period of time, the Data Encryption
Standard (DES) was considered a standard for the
symmetric key encryption. DES has a key length of
56 bits. For the time being, this key length is
considered small and can easily be broken. For this
reason, the National Institute of Standards and
Technology (NIST) announced as a result of
computation among 15 algorithms that the Rijndael
cipher will replace the DES cipher and will become a
new AES. The Rijndael cipher has three possible
block and key lengths: 128, 192, or 256 bits.
Therefore, the problem of breaking the key becomes
more difficult [1-2].
In general, hardware implementations of encryption
algorithms and their associated key schedules are
physically secure, as they cannot easily be modified
by an outside attacker. Also, the high speed Rijndael
9
encryptor core should prove beneficial in applications
where speed is important as with real-time
communications such as SONET OC-48 networks and
satellite communications.
The National Security Agency (NSA) evaluation plan
targets only implementations using semi-custom
Application Specific Integrated Circuits (ASICs)
providing no data regarding other technologies. FPGA
devices are assumed better alternative for such
implementations for many reasons as FPGA devices
have the following advantages over the ASICs:
1- Shorter design cycle leading to fully
functioning device prototypes.
2- Lower cost of the computer aided tools,
verification and testing.
3- Potential for fast, low cost multiple
reprogramming and experimental
testing of a large number of various
architectures and revised versions of
the same architecture.
A team from the University of California, Los
Angeles demonstrated in [3] an implementation of the
Rijndael cipher on Xilinx Virtex II XC2V1000-4
device using experimental frequency of 75 MHz,
throughput 739 Mbit/s for 128 bits.
Máire McLoone, John V and McCanny described in
[4] their FPGA implementation, which employed
fully pipelined single-chip Rijndael design and runs at
a data rate of 7 Gbits/sec on a Xilinx Virtex-E
XCV812E-8-BG560 FPGA device. The decryptor
design also achieves a fast throughout of 6.4
Gbits/sec.
Viktor Fischer and Milos Drutarovsk in [5] have
implemented Rijndael cipher using 128-bit keys
implemented in Altera ACEX reconfigurable
hardware, which has been found to be an excellent
solution for cost-sensitive encryption applications.
Kenneth Stevens and Otmane Ait Mohamed have
demonstrated in [6] a single-chip FPGA design of the
Rijndael encryption algorithm. The design employed
two 32-bit DSP cores to reduce the latency issues
 ICGST-PDCS Journal, Volume 9, Issue 1, October 2009
while a block cipher was implemented using the
Electronic Code Book mode of operation knowing
that the design focuses on a memory-based, byte-
sized arithematic pipeline structure that processes one
round at a time. The design provides a throughput
rate of 0.1 Gbps per data channel.
UCL Crypto Group, Laboratoire de
Micro´electronique gave in [7] a good solution for
applications, which need low area for implementation
like embedded systems where the rate of data transfer
is not the main concern. Such implementations use
FPGA Families like (Xilinx Virtex-II, Xilinx Spartan-
3 XC3S50).
M. C. Liberatori and J. D. Bonadero proposed in [8] a
low-cost solution to deal with the sub-keys computed
during the decryption step while merging the key
schedule and the data path parts which makes it
practical for cryptographic embedded applications.
In this paper, we propose a modified implementation
of Rijndael cipher using FPGA. Based on the fact that
any FPGA includes built in memory block, we store
all the results of the fixed operations within the
memory modules. In order to achieve this goal, we
first implement the algorithm using C language. This
step guides us through the FPGA design and helps us
in the optimization of the proposed design and in
obtaining the results of the fixed operation.
The present paper is organized as follows: in
Section2, description of Rijndael cipher is given.
Then, in Section 3, a description of the proposed
design for Very high speed integrated circuits
Hardware Description Language (VHDL)
implementation of Rijndael encryption function is
detailed. In Section 4, a description of the proposed
design for VHDL implementation of Rijndael
decryption function is detailed. Then, in Section 5, a
comparison of the proposed design with other FPGA
designs is illustrated. Finally, the paper concludes in
Section 6.
2. Description of Rijndael Cipher
The Rijndael is a block cipher, which operates on
different keys and block lengths: 128 bits, 192 bits, or
256 bits. The input to each round consists of a block
of message called the state and the round key. It has
to be noted that the round key changes in every
round. The state can be represented as a rectangular
array of bytes. This array has four rows; the number
of columns is denoted by Nb and is equal to the block
length divided by 32. The same could be applied to
the cipher key. The number of columns of the cipher
key is denoted by Nk and is equal to the key length
divided by 32. The cipher consists of a number of
rounds - that is denoted by Nr - which depends on
both block and key lengths. Each round of Rijndael
encryption function consists mainly of four different
transformations: ByteSub, ShiftRow, Mix-Column
10
and key addition. On the other hand, each round of
Rijndael decryption function consists mainly of four
different transformations: InvByteSub, InvShiftRow,
InvMix-Column, and key addition. For a detailed
description of each round transformations, the reader
could refer to [1-2]. The output of the above
transformations is called the 'state'. The state consists
of the same byte length as each block of the message.
The description of the four transformations of the
Rijndael cipher and their inverses will be given
below.
ByteSub Transformation: The ByteSub transformation
is a non-linear byte substitution, operating on each of
the state bytes independently. The ByteSub
transformation is done using a once-pre-calculated
substitution table called S-box. That S-box table
contains 256 numbers (from 0 to 255) and their
corresponding resulting values. For more details of
the method of calculating the S-box table refer to
[1- 2].
InvByteSub Transformation: The InvByteSub
transformation is done using a once-pre-calculated
substitution table called InvS-box. That table (or
InvS-box) contains 256 numbers (from 0 to 255) and
their corresponding values.
ShiftRow Transformation: In ShiftRow
transformation, the rows of the state are cyclically left
shifted over different offsets. Row 0 is not shifted;
row 1 is shifted over one byte; row 2 is shifted over
two bytes and row 3 is shifted over three bytes.
InvShiftRow Transformation: In InvShiftRow
transformation, the rows of the state are cyclically
right shifted over different offsets. Row 0 is not
shifted, row 1 is shifted over one byte, row 2 is shifted
over two bytes and row 3 is shifted over three bytes.
Mix-Column Transformation: In Mix-Column, the
columns of the state are considered as polynomials
multiplied by a fixed polynomial c(X), given by:
c(X)=’03’X3 + ‘01’X2 + ‘01’X + ‘02’. The Mix-
Column transformation can be written in a matrix
multiplication as follows (equation 1):
⎡d 0, j ⎤ ⎡02 03 01 01⎤ ⎡c 0, j ⎤
⎢d ⎥ ⎢ ⎢ ⎥
⎢ 1, j ⎥ = ⎢ 01 02 03 01⎥⎥ ⎢ c1, j ⎥ (1)
⎢d 2, j ⎥ ⎢ 01 01 02 03⎥ ⎢c 2, j ⎥
⎢ ⎥ ⎢ ⎥⎢ ⎥
⎢⎣d 3, j ⎥⎦ ⎣03 01 01 01⎦ ⎢⎣c 3, j ⎥⎦
Where the matrix ‘c’ represents the input to the Mix-
Column transformation and the matrix ‘d’ represents
the output of the Mix-Column transformation. Both
‘c’ and ‘d’ have a length of 32 bits.
InvMix-Column Transformation: In InvMix-Column,
the columns of the state are considered as polynomials
 ICGST-PDCS Journal, Volume 9, Issue 1, October 2009

multiplied by a fixed polynomial d(x), given by: round_constant: it goes to the key schedule layer to
d(x)=’0B’x3 + ‘0D’x2 + ‘09’x + ‘0E’. The InvMix- indicate which round is running at the moment and it
Column transformation can be written in a matrix applies a constant value according to the running
multiplication form (equation 2) : round

⎡ b 0, j ⎤ ⎡ 0E 0B 0D 09 ⎤ ⎡a 0, j ⎤
⎢ ⎥ ⎢ ⎥⎢ ⎥
⎢ b1, j ⎥ ⎢ 09 0E 0B 0D ⎥ ⎢ a1, j ⎥ (2)
⎢b ⎥=⎢ ⎥ ⎢a ⎥
⎢ 2, j ⎥ ⎢0D 09 0E 0B ⎥ ⎢ 2, j ⎥
⎢ b 3, j ⎥ ⎣ 0B 0D 09 0E ⎦ ⎢a 3, j ⎥
⎣ ⎦ ⎣ ⎦

Where the matrix ‘a’ represents the input to the

InvMix-Column transformation and the matrix ‘b’
represents the output of the InvMix-Column
transformation. Both ‘a’ and ‘b’ have a length of 32
bits.

AddKey Transformation: The round key is applied to

the state - resulted from the operation of the Mix- Figure 1: Block Diagram of Encryption Module
Column transformation - by a simple bitwise X-OR.
The round key length is equal to the block length. 3.2. Key Generator: This block is responsible for
[1-2] contain information about how to calculate the creating the keys for each round as shown in Figure 2.
round key from the secret key. In the next section, a It contains four S boxes.
description of the proposed design for VHDL
implementation of Rijndael encryption function is
detailed.

3. VHDL Implementation of Rijndael

Encryption Function
In [9], FPGA implementation of Rijndael encryption
function using VHDL (the case where Nb=4 and
Nk=4) was designed. This implementation is based
on performing Mix-Column transformation using
shifts and X-OR operations. Since Mix-Column
transformation is a fixed transformation, therefore
look-up tables could be used to execute it. This will
lead to obtain a higher throughput. We enhance the
design proposed in [9] by using look-up tables for
both Mix-Column and SubByte transformations. The
components needed to implement the encryption
function of AES are shown in Figure 1. Figure 1 Figure 2. Block Diagram of key_schedule Module
contains the following components:

3.1. The controller
This block controls the sequencing operations of the
rounds. It generates the round constant associated
with each round. It also generates the control signal at
the appropriate time, those control signals are:
key_reg_mux_sel: The key schedule input selector
which selects the input key before the first round, and
then it reads the output key as the next input.
load_key_reg: The key schedule output enable.
load_data_reg: The input register enable.
data_reg_mux_sel : The data register selector which
selects input register data from the plaintext input,
round0 output which is the X-OR between key zero
and the plaintext input, or the round layers outputs.
last_mux_sel: it goes to the round layer to indicate
the last round.
3.3. The round layers: This block represents the
rounds as shown in Figure 3.
It contains the row shifter followed by two blocks
running in parallel. The first one is Mix-Column
block combined with an S-Box block, and the second
one is S-Box block. The first block calls four look-up
tables to calculate its output. The second block is the
normal S-Box block. The final output is taken from S-
Box combined with Mix-Column block except for the
final case where the output is taken directly from S-
Box block using last_mux_sel signal. Then, an X-OR
function is applied with the round key.

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 ICGST-PDCS Journal, Volume 9, Issue 1, October 2009
e_in
Shift Row
S Box S Box + Mix Column
last_round_mux_sel
Mux
Add Round Key
d_out
Figure 3: Block Diagram of the Round Module (encryption)
To test the system, a test bench is used. The test
bench applies encryption input pulse to trigger the
system, then it checks the output ciphertext if valid or
not. Another test bench is used to continuously apply
inputs (read from a file) to the system by applying
encrypt pulse each 13 clocks. It also generates the
reset and clock signals. In the next section, a
description of the proposed design for VHDL
implementation of Rijndael decryption function is
detailed.
4. VHDL Implementation of Rijndael
Decryption Function
The implementation of Rijndael decryption function
is similar to that of the encryption function except for
the following points:
- As the keys have to be read in reverse order, they
must be calculated prior to applying any input,
therefore they are stored in a stack-like buffer.
This buffer contains InvMix-Column block that is
used before storing the keys in the stack (for keys
1 to 9 only).
- The controller generates a new signal:
Figure 4: Block Diagram of decryption Module
write_key_reg which is used to enable the key
schedule - which is the same as the one used in the
12
encryption code - and enable writing into the stack
as shown in Figure 4.
The old load_key_reg is used to read from the stack
after calculating the keys. After the rounds has
finished, the controller will be in the idle state
waiting a new decrypt pulse (not the init state) to
prevent re-calculating the keys once again as they
have been already calculated and stored in the key
stack.
The round layers block uses the Inv-Sbox block in
parallel with the Inv-Mix-Column combined with
Inv-Sbox block. The Inv-Shift-Row block has
changed internally while its interface stays the same
as shown in Figure 5.
d_in
Inv Shift Row
Inv S Box Inv S Box +
Inv Mix
last round mux
Mux
Add Round Key
e_out
Figure 5. Block Diagram of Round Module (decryption)
To test the system, a test bench is used. The test bench
applies decryption input pulse to trigger the system,
then it checks the output plaintext if valid or not.
Another test bench is used to continuously apply
inputs (read from file) to the system by applying
encrypt pulse each 13 clocks. It also generates the
reset and clock signals. Note that the keys are
calculated once in the beginning of operation. To
change the keys, a reset signal must be asserted to
enable the load stack state to perform once again. The
simulation output of test vectors are given in
Appendix A.
5. Synthesis Results
To ensure that our modifications give a better results
in terms of area and speed than the original one [9],
we compare the two encryption codes (original and
modified). The comparison considered two criteria:
chip speed and area utilization. The design was
implemented on an ALTERA EP20K300EBC652
device. It has to be noted that in [9], no decryption
algorithm was proposed. Both designs were
synthesized using Leonardo Spectrum tool and
simulated using ModelSim tool. As shown in Table 1,
an increase in speed about 25% was achieved in our
design and a reduction in area about 11% was
 ICGST-PDCS Journal, Volume 9, Issue 1, October 2009

achieved in our design. On the other hand, since we The last step is to compare our decryption design with
use look-up tables to perform Mix-Column other design approaches. In [10] a design of
transformation, the new encryption design needs decryption module based on Altera FPGA is
more memory (as shown in Table 1), but this increase proposed. As shown in Table 3, our design
is not bad as it utilized the memory resources inside outperforms the design in [10] by a 84.21% reduction
the FPGA efficiently. For the sake of comparing the in area and 97.12% increase in speed with a price of
design with another Altera based designs, the design increased memory utilization.
in [10] is including in the table. The comparison
shows that the proposed design has a higher Table 3. Comparison Between the Altera Based Designs of
throughput compared to the design in [10]. the Decryption Module
Resource Used Available Utilization
Table 1. Comparison between the Altera Based Designs of
the Encryption Module IOs 387 408 94.85%
LCs 1494 16640 8.98%
Our design
Resource Used Available Utilization Memory Bits 169984 212992 79.81%
Speed 72.9 MHz
Ios 387 408 94.85%
Original IOs 387 408 94.85%
design [9] LCs 897 11520 7.79%
Memory Bits 40960 147456 27.78% Piotr [10] LCs 2885 11520 25.04%
Speed 81.2 MHz Memory Bits 40960 147456 27.78%
Ios 387 408 94.85% Speed 40.69 MHz
Modified
LCs 797 11520 6.92%
proposed
Design
Memory Bits 114688 147456 77.78% Note that the implementation in [10] needs 21 clock
Speed 99.1 MHz cycles to give a key compared to 13 clock cycles in
Ios 387 408 94.85% our design. The FPGAs used are EP20K300EBC652
LCs 1032 11520 8.96%
Piotr [10] in our design and EPF10K250AGC599-1 in [10].
Memory Bits 40960 147456 27.78%
Speed 44 MHz
We have to indicate that the new trends to implement
the AES employ VLSI (ASIC) and reconfigurable
Then, we compare our design with different designs.
architectures to improve the system efficiency by
A good comparison of the different designs
means of speed, power and size. Using such
implemented in xilinix FPGA chips could be found in
techniques to implement encryptors may achieve
[10]. To compare our work with those in [10], we
speeds up to 17.8 Gbps and more than ten times
implemented our design in xilinix XC2V2000 family
power efficient compared to field programmable gate
which has sufficient memory for our design. The
arrays implementations. Therefore, our modified
maximum core frequency was 80.5 MHz. Since each
algorithm could achieve higher throughput using such
round was finished in one clock cycle, plus two clock
techniques.
cycles for registering the inputs, 13 clock cycles were
needed in a 128-bit key design. As a result, the
throughput of the Rijndael core was 793.3 Mbit/sec 6. Conclusions
which could be improved to 937.6 Mbit/sec if the two In this paper we approved a modified implementation
registering cycles are performed in parallel. of Rijndael AES encryption standard based on the fact
Throughput calculated by other researches is listed that any FPGA includes built in memory block;
below in Table 2. therefore we store all the results of the fixed
operations within the memory modules. The
Table 2 Comparison of 128-bit Rijndael Encryption modification gives an 11% reduction in area and 25%
Implementations increase in speed (Throughput) compared with the
Design Device
Area Throughput original design. Our design gives the highest
(CLB) (Mbit/sec) throughput and area utilization over all the Iterative
Gaj [11] IL XCV1000BG560-6 2902 331.5
Looping based FPGA implementations. The
Dandalis [12] IL XCV1000 5673 353.0
Tong [13] IL XCV1000HQ240-6 702 755.1
decryption algorithm is implemented and gives better
Our design IL XC2V2000BF957-6 402 793.3 results than the design in [10].
Elbirt [14] P XCV1000BG560-4 10992 1937.9
McLoone[15] P XCV3200EBG560-8 7576 3239.0
McLoone[15] P XCV812EBG560-8 2222 6956.0

[KEY]: IL = Iterative Looping P = Pipelining

Table 2 shows that our design outperforms all designs
based on the iterative loops in terms of area and
throughput. While the pipelined approach gives much
higher throughput, it needs much more area than the
iterative loop approaches.

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 ICGST-PDCS Journal, Volume 9, Issue 1, October 2009

7. References Programmable Technology (FPT), Hong Kong,

[1] Daemen J., and Rijmen V., “AES proposal: pp. 102-109, 2002
Rijndael-The Rijndael Block Cipher”, A [14] A.J. Elbert, E. Yip, B. Chetwynd, C. Paar: An
Technical Report (Version 2) Presented to the FPGA Implementation and Performance
National Institute of Standards and Technology Evaluation of the AES Block Cipher Candidate
(NIST), 1999. Algorithm Finalists, IEEE Transactions on VLSI,
[2] Daemen J., and Rijmen V. "The Design of August 2001, vol. 9, no. 4, pp. 545-557.
Rijndael: AES-the Advanced Encryption [15] M. McLoone, J.V McCanny: High Performance
Standard". Springer-Verlag., 2002 Single-Chip FPGA Rijndael Algorithm
[3] Cristian Chit¸ua, Manfred Glesner, "An FPGA Implementations, CHES 2001, pp. 65-76.
implementation of the AES-Rijndael in [16] “Announcing the Advanced Encryption Standard
OCB/ECB modes of operation", (AES)” Federal Information Processing
Microelectronics Journal 36, pp139–146, 2004. Standards Publication 197, November 26, 2001.
[4] Máire McLoone , John V. McCanny, "Single-
Chip FPGA Implementation of the Advanced Appendix A: Simulation Results using
Encryption Standard Algorithm", G. Brebner and Test Vectors
R. Woods (Eds.): FPL 2001, LNCS 2147, pp. In [16], there are several test vectors for Nb = 4 and
152-161, 2001. Nk = 4, 6 and 8. The test vectors for the case where
[5] Viktor Fischer and Miloˇs Drutarovsky, "Two Nb = 4 and Nk = 4 are given below:
Methods of Rijndael Implementation in Plaintext: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd
Reconfigurable Hardware", LNCS 2162, pp. ee ff
77–92, 2001. Key: 00 01 02 03 04 05 06 07 08 09 0a 0b 0c
[6] Kenneth Stevens and Otmane Ait Mohamed, 0d 0e 0f
"Single-chip FPGA Implementation of a Ciphertext: 69 c4 e0 d8 6a 7b 04 30 d8 cd b7 80 70 b4
Pipelined, Memory-Based AES Rijndael c5 5a
Encryption Design", IEEE 2005. In Figures 6 and 7, the simulation outputs of the
[7] G. Rouvroy, F. Standaert, J. Quisquater and J. abovementioned test vectors of the encryption and
Legat, "Compact and Efficient decryption algorithms are given. The two figures
Encryption/Decryption Module for FPGA show that the outputs of both the encryption and
Implementation of the AES Rijndael VeryWell decryption functions are as stated in [9].
Suited for Small Embedded Applications",
Proceedings of the International Conference on
Information Technology: Coding and
Computing (ITCC’04), IEEE 2004.
[8] M. Liberatori and J. Bonadero, " AES-128
Cipher. Minimum Area, Low Cost FPGA
Implementation", Latin America Applied
Research, 37:71-77 , 2007
[9] http://islab.oregonstate.edu/koc/ece575/03Projec
t/Megarajan-Park.
[10] Piotr Mroczkowski, “Implementation of the
block cipher Rijndael using Altera FPGA”,
Public Comments on AES Candidate Algorithms
- Round 2, 2000.
[11] K. Gaj, P. Chodowiec: Comparison of the
Hardware Performance of the AES Candidates
using Reconfigurable Hardware: The Third
Advanced Encryption Standard Candidate
Conference, April 13-14, 2000, New York,
USA.
[12] A. Dandalis, V. K. Prasanna, J. D. P. Rolim: A
Comparative Study of Performance of AES
Candidates Using FPGAs: The Third Advanced
Encryption Standard Candidate Conference,
April 13-14, 2000, New York, USA.
[13] Dennis Ka Yau Tong, Pui Sze Lo, Kin Hong
Lee, Philip H.W. Leong, “A System Level
Implementation of Rijndael on a Memory-slot
based FPGA Card”, Proceedings of the 2002
IEEE International Conference on Field

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 ICGST-PDCS Journal, Volume 9, Issue 1, October 2009
Biographies:
Mohamed Bakr Abdelhalim
received his BSc, MSc and PhD
degrees in Electronics
Engineering from Cairo
University in 1999, 2003 and
2008 respectively. He was a
researcher at the Department of
Electrical and Communications
Engineering, Cairo University.
He was also a teaching and lab
assistant at the Electronics Engineering Department,
American University in Cairo. Currently he is an
assistant professor at the College of Computing and
Information Technology - Arab Academy for
Science, Technology and Maritime Transport.
His research interests are FPGA-based design,
System-level design and description languages, CAD
tools, and Soft computing techniques.
Dr. Heba K. Aslan is an
Associate Professor at the
Electronics Research Institute,
Cairo- Egypt. She received her
B. Sc., M. Sc. And Ph. D. from
Faculty of Engineering, Cairo
University in 1990, 1994 and
1998 respectively. Her research
interests include: Key Distribution Protocols,
Authentication Protocols, Logical Analysis of
Protocols and Intrusion Detection Protocols.
Figure 6. Simulation Output of the Encryption Function
Figure 7. Simulation Output of the Decryption Function
15
Dr. A. Tobal is an Associate
Prof. at the Electronics
Research Institute, Cairo,
Egypt. He received his B.
Sc., M. Sc. And Ph. D. from
Faculty of Engineering, Cairo
University in 1990, 1994 and
1999 respectively.
His fields of research include embedded systems
implementation, digital signal processing,
Biological Neural Network, pattern recognition and
Artificial Intelligence.
Dr. Farouk is an Assistant
Prof. He joined the Electronics
Research Institute, Egypt, in
1993. His fields of research
are signal processing, image
compression, video
processing, video
compression, video indexing
and retrieval, video on
demand, pattern recognition and machine vision.
Dr. Farouk received his Ph.D. at 2001 from
Electronics & Communications Dept., Faculty of
Engineering, Cairo Univ. and his M.Sc. at 1996
from Electronics & Communications Dept.,
Faculty of Engineering, Cairo Univ.